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TimeQuest Timing Analyzer report for spectrum
Fri Apr 1 18:55:48 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
17. Slow 1200mV 85C Model Hold: 'CLOCK_50'
18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
21. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
22. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
23. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
24. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
25. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
26. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
27. Setup Times
28. Hold Times
29. Clock to Output Times
30. Minimum Clock to Output Times
31. Propagation Delay
32. Minimum Propagation Delay
33. Slow 1200mV 85C Model Metastability Report
34. Slow 1200mV 0C Model Fmax Summary
35. Slow 1200mV 0C Model Setup Summary
36. Slow 1200mV 0C Model Hold Summary
37. Slow 1200mV 0C Model Recovery Summary
38. Slow 1200mV 0C Model Removal Summary
39. Slow 1200mV 0C Model Minimum Pulse Width Summary
40. Slow 1200mV 0C Model Setup: 'CLOCK_50'
41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
43. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
46. Slow 1200mV 0C Model Hold: 'CLOCK_50'
47. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
48. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
49. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
50. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
51. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
52. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
53. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
54. Setup Times
55. Hold Times
56. Clock to Output Times
57. Minimum Clock to Output Times
58. Propagation Delay
59. Minimum Propagation Delay
60. Slow 1200mV 0C Model Metastability Report
61. Fast 1200mV 0C Model Setup Summary
62. Fast 1200mV 0C Model Hold Summary
63. Fast 1200mV 0C Model Recovery Summary
64. Fast 1200mV 0C Model Removal Summary
65. Fast 1200mV 0C Model Minimum Pulse Width Summary
66. Fast 1200mV 0C Model Setup: 'CLOCK_50'
67. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
68. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
69. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
70. Fast 1200mV 0C Model Hold: 'CLOCK_50'
71. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
72. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
73. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
74. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
75. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
76. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
77. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
78. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
79. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
80. Setup Times
81. Hold Times
82. Clock to Output Times
83. Minimum Clock to Output Times
84. Propagation Delay
85. Minimum Propagation Delay
86. Fast 1200mV 0C Model Metastability Report
87. Multicorner Timing Analysis Summary
88. Setup Times
89. Hold Times
90. Clock to Output Times
91. Minimum Clock to Output Times
92. Propagation Delay
93. Minimum Propagation Delay
94. Board Trace Model Assignments
95. Input Transition Times
96. Signal Integrity Metrics (Slow 1200mv 0c Model)
97. Signal Integrity Metrics (Slow 1200mv 85c Model)
98. Signal Integrity Metrics (Fast 1200mv 0c Model)
99. Setup Transfers
100. Hold Transfers
101. Recovery Transfers
102. Removal Transfers
103. Report TCCS
104. Report RSKM
105. Unconstrained Paths
106. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; SDC File List ;
+--------------------------------------------------------------------------------+
SDC File Path : spectrum.sdc
Status : OK
Read at : Fri Apr 1 18:55:45 2022
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : beep
Type : Base
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { ula:ula_|beep }
Clock Name : CLOCK_50
Type : Base
Period : 20.000
Frequency : 50.0 MHz
Rise : 0.000
Fall : 10.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 39.716
Frequency : 25.18 MHz
Rise : 0.000
Fall : 19.858
Duty Cycle : 50.00
Divide by : 280
Multiply by : 141
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 71.489
Frequency : 13.99 MHz
Rise : 0.000
Fall : 35.744
Duty Cycle : 50.00
Divide by : 168
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Type : Generated
Period : 41.702
Frequency : 23.98 MHz
Rise : 0.000
Fall : 20.851
Duty Cycle : 50.00
Divide by : 98
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 49.07 MHz
Restricted Fmax : 49.07 MHz
Clock Name : CLOCK_50
Note :
Fmax : 124.66 MHz
Restricted Fmax : 124.66 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 161.45 MHz
Restricted Fmax : 161.45 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 938.97 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -18.123
End Point TNS : -549.338
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -7.533
End Point TNS : -284.813
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.740
End Point TNS : -42.810
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.914
End Point TNS : -2.914
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.210
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.344
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.357
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -6.223
End Point TNS : -459.348
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.698
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.488
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.602
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.595
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -18.123
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.954
Slack : -18.117
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.948
Slack : -18.075
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.905
Slack : -18.071
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.902
Slack : -18.067
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.897
Slack : -18.052
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.883
Slack : -18.038
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.868
Slack : -17.978
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.809
Slack : -17.977
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.803
Slack : -17.957
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.783
Slack : -17.929
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.760
Slack : -17.924
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.755
Slack : -17.912
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.472
Slack : -17.909
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.474
Slack : -17.904
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.735
Slack : -17.882
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.712
Slack : -17.861
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.692
Slack : -17.852
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.685
Slack : -17.852
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 7.684
Slack : -17.810
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.366
Slack : -17.798
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.631
Slack : -17.790
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 7.621
Slack : -17.747
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.297
Slack : -17.716
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.266
Slack : -17.709
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.535
Slack : -17.708
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.535
Slack : -17.700
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.533
Slack : -17.676
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.506
Slack : -17.657
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 7.487
Slack : -17.622
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.182
Slack : -17.617
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.443
Slack : -17.612
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.437
Slack : -17.578
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.404
Slack : -17.576
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.135
Slack : -17.567
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 7.136
Slack : -17.554
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.113
Slack : -17.492
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.046
Slack : -17.483
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.041
Slack : -17.477
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.303
Slack : -17.475
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.031
Slack : -17.460
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.293
Slack : -17.458
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.021
Slack : -17.448
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.281
Slack : -17.445
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 7.277
Slack : -17.442
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.268
Slack : -17.441
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 7.273
Slack : -17.429
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.980
Slack : -17.425
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.251
Slack : -17.393
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.943
Slack : -17.368
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.918
Slack : -17.351
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.902
Slack : -17.350
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.183
Slack : -17.328
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.891
Slack : -17.322
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.881
Slack : -17.316
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 6.883
Slack : -17.314
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.147
Slack : -17.300
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.850
Slack : -17.296
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.122
Slack : -17.274
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 7.106
Slack : -17.267
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 7.093
Slack : -17.247
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.808
Slack : -17.239
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 7.071
Slack : -17.229
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.241
Data Delay : 7.062
Slack : -17.199
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.751
Slack : -17.188
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 6.755
Slack : -17.162
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.720
Slack : -17.128
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 6.954
Slack : -17.120
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.680
Slack : -17.110
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 6.942
Slack : -17.095
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.519
Data Delay : 6.650
Slack : -17.083
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.635
Slack : -17.035
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 6.600
Slack : -16.837
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 6.391
Slack : -16.833
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.394
Slack : -16.800
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 6.627
Slack : -16.774
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.242
Data Delay : 6.606
Slack : -16.762
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.593
Slack : -16.756
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.587
Slack : -16.714
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.544
Slack : -16.710
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.541
Slack : -16.706
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.536
Slack : -16.702
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.260
Slack : -16.691
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.522
Slack : -16.677
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.507
Slack : -16.617
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.448
Slack : -16.616
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 6.442
Slack : -16.596
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 6.422
Slack : -16.590
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.421
Slack : -16.589
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.420
Slack : -16.568
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.399
Slack : -16.567
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.397
Slack : -16.563
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.394
Slack : -16.549
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.379
Slack : -16.543
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.374
Slack : -16.523
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.354
Slack : -16.521
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.351
Slack : -16.500
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.331
Slack : -16.495
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.243
Data Delay : 6.326
Slack : -16.484
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_G[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.244
Data Delay : 6.314
Slack : -16.460
From Node : ula:ula_|video:video_|attr[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.248
Data Delay : 6.286
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -7.533
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 5.348
Slack : -7.427
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 5.251
Slack : -7.365
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 5.183
Slack : -7.307
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 5.131
Slack : -7.245
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 5.108
Slack : -7.233
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.307
Data Delay : 5.034
Slack : -7.228
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 5.085
Slack : -7.218
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 5.042
Slack : -7.217
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 5.042
Slack : -7.215
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.263
Data Delay : 5.060
Slack : -7.206
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 5.015
Slack : -7.130
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.993
Slack : -7.122
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.282
Data Delay : 4.948
Slack : -7.122
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.988
Slack : -7.092
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.956
Slack : -7.063
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.879
Slack : -7.057
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.868
Slack : -7.054
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 4.863
Slack : -7.052
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.903
Slack : -7.042
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 4.851
Slack : -7.025
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.884
Slack : -7.023
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.848
Slack : -7.020
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.866
Slack : -7.020
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 4.847
Slack : -7.017
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.865
Slack : -7.009
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 4.832
Slack : -7.002
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.868
Slack : -6.982
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 4.795
Slack : -6.955
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 4.776
Slack : -6.943
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 5.042
Slack : -6.934
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.788
Slack : -6.930
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.755
Slack : -6.927
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.274
Data Delay : 4.761
Slack : -6.927
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.276
Data Delay : 4.759
Slack : -6.914
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.739
Slack : -6.912
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 4.779
Slack : -6.876
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.247
Data Delay : 4.737
Slack : -6.862
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.725
Slack : -6.861
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.720
Slack : -6.857
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.705
Slack : -6.837
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.945
Slack : -6.836
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.267
Data Delay : 4.677
Slack : -6.834
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 4.653
Slack : -6.811
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 4.628
Slack : -6.810
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.647
Slack : -6.806
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 4.629
Slack : -6.804
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.240
Data Delay : 4.672
Slack : -6.798
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.253
Data Delay : 4.653
Slack : -6.792
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 4.659
Slack : -6.791
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 4.612
Slack : -6.789
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.232
Data Delay : 4.665
Slack : -6.789
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.234
Data Delay : 4.663
Slack : -6.781
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.253
Data Delay : 4.636
Slack : -6.770
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.269
Data Delay : 4.609
Slack : -6.768
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.275
Data Delay : 4.601
Slack : -6.765
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.619
Slack : -6.761
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.286
Data Delay : 4.583
Slack : -6.756
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.571
Slack : -6.756
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.999
Data Delay : 4.865
Slack : -6.751
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.588
Slack : -6.748
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.599
Slack : -6.745
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.605
Slack : -6.745
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.250
Data Delay : 4.603
Slack : -6.741
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 4.564
Slack : -6.739
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.835
Slack : -6.737
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.553
Slack : -6.727
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.543
Slack : -6.720
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 4.547
Slack : -6.717
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.825
Slack : -6.714
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.578
Slack : -6.714
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.525
Slack : -6.693
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.792
Slack : -6.692
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.556
Slack : -6.689
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 4.558
Slack : -6.683
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.511
Slack : -6.681
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 4.487
Slack : -6.678
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.493
Slack : -6.678
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 4.491
Slack : -6.674
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 4.487
Slack : -6.658
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.261
Data Delay : 4.505
Slack : -6.655
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.466
Slack : -6.646
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.471
Slack : -6.641
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.266
Data Delay : 4.483
Slack : -6.638
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.482
Slack : -6.629
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.457
Slack : -6.629
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.473
Slack : -6.627
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.999
Data Delay : 4.736
Slack : -6.620
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.485
Slack : -6.614
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.272
Data Delay : 4.450
Slack : -6.604
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.433
Slack : -6.602
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 4.454
Slack : -6.591
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 4.418
Slack : -6.588
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.278
Data Delay : 4.418
Slack : -6.573
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.427
Slack : -6.572
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.436
Slack : -6.561
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.426
Slack : -6.546
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.362
Slack : -6.533
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.389
Slack : -6.514
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.379
Slack : -6.514
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.368
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.740
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 2.831
Slack : -4.581
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.799
Slack : -4.581
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.799
Slack : -4.362
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.580
Slack : -4.362
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.580
Slack : -4.362
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.580
Slack : -4.362
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.580
Slack : -4.362
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.580
Slack : -3.957
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.175
Slack : -3.141
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.170
Data Delay : 1.690
Slack : 16.840
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.577
Slack : 16.845
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.572
Slack : 16.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.439
Slack : 16.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.439
Slack : 16.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.434
Slack : 16.983
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.434
Slack : 16.986
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.431
Slack : 17.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.366
Slack : 17.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.366
Slack : 17.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.366
Slack : 17.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.366
Slack : 17.056
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.361
Slack : 17.056
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.361
Slack : 17.056
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.361
Slack : 17.056
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.361
Slack : 17.086
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.331
Slack : 17.117
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.300
Slack : 17.117
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.300
Slack : 17.140
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.277
Slack : 17.140
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.277
Slack : 17.145
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.272
Slack : 17.145
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.272
Slack : 17.159
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.256
Slack : 17.159
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.256
Slack : 17.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.251
Slack : 17.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.251
Slack : 17.189
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.228
Slack : 17.189
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.228
Slack : 17.189
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.228
Slack : 17.189
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.228
Slack : 17.224
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.193
Slack : 17.224
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.193
Slack : 17.256
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.161
Slack : 17.259
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.158
Slack : 17.259
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.158
Slack : 17.259
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.158
Slack : 17.259
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.158
Slack : 17.259
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.158
Slack : 17.264
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.153
Slack : 17.264
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.153
Slack : 17.264
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.153
Slack : 17.264
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.153
Slack : 17.264
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.153
Slack : 17.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.128
Slack : 17.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.128
Slack : 17.297
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.120
Slack : 17.297
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.120
Slack : 17.297
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.120
Slack : 17.297
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.120
Slack : 17.308
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.107
Slack : 17.308
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.107
Slack : 17.386
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.031
Slack : 17.386
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.031
Slack : 17.394
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.023
Slack : 17.394
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.023
Slack : 17.405
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.010
Slack : 17.405
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.010
Slack : 17.408
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.009
Slack : 17.408
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.009
Slack : 17.408
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.009
Slack : 17.408
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.009
Slack : 17.408
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 3.009
Slack : 17.432
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.983
Slack : 17.437
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.978
Slack : 17.467
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.950
Slack : 17.467
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.950
Slack : 17.467
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.950
Slack : 17.467
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.950
Slack : 17.501
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.916
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.912
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.912
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.912
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.912
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.912
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.861
Slack : 17.556
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.861
Slack : 17.563
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.076
Data Delay : 3.207
Slack : 17.568
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.076
Data Delay : 3.202
Slack : 17.575
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.840
Slack : 17.575
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.840
Slack : 17.581
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.834
Slack : 17.639
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.778
Slack : 17.639
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.778
Slack : 17.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.742
Slack : 17.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.742
Slack : 17.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.742
Slack : 17.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.742
Slack : 17.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.429
Data Delay : 2.742
Slack : 17.678
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.737
Slack : 17.710
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.076
Data Delay : 3.060
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.914
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.216
Data Delay : 1.508
Slack : 70.424
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.982
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.210
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.627
Data Delay : 3.128
Slack : 0.266
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.628
Data Delay : 3.185
Slack : 1.266
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.574
Data Delay : 4.131
Slack : 1.277
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.575
Data Delay : 4.143
Slack : 1.289
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.571
Data Delay : 4.151
Slack : 1.310
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.163
Slack : 1.311
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.164
Slack : 1.311
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.574
Data Delay : 4.176
Slack : 1.313
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.162
Slack : 1.318
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.174
Slack : 1.328
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.575
Data Delay : 4.194
Slack : 1.332
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.185
Slack : 1.333
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.189
Slack : 1.370
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.226
Slack : 1.390
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.241
Slack : 1.397
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.245
Slack : 1.404
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.567
Data Delay : 4.262
Slack : 1.406
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.251
Slack : 1.412
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 4.252
Slack : 1.417
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.261
Slack : 1.418
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.271
Slack : 1.422
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.275
Slack : 1.426
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.268
Slack : 1.427
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.280
Slack : 1.431
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.291
Slack : 1.438
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.291
Slack : 1.443
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.285
Slack : 1.446
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.297
Slack : 1.449
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.302
Slack : 1.455
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.306
Slack : 1.456
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.305
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.304
Slack : 1.470
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.571
Data Delay : 4.332
Slack : 1.472
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.314
Slack : 1.474
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 4.314
Slack : 1.474
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.318
Slack : 1.476
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.625
Data Delay : 4.392
Slack : 1.477
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.322
Slack : 1.479
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.649
Data Delay : 4.419
Slack : 1.483
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.336
Slack : 1.489
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.571
Data Delay : 4.351
Slack : 1.492
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.633
Data Delay : 4.416
Slack : 1.496
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.340
Slack : 1.496
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.342
Slack : 1.497
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.567
Data Delay : 4.355
Slack : 1.499
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.347
Slack : 1.502
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.378
Data Delay : 4.171
Slack : 1.505
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.358
Slack : 1.507
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.355
Slack : 1.508
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.368
Slack : 1.509
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.354
Slack : 1.512
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.365
Slack : 1.517
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.368
Slack : 1.517
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.362
Slack : 1.519
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.379
Slack : 1.522
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.632
Data Delay : 4.445
Slack : 1.523
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.365
Slack : 1.525
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.367
Slack : 1.525
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 4.365
Slack : 1.525
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.381
Slack : 1.527
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.380
Slack : 1.528
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.382
Slack : 1.529
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.571
Data Delay : 4.391
Slack : 1.531
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.645
Data Delay : 4.467
Slack : 1.531
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.374
Slack : 1.532
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.380
Slack : 1.533
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.641
Data Delay : 4.465
Slack : 1.533
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.382
Slack : 1.534
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.376
Slack : 1.534
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.377
Slack : 1.538
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.390
Slack : 1.540
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.385
Slack : 1.542
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.568
Data Delay : 4.401
Slack : 1.543
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 4.383
Slack : 1.544
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.393
Slack : 1.545
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.574
Data Delay : 4.410
Slack : 1.547
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.407
Slack : 1.547
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.388
Slack : 1.547
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.392
Slack : 1.548
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.397
Slack : 1.549
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.405
Slack : 1.549
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.398
Slack : 1.551
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.405
Slack : 1.553
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.574
Data Delay : 4.418
Slack : 1.553
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.398
Slack : 1.555
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.575
Data Delay : 4.421
Slack : 1.555
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.409
Slack : 1.557
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 4.397
Slack : 1.558
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.412
Slack : 1.562
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.403
Slack : 1.563
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.416
Slack : 1.565
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.413
Slack : 1.565
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.367
Data Delay : 4.223
Slack : 1.567
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.416
Slack : 1.569
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.422
Slack : 1.572
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.429
Slack : 1.578
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.432
Slack : 1.578
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.431
Slack : 1.579
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.428
Slack : 1.580
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.425
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.576
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 1.324
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.636
Data Delay : 1.190
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.344
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.346
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.580
Slack : 0.347
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.580
Slack : 0.357
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.362
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.597
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.384
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.603
Slack : 0.384
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.603
Slack : 0.386
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.605
Slack : 0.399
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.618
Slack : 0.401
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.620
Slack : 0.463
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.698
Slack : 0.463
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.698
Slack : 0.464
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.699
Slack : 0.464
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.699
Slack : 0.466
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.701
Slack : 0.513
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.732
Slack : 0.515
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 0.732
Slack : 0.542
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.777
Slack : 0.544
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.779
Slack : 0.547
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.782
Slack : 0.548
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.106
Data Delay : 0.811
Slack : 0.554
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.773
Slack : 0.555
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.774
Slack : 0.555
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.790
Slack : 0.557
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.792
Slack : 0.558
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.777
Slack : 0.559
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.559
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.561
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.564
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.782
Slack : 0.567
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.787
Slack : 0.574
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.809
Slack : 0.574
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.809
Slack : 0.575
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.810
Slack : 0.575
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.164
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 0.577
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.812
Slack : 0.577
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.796
Slack : 0.580
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.799
Slack : 0.590
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.809
Slack : 0.590
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.809
Slack : 0.597
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.816
Slack : 0.604
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.823
Slack : 0.612
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.831
Slack : 0.613
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.832
Slack : 0.627
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.846
Slack : 0.636
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.855
Slack : 0.639
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.858
Slack : 0.680
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.899
Slack : 0.686
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.905
Slack : 0.703
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.922
Slack : 0.747
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 0.611
Slack : 0.763
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 0.984
Slack : 0.764
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 0.985
Slack : 0.771
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 0.992
Slack : 0.780
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.999
Slack : 0.785
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.004
Slack : 0.786
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.005
Slack : 0.788
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.008
Slack : 0.799
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.018
Slack : 0.808
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.028
Slack : 0.814
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.033
Slack : 0.817
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.052
Slack : 0.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.053
Slack : 0.831
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.050
Slack : 0.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.066
Slack : 0.832
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.051
Slack : 0.832
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.051
Slack : 0.833
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.699
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.834
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.069
Slack : 0.835
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.069
Slack : 0.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.070
Slack : 0.836
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.071
Slack : 0.845
From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.064
Slack : 0.848
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.850
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.069
Slack : 0.852
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.071
Slack : 0.854
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.073
Slack : 0.854
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.073
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.549
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.768
Slack : 0.553
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.772
Slack : 0.563
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.570
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.789
Slack : 0.657
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.876
Slack : 0.728
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.948
Slack : 0.821
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.047
Slack : 0.824
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.043
Slack : 0.840
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.059
Slack : 0.841
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.060
Slack : 0.843
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.062
Slack : 0.860
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.080
Slack : 0.919
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.138
Slack : 0.934
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.153
Slack : 0.953
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.172
Slack : 0.967
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.193
Slack : 0.980
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.206
Slack : 1.030
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.253
Slack : 1.074
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.299
Slack : 1.074
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.299
Slack : 1.077
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.302
Slack : 1.078
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.303
Slack : 1.111
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 0.968
Slack : 1.117
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.343
Slack : 1.118
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.344
Slack : 1.129
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.355
Slack : 1.140
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 0.997
Slack : 1.143
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 1.000
Slack : 1.151
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 1.008
Slack : 1.159
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.385
Slack : 1.193
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.412
Slack : 1.195
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.414
Slack : 1.201
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.427
Slack : 1.241
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.467
Slack : 1.248
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.474
Slack : 1.262
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.482
Slack : 1.265
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.485
Slack : 1.265
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.485
Slack : 1.265
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.485
Slack : 1.265
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.485
Slack : 1.269
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.495
Slack : 1.279
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.505
Slack : 1.281
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 1.138
Slack : 1.281
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.507
Slack : 1.291
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.511
Slack : 1.291
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.512
Slack : 1.296
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.328
Data Delay : 1.125
Slack : 1.299
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 1.156
Slack : 1.305
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.524
Slack : 1.310
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.529
Slack : 1.312
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.531
Slack : 1.314
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.540
Slack : 1.316
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.542
Slack : 1.323
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.328
Data Delay : 1.152
Slack : 1.339
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.328
Data Delay : 1.168
Slack : 1.342
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.329
Data Delay : 1.170
Slack : 1.351
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.577
Slack : 1.355
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.575
Slack : 1.360
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.329
Data Delay : 1.188
Slack : 1.378
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.604
Slack : 1.380
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.606
Slack : 1.387
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.610
Slack : 1.391
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.617
Slack : 1.398
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.621
Slack : 1.405
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.631
Slack : 1.406
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.626
Slack : 1.407
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.633
Slack : 1.426
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.652
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.450
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.469
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.479
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.440
Data Delay : 2.076
Slack : 1.490
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.716
Slack : 1.500
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.720
Slack : 1.509
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.300
Data Delay : 1.366
Slack : 1.517
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.740
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 4.344
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 4.342
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.341
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 4.340
Slack : -6.222
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.340
Slack : -5.985
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 4.076
Slack : -5.971
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.195
Data Delay : 4.060
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.923
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.923
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.923
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.923
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.166
Data Delay : 3.919
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 3.920
Slack : -5.375
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.170
Data Delay : 3.924
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.190
Data Delay : 3.922
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.354
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.185
Data Delay : 3.918
Slack : -5.353
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.188
Data Delay : 3.920
Slack : -5.351
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.192
Data Delay : 3.922
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
Slack : -5.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.198
Data Delay : 3.924
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.698
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.609
Data Delay : 3.556
Slack : 3.705
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.611
Data Delay : 3.557
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.554
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.553
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.553
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.553
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.553
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.553
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.554
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.554
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.554
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.554
Slack : 3.710
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.554
Slack : 3.728
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.588
Data Delay : 3.557
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.553
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.553
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.557
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.557
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.557
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.557
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.553
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.553
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.553
Slack : 4.074
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.239
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 3.554
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.294
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.190
Data Delay : 3.669
Slack : 4.309
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.192
Data Delay : 3.686
Slack : 4.519
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.922
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.225
Data Delay : 3.926
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 3.924
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.923
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 3.922
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.604
Actual Width : 20.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.615
Actual Width : 20.831
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.684
Actual Width : 20.868
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.692
Actual Width : 20.876
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.693
Actual Width : 20.848
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.694
Actual Width : 20.878
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.981
Fall : 2.458
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.874
Fall : 4.319
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.262
Fall : 1.505
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.823
Fall : 3.104
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.568
Fall : -2.042
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.986
Fall : -3.436
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.397
Fall : -0.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.397
Fall : -0.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.645
Fall : -0.878
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.355
Fall : -1.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.359
Fall : 10.359
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.359
Fall : 10.359
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.229
Fall : 9.317
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 10.015
Fall : 9.971
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.628
Fall : 9.644
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.826
Fall : 9.843
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.397
Fall : 9.318
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.972
Fall : 9.975
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.201
Fall : 9.152
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.986
Fall : 7.983
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.696
Fall : 7.696
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.783
Fall : 7.821
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.371
Fall : 7.388
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.739
Fall : 7.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.986
Fall : 7.975
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.534
Fall : 7.528
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.914
Fall : 7.983
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.285
Fall : 7.303
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.197
Fall : 7.907
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.197
Fall : 7.907
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.071
Fall : 5.974
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.410
Fall : 6.400
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.836
Fall : 6.810
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.558
Fall : 6.425
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.558
Fall : 6.425
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.366
Fall : 6.305
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.429
Fall : 6.279
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.429
Fall : 6.279
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.621
Fall : 6.664
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.621
Fall : 6.664
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.426
Fall : 6.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.231
Fall : 6.211
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.443
Fall : 6.428
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.669
Fall : 7.651
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.267
Fall : 8.296
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.307
Fall : 8.286
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.669
Fall : 7.651
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.069
Fall : 8.077
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.420
Fall : 8.430
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.905
Fall : 7.819
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.716
Fall : 7.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.805
Fall : 7.751
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.460
Fall : 5.452
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.523
Fall : 6.572
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.581
Fall : 6.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.318
Fall : 6.325
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.316
Fall : 6.388
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.460
Fall : 5.452
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.325
Fall : 6.358
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.708
Fall : 6.750
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.065
Fall : 6.060
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.938
Fall : 3.816
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.979
Fall : 5.590
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.938
Fall : 3.816
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.183
Fall : 4.073
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.592
Fall : 4.467
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 4.007
Fall : 3.940
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 4.406
Fall : 4.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 4.007
Fall : 3.940
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.282
Fall : 4.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.282
Fall : 4.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.461
Fall : 2.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.864
Fall : 3.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.238
Fall : 4.188
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.151
Fall : 4.091
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.864
Fall : 3.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 4.068
Fall : 3.961
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.457
Fall : 2.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.456
Fall : 2.369
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.479
Fall : 4.115
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.458
Fall : 2.371
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.551
Fall : 2.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.629
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.626
RF :
FR :
FF : 7.003
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.318
RF :
FR :
FF : 4.517
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.491
RF :
FR :
FF : 4.559
Input Port : SW[2]
Output Port : LED[2]
RR : 3.930
RF :
FR :
FF : 4.081
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.402
RF :
FR :
FF : 6.769
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.186
RF :
FR :
FF : 4.384
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 51.79 MHz
Restricted Fmax : 51.79 MHz
Clock Name : CLOCK_50
Note :
Fmax : 138.35 MHz
Restricted Fmax : 138.35 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 177.12 MHz
Restricted Fmax : 177.12 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 1052.63 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -17.311
End Point TNS : -526.609
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.686
End Point TNS : -253.661
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.428
End Point TNS : -40.009
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.785
End Point TNS : -2.785
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.300
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.304
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.311
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -5.744
End Point TNS : -423.582
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.374
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.489
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.591
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.491
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -17.311
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 7.112
Slack : -17.306
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 7.107
Slack : -17.281
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.081
Slack : -17.275
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.075
Slack : -17.265
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 7.066
Slack : -17.249
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 7.050
Slack : -17.244
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 7.044
Slack : -17.196
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.755
Slack : -17.190
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.991
Slack : -17.182
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.984
Slack : -17.176
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.740
Slack : -17.176
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.973
Slack : -17.172
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.969
Slack : -17.142
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.944
Slack : -17.140
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.941
Slack : -17.136
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.937
Slack : -17.114
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.915
Slack : -17.106
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 6.906
Slack : -17.082
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.883
Slack : -17.075
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.631
Slack : -17.061
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.863
Slack : -17.022
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 6.823
Slack : -16.969
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.519
Slack : -16.953
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.750
Slack : -16.941
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.738
Slack : -16.939
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.489
Slack : -16.921
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.723
Slack : -16.917
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 6.717
Slack : -16.916
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.475
Slack : -16.906
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 6.706
Slack : -16.904
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.462
Slack : -16.894
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 6.464
Slack : -16.865
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.423
Slack : -16.857
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.654
Slack : -16.852
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.647
Slack : -16.821
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.618
Slack : -16.820
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.376
Slack : -16.761
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.314
Slack : -16.737
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.539
Slack : -16.733
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.535
Slack : -16.727
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.524
Slack : -16.721
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.272
Slack : -16.719
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.280
Slack : -16.716
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.274
Slack : -16.702
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.499
Slack : -16.700
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.502
Slack : -16.698
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.500
Slack : -16.679
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.476
Slack : -16.665
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.215
Slack : -16.650
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.216
Slack : -16.637
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.188
Slack : -16.629
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.431
Slack : -16.615
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.165
Slack : -16.606
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.167
Slack : -16.595
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.397
Slack : -16.582
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.142
Slack : -16.567
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.364
Slack : -16.565
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.123
Slack : -16.554
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.104
Slack : -16.544
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.341
Slack : -16.541
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.093
Slack : -16.539
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.341
Slack : -16.529
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.095
Slack : -16.512
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.314
Slack : -16.511
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.313
Slack : -16.483
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.041
Slack : -16.443
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.517
Data Delay : 6.000
Slack : -16.425
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 6.227
Slack : -16.422
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 5.984
Slack : -16.415
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.212
Slack : -16.393
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 5.945
Slack : -16.347
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 5.911
Slack : -16.212
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 5.772
Slack : -16.157
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.958
Slack : -16.155
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 5.708
Slack : -16.152
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.953
Slack : -16.143
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 5.940
Slack : -16.127
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.927
Slack : -16.121
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.921
Slack : -16.113
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.272
Data Delay : 5.915
Slack : -16.111
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.912
Slack : -16.095
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.896
Slack : -16.090
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.890
Slack : -16.052
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 5.610
Slack : -16.036
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.837
Slack : -16.022
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 5.819
Slack : -16.018
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 5.815
Slack : -15.986
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.787
Slack : -15.982
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.783
Slack : -15.961
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.762
Slack : -15.960
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.761
Slack : -15.956
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.757
Slack : -15.952
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.752
Slack : -15.931
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.731
Slack : -15.928
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.729
Slack : -15.925
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.725
Slack : -15.918
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_G[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.274
Data Delay : 5.718
Slack : -15.915
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.716
Slack : -15.899
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.700
Slack : -15.868
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.273
Data Delay : 5.669
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.686
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.774
Slack : -6.590
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.686
Slack : -6.554
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.644
Slack : -6.499
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.983
Data Delay : 4.616
Slack : -6.497
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.593
Slack : -6.479
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.027
Data Delay : 4.552
Slack : -6.476
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.573
Slack : -6.457
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.538
Slack : -6.451
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.586
Slack : -6.417
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 4.546
Slack : -6.411
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.508
Slack : -6.338
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 4.475
Slack : -6.321
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 4.458
Slack : -6.320
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.417
Slack : -6.306
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 4.385
Slack : -6.299
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.435
Slack : -6.296
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 4.411
Slack : -6.294
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.006
Data Delay : 4.388
Slack : -6.293
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.377
Slack : -6.292
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.978
Data Delay : 4.414
Slack : -6.291
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.410
Slack : -6.289
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.387
Slack : -6.278
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.359
Slack : -6.270
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.400
Slack : -6.264
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.351
Slack : -6.253
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.348
Slack : -6.237
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.321
Slack : -6.215
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.307
Slack : -6.207
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 4.345
Slack : -6.203
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.327
Slack : -6.198
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.759
Data Delay : 4.539
Slack : -6.179
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.275
Slack : -6.173
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.987
Data Delay : 4.286
Slack : -6.161
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.996
Data Delay : 4.265
Slack : -6.145
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.997
Data Delay : 4.248
Slack : -6.145
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.242
Slack : -6.142
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 4.280
Slack : -6.128
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.247
Slack : -6.124
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 4.261
Slack : -6.106
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 4.239
Slack : -6.102
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.751
Data Delay : 4.451
Slack : -6.091
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.182
Slack : -6.091
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 4.202
Slack : -6.091
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.221
Slack : -6.072
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.158
Slack : -6.065
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.177
Slack : -6.064
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.189
Slack : -6.063
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.203
Slack : -6.062
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.996
Data Delay : 4.166
Slack : -6.055
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 4.166
Slack : -6.051
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.176
Slack : -6.051
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.146
Slack : -6.040
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 4.178
Slack : -6.039
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.134
Slack : -6.036
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.128
Slack : -6.026
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 4.153
Slack : -6.022
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.954
Data Delay : 4.168
Slack : -6.019
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 4.142
Slack : -6.009
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.750
Data Delay : 4.359
Slack : -6.006
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.955
Data Delay : 4.151
Slack : -6.004
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.090
Slack : -6.004
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.102
Slack : -6.004
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.761
Data Delay : 4.343
Slack : -6.001
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 4.132
Slack : -6.000
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.092
Slack : -5.988
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.124
Slack : -5.988
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.750
Data Delay : 4.338
Slack : -5.985
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.115
Slack : -5.983
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.070
Slack : -5.978
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.076
Slack : -5.973
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 4.052
Slack : -5.972
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.058
Slack : -5.970
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 4.081
Slack : -5.965
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 4.080
Slack : -5.963
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.047
Slack : -5.955
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.042
Slack : -5.952
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.092
Slack : -5.950
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.980
Data Delay : 4.070
Slack : -5.939
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.025
Slack : -5.937
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.022
Slack : -5.933
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.759
Data Delay : 4.274
Slack : -5.931
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.028
Slack : -5.930
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.065
Slack : -5.927
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.011
Slack : -5.923
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.750
Data Delay : 4.273
Slack : -5.908
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 4.014
Slack : -5.896
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.012
Slack : -5.887
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 3.985
Slack : -5.884
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 3.984
Slack : -5.884
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 3.972
Slack : -5.877
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 4.011
Slack : -5.874
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 3.998
Slack : -5.870
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 3.970
Slack : -5.857
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 3.955
Slack : -5.836
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 3.973
Slack : -5.826
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.180
Data Delay : 4.106
Slack : -5.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 3.952
Slack : -5.814
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 3.940
Slack : -5.804
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.188
Data Delay : 4.092
Slack : -5.794
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 3.901
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.428
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 2.602
Slack : -4.267
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.559
Slack : -4.267
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.559
Slack : -4.074
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.366
Slack : -4.074
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.366
Slack : -4.074
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.366
Slack : -4.074
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.366
Slack : -4.074
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.366
Slack : -3.711
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.003
Slack : -2.966
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.208
Data Delay : 1.553
Slack : 17.237
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.241
Slack : 17.242
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.236
Slack : 17.361
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.117
Slack : 17.361
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.117
Slack : 17.362
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.116
Slack : 17.366
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.112
Slack : 17.366
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.112
Slack : 17.421
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.057
Slack : 17.421
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.057
Slack : 17.421
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.057
Slack : 17.421
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.057
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.052
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.052
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.052
Slack : 17.426
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.052
Slack : 17.453
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 3.025
Slack : 17.488
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.990
Slack : 17.488
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.990
Slack : 17.495
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.983
Slack : 17.495
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.983
Slack : 17.500
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.978
Slack : 17.500
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.978
Slack : 17.528
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.949
Slack : 17.528
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.949
Slack : 17.533
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.944
Slack : 17.533
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.944
Slack : 17.548
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.930
Slack : 17.548
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.930
Slack : 17.548
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.930
Slack : 17.548
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.930
Slack : 17.577
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.901
Slack : 17.577
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.901
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.874
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.874
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.874
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.874
Slack : 17.604
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.874
Slack : 17.609
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.869
Slack : 17.609
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.869
Slack : 17.609
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.869
Slack : 17.609
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.869
Slack : 17.609
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.869
Slack : 17.618
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.860
Slack : 17.622
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.856
Slack : 17.622
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.856
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.841
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.841
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.841
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.841
Slack : 17.655
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.822
Slack : 17.655
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.822
Slack : 17.711
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.767
Slack : 17.711
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.767
Slack : 17.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.747
Slack : 17.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.747
Slack : 17.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.747
Slack : 17.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.747
Slack : 17.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.747
Slack : 17.742
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.736
Slack : 17.742
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.736
Slack : 17.744
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.733
Slack : 17.744
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.733
Slack : 17.770
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.707
Slack : 17.775
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.702
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.676
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.676
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.676
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.676
Slack : 17.820
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.658
Slack : 17.820
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.658
Slack : 17.820
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.658
Slack : 17.820
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.658
Slack : 17.820
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.658
Slack : 17.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.647
Slack : 17.876
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.602
Slack : 17.876
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.602
Slack : 17.890
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.049
Data Delay : 2.907
Slack : 17.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.049
Data Delay : 2.902
Slack : 17.897
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.580
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.568
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.568
Slack : 17.955
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.523
Slack : 17.955
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.523
Slack : 17.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.493
Slack : 17.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.493
Slack : 17.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.493
Slack : 17.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.493
Slack : 17.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.368
Data Delay : 2.493
Slack : 17.986
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.491
Slack : 18.007
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.396
Data Delay : 2.353
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.785
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.254
Data Delay : 1.417
Slack : 70.539
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.876
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.518
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 1.248
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.626
Data Delay : 1.091
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.300
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.519
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.519
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.322
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.535
Slack : 0.339
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.342
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.541
Slack : 0.342
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.541
Slack : 0.344
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.543
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.561
Slack : 0.363
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.563
Slack : 0.418
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.631
Slack : 0.418
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.631
Slack : 0.419
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.632
Slack : 0.419
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.632
Slack : 0.421
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.634
Slack : 0.469
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.668
Slack : 0.474
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.673
Slack : 0.487
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.700
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.703
Slack : 0.491
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.096
Data Delay : 0.731
Slack : 0.492
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.705
Slack : 0.498
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.697
Slack : 0.499
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.698
Slack : 0.501
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.700
Slack : 0.501
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.714
Slack : 0.502
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.503
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.716
Slack : 0.507
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.706
Slack : 0.508
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.707
Slack : 0.514
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.727
Slack : 0.515
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.728
Slack : 0.516
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.715
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.717
Slack : 0.519
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.732
Slack : 0.520
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.719
Slack : 0.529
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.728
Slack : 0.532
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.387
Data Delay : 1.063
Slack : 0.537
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.736
Slack : 0.538
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.737
Slack : 0.539
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.738
Slack : 0.547
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.746
Slack : 0.548
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.747
Slack : 0.561
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.761
Slack : 0.563
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.763
Slack : 0.565
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.764
Slack : 0.599
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.799
Slack : 0.605
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.805
Slack : 0.630
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.829
Slack : 0.668
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 0.547
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.901
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.901
Slack : 0.706
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.905
Slack : 0.709
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.908
Slack : 0.709
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.907
Slack : 0.710
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.908
Slack : 0.714
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.914
Slack : 0.721
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.921
Slack : 0.728
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.927
Slack : 0.729
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.928
Slack : 0.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.944
Slack : 0.735
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.948
Slack : 0.738
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.951
Slack : 0.740
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.953
Slack : 0.741
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.954
Slack : 0.744
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.745
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.944
Slack : 0.745
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.958
Slack : 0.746
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.945
Slack : 0.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.960
Slack : 0.748
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.961
Slack : 0.749
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.632
Slack : 0.750
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.962
Slack : 0.753
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.760
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.959
Slack : 0.764
From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.964
Slack : 0.770
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.969
Slack : 0.772
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.972
Slack : 0.773
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.972
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.304
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.304
Data Delay : 2.881
Slack : 0.359
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.305
Data Delay : 2.937
Slack : 1.206
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.731
Slack : 1.215
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.739
Slack : 1.221
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.255
Data Delay : 3.749
Slack : 1.229
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.744
Slack : 1.234
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.759
Slack : 1.240
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.758
Slack : 1.262
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.773
Slack : 1.264
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.255
Data Delay : 3.792
Slack : 1.266
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.784
Slack : 1.278
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.793
Slack : 1.287
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.802
Slack : 1.332
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.853
Slack : 1.340
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.858
Slack : 1.351
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.864
Slack : 1.367
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.881
Slack : 1.373
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.897
Slack : 1.373
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.883
Slack : 1.378
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.898
Slack : 1.378
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.881
Slack : 1.379
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.894
Slack : 1.379
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.892
Slack : 1.383
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.886
Slack : 1.384
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.891
Slack : 1.389
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.904
Slack : 1.393
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.896
Slack : 1.394
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.909
Slack : 1.396
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.911
Slack : 1.400
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.911
Slack : 1.401
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.904
Slack : 1.402
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.908
Slack : 1.405
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.925
Slack : 1.407
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.921
Slack : 1.410
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.923
Slack : 1.410
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.924
Slack : 1.412
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.927
Slack : 1.413
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.919
Slack : 1.417
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.930
Slack : 1.417
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.920
Slack : 1.425
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.949
Slack : 1.433
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.954
Slack : 1.434
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.941
Slack : 1.435
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.938
Slack : 1.435
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.953
Slack : 1.436
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.947
Slack : 1.440
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.950
Slack : 1.442
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.958
Slack : 1.449
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.960
Slack : 1.451
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.958
Slack : 1.452
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.310
Data Delay : 4.035
Slack : 1.452
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.962
Slack : 1.453
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.964
Slack : 1.454
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.960
Slack : 1.455
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.326
Data Delay : 4.054
Slack : 1.455
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.090
Data Delay : 3.818
Slack : 1.455
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.976
Slack : 1.458
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.979
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.975
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.976
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.974
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.968
Slack : 1.461
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.967
Slack : 1.465
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.253
Data Delay : 3.991
Slack : 1.465
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.972
Slack : 1.466
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 3.970
Slack : 1.467
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 3.971
Slack : 1.471
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.996
Slack : 1.473
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.976
Slack : 1.476
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.987
Slack : 1.480
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 4.004
Slack : 1.481
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.301
Data Delay : 4.055
Slack : 1.482
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.997
Slack : 1.485
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.988
Slack : 1.485
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 4.003
Slack : 1.487
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.994
Slack : 1.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.309
Data Delay : 4.069
Slack : 1.489
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 4.004
Slack : 1.490
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 4.002
Slack : 1.492
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.995
Slack : 1.493
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 4.008
Slack : 1.494
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 4.004
Slack : 1.494
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 4.008
Slack : 1.496
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 4.003
Slack : 1.498
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 4.009
Slack : 1.498
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 4.009
Slack : 1.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.322
Data Delay : 4.094
Slack : 1.502
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 4.005
Slack : 1.503
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 4.014
Slack : 1.504
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 4.008
Slack : 1.505
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 4.026
Slack : 1.507
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 4.032
Slack : 1.508
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 4.027
Slack : 1.509
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 4.024
Slack : 1.510
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 4.035
Slack : 1.510
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.081
Data Delay : 3.864
Slack : 1.511
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 4.017
Slack : 1.513
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 4.023
Slack : 1.513
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 4.020
Slack : 1.520
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 4.027
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.493
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.692
Slack : 0.498
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.697
Slack : 0.509
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.708
Slack : 0.512
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.711
Slack : 0.596
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.795
Slack : 0.652
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.852
Slack : 0.737
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.936
Slack : 0.747
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.946
Slack : 0.748
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.751
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.957
Slack : 0.755
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.954
Slack : 0.778
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.978
Slack : 0.826
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.025
Slack : 0.839
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.038
Slack : 0.844
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.043
Slack : 0.885
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.091
Slack : 0.901
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.107
Slack : 0.911
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.114
Slack : 0.986
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.191
Slack : 0.987
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.192
Slack : 0.996
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.201
Slack : 0.996
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.201
Slack : 1.019
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 0.892
Slack : 1.022
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.228
Slack : 1.025
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.231
Slack : 1.039
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.245
Slack : 1.040
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 0.913
Slack : 1.041
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 0.914
Slack : 1.050
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 0.923
Slack : 1.062
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.268
Slack : 1.070
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.269
Slack : 1.082
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.281
Slack : 1.106
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.312
Slack : 1.130
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.336
Slack : 1.143
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.349
Slack : 1.145
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.345
Slack : 1.145
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.345
Slack : 1.145
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.345
Slack : 1.145
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.345
Slack : 1.151
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.357
Slack : 1.153
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.353
Slack : 1.154
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.360
Slack : 1.166
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.365
Slack : 1.168
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.374
Slack : 1.170
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.371
Slack : 1.172
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 1.045
Slack : 1.174
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.374
Slack : 1.176
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.376
Slack : 1.176
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.376
Slack : 1.182
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.298
Data Delay : 1.028
Slack : 1.183
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.389
Slack : 1.184
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.271
Data Delay : 1.057
Slack : 1.200
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.406
Slack : 1.207
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.298
Data Delay : 1.053
Slack : 1.219
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.425
Slack : 1.223
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.298
Data Delay : 1.069
Slack : 1.225
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.298
Data Delay : 1.071
Slack : 1.240
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.298
Data Delay : 1.086
Slack : 1.242
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.442
Slack : 1.243
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.449
Slack : 1.250
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.456
Slack : 1.250
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.456
Slack : 1.257
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.457
Slack : 1.261
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.467
Slack : 1.264
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.467
Slack : 1.268
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.474
Slack : 1.277
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.480
Slack : 1.279
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.485
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.320
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.422
Data Delay : 1.886
Slack : 1.339
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.545
Slack : 1.345
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.548
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.349
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|bits_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.394
Data Delay : 1.887
Slack : 1.357
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.563
Slack : 1.362
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.562
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.943
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.941
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.940
Slack : -5.743
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.939
Slack : -5.743
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.092
Data Delay : 3.938
Slack : -5.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 3.681
Slack : -5.494
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.116
Data Delay : 3.667
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.548
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.548
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.549
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.544
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.544
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.545
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.544
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.544
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.544
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.089
Data Delay : 3.546
Slack : -4.963
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.208
Data Delay : 3.550
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.212
Data Delay : 3.547
Slack : -4.941
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.543
Slack : -4.941
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.543
Slack : -4.941
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.543
Slack : -4.941
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.543
Slack : -4.941
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.543
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.542
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.542
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.542
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.542
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.542
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.227
Data Delay : 3.546
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.547
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
Slack : -4.936
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.550
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.205
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.374
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.209
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.599
Data Delay : 3.205
Slack : 3.380
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.595
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.583
Data Delay : 3.205
Slack : 3.403
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.578
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.268
Data Delay : 3.204
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.269
Data Delay : 3.205
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.267
Data Delay : 3.204
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.267
Data Delay : 3.204
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.267
Data Delay : 3.204
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.267
Data Delay : 3.204
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.267
Data Delay : 3.204
Slack : 3.895
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.226
Data Delay : 3.294
Slack : 3.909
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.227
Data Delay : 3.309
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.254
Data Delay : 3.541
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.252
Data Delay : 3.539
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.251
Data Delay : 3.538
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.537
Slack : 4.118
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.538
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.496
Actual Width : 9.726
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[4]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[0]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[2]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[4]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[5]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[6]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[7]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[8]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[9]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[0]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[1]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[2]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[3]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[4]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[5]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[6]
Slack : 19.600
Actual Width : 19.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[9]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[10]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[11]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[12]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[9]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[1]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[2]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[3]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[4]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[5]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[6]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[7]
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.592
Actual Width : 20.808
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.603
Actual Width : 20.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.695
Actual Width : 20.845
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.696
Actual Width : 20.846
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.697
Actual Width : 20.852
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.697
Actual Width : 20.881
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.700
Actual Width : 20.855
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.702
Actual Width : 20.857
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.911
Fall : 2.250
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.553
Fall : 3.886
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.869
Fall : 1.148
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.869
Fall : 1.148
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.127
Fall : 1.330
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.508
Fall : 2.792
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.524
Fall : -1.860
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.737
Fall : -3.061
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.321
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.321
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.576
Fall : -0.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.192
Fall : -1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.288
Fall : 9.190
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.288
Fall : 9.190
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.334
Fall : 8.266
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.015
Fall : 8.878
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.651
Fall : 8.566
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.878
Fall : 8.812
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.466
Fall : 8.329
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.024
Fall : 8.945
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.255
Fall : 8.139
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.270
Fall : 7.175
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.990
Fall : 6.892
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.043
Fall : 6.987
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.669
Fall : 6.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.995
Fall : 6.959
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.270
Fall : 7.174
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.811
Fall : 6.729
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.250
Fall : 7.175
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.586
Fall : 6.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 7.385
Fall : 6.991
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 7.385
Fall : 6.991
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 5.536
Fall : 5.411
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 5.836
Fall : 5.758
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.231
Fall : 6.124
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.815
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 5.802
Fall : 5.684
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 5.868
Fall : 5.672
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 5.868
Fall : 5.672
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.597
Fall : 2.522
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.035
Fall : 5.996
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.035
Fall : 5.996
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 5.858
Fall : 5.798
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 5.672
Fall : 5.600
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 5.870
Fall : 5.793
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.595
Fall : 2.520
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.361
Fall : 3.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.594
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.647
Fall : 2.553
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.648
Fall : 2.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.905
Fall : 6.797
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.457
Fall : 7.377
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.475
Fall : 7.384
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.905
Fall : 6.797
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.286
Fall : 7.208
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.618
Fall : 7.567
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.138
Fall : 6.996
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.984
Fall : 6.911
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.037
Fall : 6.924
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.004
Fall : 4.912
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.924
Fall : 5.881
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.978
Fall : 5.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.763
Fall : 5.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.765
Fall : 5.720
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.004
Fall : 4.912
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.746
Fall : 5.674
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.140
Fall : 6.075
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.512
Fall : 5.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.609
Fall : 3.472
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.390
Fall : 4.913
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.609
Fall : 3.472
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.832
Fall : 3.672
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.210
Fall : 4.023
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.660
Fall : 3.561
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 4.048
Fall : 3.884
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.660
Fall : 3.561
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.929
Fall : 3.746
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.929
Fall : 3.746
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.241
Fall : 2.165
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.534
Fall : 3.394
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.882
Fall : 3.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.799
Fall : 3.710
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.534
Fall : 3.394
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.723
Fall : 3.578
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.237
Fall : 2.161
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.236
Fall : 2.160
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.005
Fall : 3.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.238
Fall : 2.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.290
Fall : 2.196
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.291
Fall : 2.197
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.171
RF :
FR :
FF : 4.298
Input Port : SW[2]
Output Port : LED[2]
RR : 3.640
RF :
FR :
FF : 3.830
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.058
RF :
FR :
FF : 6.293
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.926
RF :
FR :
FF : 4.082
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.037
RF :
FR :
FF : 4.164
Input Port : SW[2]
Output Port : LED[2]
RR : 3.527
RF :
FR :
FF : 3.715
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 5.841
RF :
FR :
FF : 6.076
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.796
RF :
FR :
FF : 3.952
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -14.971
End Point TNS : -442.545
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -4.979
End Point TNS : -171.124
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -3.775
End Point TNS : -35.541
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.784
End Point TNS : -2.784
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -0.053
End Point TNS : -0.089
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.177
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.178
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.693
End Point TNS : -358.284
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 2.518
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.208
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.609
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.535
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -14.971
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 5.024
Slack : -14.965
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 5.018
Slack : -14.951
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 5.004
Slack : -14.940
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.993
Slack : -14.933
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.985
Slack : -14.932
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.984
Slack : -14.927
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.979
Slack : -14.893
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.946
Slack : -14.893
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.942
Slack : -14.880
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.929
Slack : -14.864
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.917
Slack : -14.860
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.913
Slack : -14.853
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.906
Slack : -14.842
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.894
Slack : -14.824
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.877
Slack : -14.800
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 4.853
Slack : -14.761
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.811
Slack : -14.737
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.786
Slack : -14.728
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.780
Slack : -14.718
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 4.770
Slack : -14.694
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.743
Slack : -14.690
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.586
Slack : -14.685
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.734
Slack : -14.667
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.716
Slack : -14.623
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.523
Slack : -14.609
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.658
Slack : -14.606
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.661
Slack : -14.593
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.642
Slack : -14.587
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.636
Slack : -14.564
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.619
Slack : -14.561
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.615
Slack : -14.543
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.438
Slack : -14.517
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.406
Slack : -14.515
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.564
Slack : -14.515
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.405
Slack : -14.501
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.396
Slack : -14.497
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.402
Slack : -14.494
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.543
Slack : -14.474
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.529
Slack : -14.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.358
Slack : -14.459
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.354
Slack : -14.425
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.320
Slack : -14.420
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.469
Slack : -14.413
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.311
Slack : -14.388
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.281
Slack : -14.372
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.268
Slack : -14.341
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.232
Slack : -14.340
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.231
Slack : -14.337
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.392
Slack : -14.335
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.389
Slack : -14.333
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.387
Slack : -14.325
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.215
Slack : -14.310
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.365
Slack : -14.285
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.340
Slack : -14.285
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.175
Slack : -14.284
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.182
Slack : -14.281
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.184
Slack : -14.271
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.326
Slack : -14.259
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.154
Slack : -14.250
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.139
Slack : -14.247
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.301
Slack : -14.221
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.271
Slack : -14.206
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.103
Slack : -14.203
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.106
Slack : -14.195
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.086
Slack : -14.189
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.019
Data Delay : 4.244
Slack : -14.183
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.237
Slack : -14.169
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.065
Slack : -14.155
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.052
Slack : -14.138
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.038
Slack : -14.126
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.017
Slack : -14.124
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.024
Slack : -14.114
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.168
Slack : -14.045
From Node : ula:ula_|video:video_|attr[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.094
Slack : -14.020
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 3.917
Slack : -13.997
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 3.890
Slack : -13.949
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.020
Data Delay : 4.003
Slack : -13.888
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.941
Slack : -13.887
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.940
Slack : -13.882
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.934
Slack : -13.881
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 3.778
Slack : -13.868
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.920
Slack : -13.841
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.894
Slack : -13.826
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.879
Slack : -13.816
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.869
Slack : -13.812
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.865
Slack : -13.811
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.864
Slack : -13.806
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.858
Slack : -13.792
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.844
Slack : -13.784
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.836
Slack : -13.765
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.818
Slack : -13.750
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.803
Slack : -13.747
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.800
Slack : -13.744
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 3.793
Slack : -13.742
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.795
Slack : -13.742
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.795
Slack : -13.740
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.793
Slack : -13.738
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.021
Data Delay : 3.791
Slack : -13.731
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.022
Data Delay : 3.783
Slack : -13.731
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 3.780
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -4.979
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.058
Data Delay : 3.010
Slack : -4.977
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.052
Data Delay : 3.014
Slack : -4.861
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.051
Data Delay : 2.899
Slack : -4.849
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.052
Data Delay : 2.886
Slack : -4.418
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 3.131
Slack : -4.378
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 3.093
Slack : -4.335
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.371
Data Delay : 3.053
Slack : -4.297
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 3.046
Slack : -4.275
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 3.009
Slack : -4.272
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.991
Slack : -4.269
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.390
Data Delay : 2.968
Slack : -4.267
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.972
Slack : -4.253
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.973
Slack : -4.232
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.346
Data Delay : 2.975
Slack : -4.230
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.950
Slack : -4.220
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.939
Slack : -4.204
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 2.954
Slack : -4.200
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.911
Slack : -4.196
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.902
Slack : -4.194
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.942
Slack : -4.159
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.897
Slack : -4.157
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.901
Slack : -4.153
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.884
Slack : -4.152
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.886
Slack : -4.151
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.857
Slack : -4.149
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.897
Slack : -4.139
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.844
Slack : -4.131
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.848
Slack : -4.130
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.850
Slack : -4.126
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.835
Slack : -4.124
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.839
Slack : -4.115
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.855
Slack : -4.109
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.371
Data Delay : 2.827
Slack : -4.086
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.835
Slack : -4.073
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.792
Slack : -4.071
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.365
Data Delay : 2.795
Slack : -4.071
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.359
Data Delay : 2.801
Slack : -4.061
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.783
Slack : -4.059
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.792
Slack : -4.056
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.210
Data Delay : 2.935
Slack : -4.055
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.775
Slack : -4.048
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.759
Slack : -4.044
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.760
Slack : -4.041
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.786
Slack : -4.035
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.783
Slack : -4.034
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.783
Slack : -4.029
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.773
Slack : -4.022
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.763
Slack : -4.021
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.747
Slack : -4.018
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.732
Slack : -4.010
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.719
Slack : -4.008
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.724
Slack : -4.003
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.744
Slack : -4.002
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.361
Data Delay : 2.730
Slack : -4.001
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.336
Data Delay : 2.754
Slack : -3.999
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.331
Data Delay : 2.757
Slack : -3.999
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.750
Slack : -3.996
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.711
Slack : -3.994
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.733
Slack : -3.993
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.703
Slack : -3.989
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.745
Slack : -3.985
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.695
Slack : -3.985
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.711
Slack : -3.982
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.721
Slack : -3.980
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.382
Data Delay : 2.687
Slack : -3.980
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.724
Slack : -3.975
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.697
Slack : -3.973
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.679
Slack : -3.973
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.205
Data Delay : 2.857
Slack : -3.972
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.364
Data Delay : 2.697
Slack : -3.971
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.682
Slack : -3.970
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.712
Slack : -3.963
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 2.713
Slack : -3.961
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.670
Slack : -3.961
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.670
Slack : -3.960
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.693
Slack : -3.954
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.204
Data Delay : 2.839
Slack : -3.953
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.335
Data Delay : 2.707
Slack : -3.950
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.371
Data Delay : 2.668
Slack : -3.949
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.676
Slack : -3.948
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.359
Data Delay : 2.678
Slack : -3.944
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.382
Data Delay : 2.651
Slack : -3.936
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.682
Slack : -3.932
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.210
Data Delay : 2.811
Slack : -3.926
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.213
Data Delay : 2.802
Slack : -3.920
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.666
Slack : -3.916
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.649
Slack : -3.914
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.635
Slack : -3.914
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.653
Slack : -3.910
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.204
Data Delay : 2.795
Slack : -3.898
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.637
Slack : -3.896
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.617
Slack : -3.896
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.616
Slack : -3.892
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.619
Slack : -3.879
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.620
Slack : -3.878
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.366
Data Delay : 2.601
Slack : -3.875
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.594
Slack : -3.870
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.621
Slack : -3.862
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.601
Slack : -3.860
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.366
Data Delay : 2.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -3.775
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 1.851
Slack : -3.717
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.862
Slack : -3.717
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.862
Slack : -3.603
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.748
Slack : -3.603
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.748
Slack : -3.603
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.748
Slack : -3.603
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.748
Slack : -3.603
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.748
Slack : -3.360
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.505
Slack : -2.957
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.044
Data Delay : 1.284
Slack : 18.580
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.984
Slack : 18.583
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.981
Slack : 18.654
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.910
Slack : 18.654
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.910
Slack : 18.657
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.907
Slack : 18.657
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.907
Slack : 18.675
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.889
Slack : 18.700
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.864
Slack : 18.700
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.864
Slack : 18.700
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.864
Slack : 18.700
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.864
Slack : 18.703
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.861
Slack : 18.703
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.861
Slack : 18.703
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.861
Slack : 18.703
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.861
Slack : 18.725
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.839
Slack : 18.739
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.825
Slack : 18.739
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.825
Slack : 18.740
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.824
Slack : 18.740
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.824
Slack : 18.750
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.814
Slack : 18.750
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.814
Slack : 18.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.792
Slack : 18.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.792
Slack : 18.772
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.789
Slack : 18.772
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.789
Slack : 18.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.790
Slack : 18.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.790
Slack : 18.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.790
Slack : 18.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.790
Slack : 18.799
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.765
Slack : 18.799
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.765
Slack : 18.803
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.761
Slack : 18.811
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.753
Slack : 18.811
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.753
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.741
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.741
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.741
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.741
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.741
Slack : 18.824
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.740
Slack : 18.824
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.740
Slack : 18.824
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.740
Slack : 18.824
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.740
Slack : 18.824
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.740
Slack : 18.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.733
Slack : 18.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.733
Slack : 18.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.733
Slack : 18.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.733
Slack : 18.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.696
Slack : 18.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.696
Slack : 18.868
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.696
Slack : 18.868
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.696
Slack : 18.877
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.687
Slack : 18.877
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.687
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.669
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.669
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.669
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.669
Slack : 18.895
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.669
Slack : 18.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.652
Slack : 18.910
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.651
Slack : 18.914
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.647
Slack : 18.914
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.647
Slack : 18.923
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.641
Slack : 18.923
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.641
Slack : 18.923
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.641
Slack : 18.923
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.641
Slack : 18.947
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.617
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.612
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.612
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.612
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.612
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.612
Slack : 18.981
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.580
Slack : 18.989
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.087
Data Delay : 1.762
Slack : 18.991
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.573
Slack : 18.991
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.573
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.569
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.569
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.087
Data Delay : 1.759
Slack : 19.021
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.543
Slack : 19.021
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.543
Slack : 19.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.277
Data Delay : 1.523
Slack : 19.067
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.497
Slack : 19.067
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.497
Slack : 19.067
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.497
Slack : 19.067
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.497
Slack : 19.074
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.490
Slack : 19.074
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.274
Data Delay : 1.490
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.784
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : -0.021
Data Delay : 1.133
Slack : 70.890
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.540
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -0.053
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.556
Data Delay : 1.711
Slack : -0.036
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.557
Data Delay : 1.729
Slack : 0.540
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.270
Slack : 0.548
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.280
Slack : 0.558
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.283
Slack : 0.559
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.281
Slack : 0.561
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.293
Slack : 0.564
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.526
Data Delay : 2.298
Slack : 0.575
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.526
Data Delay : 2.309
Slack : 0.603
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.327
Slack : 0.606
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.331
Slack : 0.606
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.323
Slack : 0.610
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.332
Slack : 0.618
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.575
Data Delay : 2.401
Slack : 0.620
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.555
Data Delay : 2.383
Slack : 0.623
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.558
Data Delay : 2.389
Slack : 0.626
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.351
Slack : 0.637
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.571
Data Delay : 2.416
Slack : 0.637
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.367
Slack : 0.638
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.365
Slack : 0.641
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.570
Data Delay : 2.419
Slack : 0.646
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.367
Slack : 0.650
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.364
Slack : 0.650
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.372
Slack : 0.651
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.375
Slack : 0.651
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.375
Slack : 0.651
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.558
Data Delay : 2.417
Slack : 0.653
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.375
Slack : 0.654
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.373
Slack : 0.655
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.376
Slack : 0.660
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.389
Slack : 0.661
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.390
Slack : 0.662
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.383
Slack : 0.665
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.387
Slack : 0.665
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.387
Slack : 0.666
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.382
Slack : 0.667
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.389
Slack : 0.669
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.426
Data Delay : 2.303
Slack : 0.669
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.383
Slack : 0.669
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.384
Slack : 0.669
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.384
Slack : 0.671
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.388
Slack : 0.675
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.399
Slack : 0.675
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.386
Slack : 0.677
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.402
Slack : 0.677
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.419
Data Delay : 2.304
Slack : 0.681
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.398
Slack : 0.683
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.402
Slack : 0.687
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.402
Slack : 0.688
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.415
Slack : 0.688
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.402
Slack : 0.689
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.416
Slack : 0.689
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.404
Slack : 0.690
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.412
Slack : 0.690
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.401
Slack : 0.691
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.421
Slack : 0.691
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.402
Slack : 0.693
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.427
Data Delay : 2.328
Slack : 0.695
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.563
Data Delay : 2.466
Slack : 0.695
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.425
Slack : 0.695
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.410
Slack : 0.695
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.411
Slack : 0.696
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.418
Slack : 0.696
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.415
Data Delay : 2.319
Slack : 0.698
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.423
Slack : 0.698
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.421
Slack : 0.698
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.414
Slack : 0.699
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.562
Data Delay : 2.469
Slack : 0.699
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.413
Slack : 0.699
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.411
Slack : 0.700
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.416
Slack : 0.701
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.565
Data Delay : 2.474
Slack : 0.702
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.419
Slack : 0.703
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.417
Slack : 0.703
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.512
Data Delay : 2.423
Slack : 0.704
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.318
Slack : 0.705
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.525
Data Delay : 2.438
Slack : 0.706
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.438
Slack : 0.706
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.423
Slack : 0.706
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.423
Slack : 0.707
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.424
Slack : 0.709
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.423
Slack : 0.709
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.430
Slack : 0.710
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.421
Slack : 0.711
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.436
Slack : 0.712
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.431
Slack : 0.712
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.512
Data Delay : 2.432
Slack : 0.712
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.423
Data Delay : 2.343
Slack : 0.713
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.432
Slack : 0.713
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.575
Data Delay : 2.496
Slack : 0.714
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.430
Slack : 0.714
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.430
Slack : 0.715
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.438
Slack : 0.716
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.446
Slack : 0.719
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.441
Slack : 0.720
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.442
Slack : 0.724
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.456
Slack : 0.724
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.424
Data Delay : 2.356
Slack : 0.725
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.421
Data Delay : 2.354
Slack : 0.726
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.421
Data Delay : 2.355
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.177
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.436
Slack : 1.186
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.233
Data Delay : 0.576
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.178
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.314
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.188
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.318
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.195
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.315
Slack : 0.200
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.320
Slack : 0.201
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.321
Slack : 0.204
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.324
Slack : 0.208
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.328
Slack : 0.210
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.330
Slack : 0.243
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.372
Slack : 0.244
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.373
Slack : 0.244
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.373
Slack : 0.244
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.373
Slack : 0.245
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.374
Slack : 0.262
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.382
Slack : 0.266
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.384
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.418
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.419
Slack : 0.291
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.421
Slack : 0.292
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 0.436
Slack : 0.292
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.412
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.416
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.426
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.426
Slack : 0.297
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.417
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.034
Data Delay : 0.416
Slack : 0.298
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.302
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.423
Slack : 0.303
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.424
Slack : 0.305
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.623
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.436
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.436
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.436
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.436
Slack : 0.308
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.437
Slack : 0.308
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.437
Slack : 0.308
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.437
Slack : 0.308
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.429
Slack : 0.309
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.438
Slack : 0.309
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.430
Slack : 0.317
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.437
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.440
Slack : 0.325
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.445
Slack : 0.328
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.448
Slack : 0.332
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.452
Slack : 0.341
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.461
Slack : 0.341
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.461
Slack : 0.346
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.466
Slack : 0.370
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.490
Slack : 0.371
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.491
Slack : 0.373
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.493
Slack : 0.397
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.327
Slack : 0.398
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.521
Slack : 0.402
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.525
Slack : 0.404
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.527
Slack : 0.409
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.529
Slack : 0.410
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.530
Slack : 0.411
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.531
Slack : 0.424
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.545
Slack : 0.427
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.548
Slack : 0.430
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.551
Slack : 0.432
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.552
Slack : 0.437
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.567
Slack : 0.438
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.568
Slack : 0.443
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.155
Data Delay : 0.372
Slack : 0.446
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.447
From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.567
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.571
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.578
Slack : 0.449
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.577
Slack : 0.449
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.579
Slack : 0.449
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.579
Slack : 0.451
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.581
Slack : 0.452
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.572
Slack : 0.452
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.582
Slack : 0.452
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.582
Slack : 0.457
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.457
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.293
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.414
Slack : 0.294
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.300
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.303
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.424
Slack : 0.336
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.457
Slack : 0.400
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.521
Slack : 0.442
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.568
Slack : 0.442
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.563
Slack : 0.452
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.573
Slack : 0.453
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.574
Slack : 0.456
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.457
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.481
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.601
Slack : 0.505
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.626
Slack : 0.519
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.640
Slack : 0.524
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.650
Slack : 0.534
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.660
Slack : 0.544
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.667
Slack : 0.581
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.705
Slack : 0.582
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.706
Slack : 0.582
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.706
Slack : 0.582
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.706
Slack : 0.592
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.717
Slack : 0.595
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.720
Slack : 0.597
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.722
Slack : 0.598
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.522
Slack : 0.610
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.534
Slack : 0.611
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.736
Slack : 0.613
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.537
Slack : 0.619
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.543
Slack : 0.633
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.753
Slack : 0.636
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.756
Slack : 0.641
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.766
Slack : 0.652
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.773
Slack : 0.661
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.787
Slack : 0.673
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.799
Slack : 0.674
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.795
Slack : 0.680
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.806
Slack : 0.683
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.809
Slack : 0.686
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.610
Slack : 0.691
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.812
Slack : 0.691
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.812
Slack : 0.691
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.812
Slack : 0.691
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.812
Slack : 0.693
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.819
Slack : 0.694
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.174
Data Delay : 0.604
Slack : 0.695
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.619
Slack : 0.699
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.819
Slack : 0.702
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.174
Data Delay : 0.612
Slack : 0.703
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.824
Slack : 0.707
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.828
Slack : 0.709
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.174
Data Delay : 0.619
Slack : 0.709
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.830
Slack : 0.709
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.835
Slack : 0.710
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.831
Slack : 0.712
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.175
Data Delay : 0.621
Slack : 0.712
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.838
Slack : 0.729
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.175
Data Delay : 0.638
Slack : 0.736
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.859
Slack : 0.736
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.862
Slack : 0.744
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.867
Slack : 0.746
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.872
Slack : 0.755
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.876
Slack : 0.755
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.881
Slack : 0.758
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.884
Slack : 0.771
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.897
Slack : 0.774
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.900
Slack : 0.775
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.901
Slack : 0.794
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.915
Slack : 0.803
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.160
Data Delay : 0.727
Slack : 0.809
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.932
Slack : 0.811
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.174
Data Delay : 0.721
Slack : 0.821
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.947
Slack : 0.824
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.945
Slack : 0.828
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.178
Data Delay : 0.734
Slack : 0.832
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.953
Slack : 0.833
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.958
Slack : 0.833
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.958
Slack : 0.834
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.957
Slack : 0.836
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.957
Slack : 0.837
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.963
Slack : 0.841
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.964
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
Slack : 0.845
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.257
Data Delay : 1.186
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.791
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.789
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.230
Data Delay : 2.786
Slack : -4.692
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.789
Slack : -4.692
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.787
Slack : -4.583
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 2.659
Slack : -4.575
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.251
Data Delay : 2.648
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.572
Slack : -4.251
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.044
Data Delay : 2.578
Slack : -4.240
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.041
Data Delay : 2.570
Slack : -4.240
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.041
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.570
Slack : -4.239
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.571
Slack : -4.238
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.037
Data Delay : 2.572
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.236
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.578
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
Slack : -4.201
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.571
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.256
Data Delay : 1.945
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.559
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.951
Slack : 2.562
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.945
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.943
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.943
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.212
Data Delay : 1.944
Slack : 2.565
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.946
Slack : 2.574
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.209
Data Delay : 1.951
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.944
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.944
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.944
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.944
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.944
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.945
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.897
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.019
Data Delay : 2.020
Slack : 2.902
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.016
Data Delay : 2.028
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.009
Data Delay : 2.157
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.155
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.155
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.004
Data Delay : 2.152
Slack : 3.009
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.005
Data Delay : 2.154
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.641
Actual Width : 20.825
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.649
Actual Width : 20.865
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.659
Actual Width : 20.875
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.079
Fall : 1.946
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 2.221
Fall : 3.039
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.623
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.623
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 0.728
Fall : 1.321
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.575
Fall : 2.139
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.841
Fall : -1.690
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.690
Fall : -2.493
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.368
Fall : -0.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.742
Fall : -1.295
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.008
Fall : 6.095
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.008
Fall : 6.095
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.342
Fall : 5.537
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.828
Fall : 5.903
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.590
Fall : 5.692
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.726
Fall : 5.854
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.482
Fall : 5.521
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.820
Fall : 5.903
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.363
Fall : 5.393
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.649
Fall : 4.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.449
Fall : 4.536
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.487
Fall : 4.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.253
Fall : 4.359
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.439
Fall : 4.548
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.649
Fall : 4.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.334
Fall : 4.411
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.547
Fall : 4.697
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.198
Fall : 4.263
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 5.045
Fall : 4.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.045
Fall : 4.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.467
Fall : 3.470
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.638
Fall : 3.715
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.865
Fall : 3.962
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.736
Fall : 3.757
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.736
Fall : 3.757
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.606
Fall : 3.673
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.764
Fall : 3.886
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.764
Fall : 3.886
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.693
Fall : 3.752
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.523
Fall : 3.590
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.653
Fall : 3.739
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.712
Fall : 1.657
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.709
Fall : 1.654
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.708
Fall : 1.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.245
Fall : 2.951
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.711
Fall : 1.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.755
Fall : 1.683
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.758
Fall : 1.686
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.404
Fall : 4.492
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.714
Fall : 4.811
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.756
Fall : 4.806
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.404
Fall : 4.492
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.619
Fall : 4.708
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.805
Fall : 4.924
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.528
Fall : 4.559
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.418
Fall : 4.501
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.478
Fall : 4.502
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.074
Fall : 3.195
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.705
Fall : 3.857
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.537
Fall : 3.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.562
Fall : 3.684
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.074
Fall : 3.195
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.587
Fall : 3.750
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.787
Fall : 3.888
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.402
Fall : 3.449
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.246
Fall : 2.250
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.784
Fall : 3.550
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.246
Fall : 2.250
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.373
Fall : 2.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.590
Fall : 2.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.286
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.504
Fall : 2.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.286
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.428
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.428
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.190
Fall : 2.191
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.422
Fall : 2.474
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.385
Fall : 2.429
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.190
Fall : 2.191
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.315
Fall : 2.333
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.818
RF :
FR :
FF : 3.181
Input Port : SW[2]
Output Port : LED[2]
RR : 2.437
RF :
FR :
FF : 2.866
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.838
RF :
FR :
FF : 4.613
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.537
RF :
FR :
FF : 3.123
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.732
RF :
FR :
FF : 3.100
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.707
RF :
FR :
FF : 4.473
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.459
RF :
FR :
FF : 3.040
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -18.123
Hold : -0.053
Recovery : -6.223
Removal : 2.518
Minimum Pulse Width : 9.208
Clock : CLOCK_50
Setup : -18.123
Hold : -0.053
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 9.208
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -7.533
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 19.600
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.914
Hold : 0.177
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 35.491
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -4.740
Hold : 0.178
Recovery : -6.223
Removal : 2.518
Minimum Pulse Width : 20.591
Clock : Design-wide TNS
Setup : -879.875
Hold : -0.089
Recovery : -459.348
Removal : 0.0
Minimum Pulse Width : 0.0
Clock : CLOCK_50
Setup : -549.338
Hold : -0.089
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -284.813
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.914
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -42.810
Hold : 0.000
Recovery : -459.348
Removal : 0.000
Minimum Pulse Width : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.981
Fall : 2.458
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.874
Fall : 4.319
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.262
Fall : 1.505
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.823
Fall : 3.104
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.841
Fall : -1.690
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.690
Fall : -2.493
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.368
Fall : -0.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.742
Fall : -1.295
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.359
Fall : 10.359
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.359
Fall : 10.359
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.229
Fall : 9.317
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 10.015
Fall : 9.971
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.628
Fall : 9.644
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.826
Fall : 9.843
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.397
Fall : 9.318
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.972
Fall : 9.975
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.201
Fall : 9.152
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.986
Fall : 7.983
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.696
Fall : 7.696
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.783
Fall : 7.821
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.371
Fall : 7.388
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.739
Fall : 7.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.986
Fall : 7.975
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.534
Fall : 7.528
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.914
Fall : 7.983
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.285
Fall : 7.303
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.197
Fall : 7.907
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.197
Fall : 7.907
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.071
Fall : 5.974
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.410
Fall : 6.400
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.836
Fall : 6.810
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.558
Fall : 6.425
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.558
Fall : 6.425
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.366
Fall : 6.305
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.429
Fall : 6.279
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.429
Fall : 6.279
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.621
Fall : 6.664
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.621
Fall : 6.664
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.426
Fall : 6.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.231
Fall : 6.211
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.443
Fall : 6.428
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.404
Fall : 4.492
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.714
Fall : 4.811
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.756
Fall : 4.806
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.404
Fall : 4.492
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.619
Fall : 4.708
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.805
Fall : 4.924
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.528
Fall : 4.559
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.418
Fall : 4.501
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.478
Fall : 4.502
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.074
Fall : 3.195
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.705
Fall : 3.857
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.537
Fall : 3.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.562
Fall : 3.684
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.074
Fall : 3.195
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.587
Fall : 3.750
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.787
Fall : 3.888
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.402
Fall : 3.449
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.246
Fall : 2.250
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.784
Fall : 3.550
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.246
Fall : 2.250
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.373
Fall : 2.393
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.590
Fall : 2.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.286
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.504
Fall : 2.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.286
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.428
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.428
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.190
Fall : 2.191
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.422
Fall : 2.474
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.385
Fall : 2.429
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.190
Fall : 2.191
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.315
Fall : 2.333
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.629
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.626
RF :
FR :
FF : 7.003
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.318
RF :
FR :
FF : 4.517
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.732
RF :
FR :
FF : 3.100
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.707
RF :
FR :
FF : 4.473
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.459
RF :
FR :
FF : 3.040
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : SW[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : raw_loader_in
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_DAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_CLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : AUD_ADCDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 227
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1125
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 260
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1054
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1428
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 227
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1125
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 260
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1054
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1428
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Recovery Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Removal Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 2
Hold : 2
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 0
Hold : 0
Property : Unconstrained Output Port Paths
Setup : 0
Hold : 0
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Fri Apr 1 18:55:44 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'spectrum.sdc'
Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port
Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection
Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]}
Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin
Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock
Warning (332125): Found combinational loop of 511 nodes
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~9|datab"
Warning (332126): Node "z80_|alu_control_|db[0]~9|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~12|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~17|datab"
Warning (332126): Node "z80_|bus_control_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~8|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~8|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab"
Warning (332126): Node "z80_|alu_|db[0]~19|datac"
Warning (332126): Node "z80_|alu_|db[0]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~16|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~17|combout"
Warning (332126): Node "z80_|alu_|db[1]~13|datac"
Warning (332126): Node "z80_|alu_|db[1]~13|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~16|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~23|combout"
Warning (332126): Node "z80_|alu_|db[0]~18|datab"
Warning (332126): Node "z80_|alu_|db[0]~18|combout"
Warning (332126): Node "z80_|alu_|db[0]~19|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout"
Warning (332126): Node "z80_|alu_|db[1]~12|datac"
Warning (332126): Node "z80_|alu_|db[1]~12|combout"
Warning (332126): Node "z80_|alu_|db[1]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~2|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~2|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~3|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~3|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~24|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~24|combout"
Warning (332126): Node "z80_|alu_|db[2]~15|dataa"
Warning (332126): Node "z80_|alu_|db[2]~15|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~15|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab"
Warning (332126): Node "z80_|alu_|db[2]~14|datad"
Warning (332126): Node "z80_|alu_|db[2]~14|combout"
Warning (332126): Node "z80_|alu_|db[2]~15|datac"
Warning (332126): Node "z80_|alu_control_|db[2]~27|datab"
Warning (332126): Node "z80_|alu_control_|db[2]~27|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datad"
Warning (332126): Node "z80_|alu_control_|db[2]~29|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~12|datab"
Warning (332126): Node "z80_|bus_control_|db[2]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~13|datad"
Warning (332126): Node "z80_|bus_control_|db[2]~13|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa"
Warning (332126): Node "z80_|alu_control_|db[2]~28|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datac"
Warning (332126): Node "z80_|alu_|db[2]~14|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~7|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~8|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~8|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~11|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~11|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~25|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~25|combout"
Warning (332126): Node "z80_|alu_|db[3]~10|datad"
Warning (332126): Node "z80_|alu_|db[3]~10|combout"
Warning (332126): Node "z80_|alu_|db[3]~11|dataa"
Warning (332126): Node "z80_|alu_|db[3]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~34|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa"
Warning (332126): Node "z80_|alu_|db[3]~11|datac"
Warning (332126): Node "z80_|bus_control_|db[3]~21|datad"
Warning (332126): Node "z80_|bus_control_|db[3]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~12|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~10|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~10|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~25|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~26|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~26|combout"
Warning (332126): Node "z80_|alu_|db[4]~17|datac"
Warning (332126): Node "z80_|alu_|db[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout"
Warning (332126): Node "z80_|alu_|db[4]~16|datad"
Warning (332126): Node "z80_|alu_|db[4]~16|combout"
Warning (332126): Node "z80_|alu_|db[4]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~19|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~20|combout"
Warning (332126): Node "z80_|alu_|db[5]~25|dataa"
Warning (332126): Node "z80_|alu_|db[5]~25|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~15|datab"
Warning (332126): Node "z80_|alu_control_|db[5]~15|combout"
Warning (332126): Node "z80_|bus_control_|db[5]~15|datac"
Warning (332126): Node "z80_|bus_control_|db[5]~15|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~10|dataa"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|datab"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~14|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~15|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~18|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~13|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~14|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~14|combout"
Warning (332126): Node "z80_|alu_|db[6]~23|dataa"
Warning (332126): Node "z80_|alu_|db[6]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~6|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~7|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~8|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~8|combout"
Warning (332126): Node "z80_|alu_|db[7]~21|datac"
Warning (332126): Node "z80_|alu_|db[7]~21|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac"
Warning (332126): Node "z80_|alu_|db[7]~20|datac"
Warning (332126): Node "z80_|alu_|db[7]~20|combout"
Warning (332126): Node "z80_|alu_|db[7]~21|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~21|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~11|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~16|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~18|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~18|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~5|datab"
Warning (332126): Node "z80_|bus_control_|db[7]~5|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~7|datad"
Warning (332126): Node "z80_|bus_control_|db[7]~7|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~17|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa"
Warning (332126): Node "z80_|alu_|db[7]~20|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa"
Warning (332126): Node "z80_|alu_control_|db[6]~20|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~20|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~21|datac"
Warning (332126): Node "z80_|alu_control_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~22|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~8|datab"
Warning (332126): Node "z80_|bus_control_|db[6]~8|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa"
Warning (332126): Node "z80_|bus_control_|db[6]~9|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_|db[6]~22|datad"
Warning (332126): Node "z80_|alu_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_|db[6]~23|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~4|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~4|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~6|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~24|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~27|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~27|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|datac"
Warning (332126): Node "z80_|alu_|db[5]~24|datab"
Warning (332126): Node "z80_|alu_|db[5]~24|combout"
Warning (332126): Node "z80_|alu_|db[5]~25|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~14|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac"
Warning (332126): Node "z80_|alu_|db[5]~24|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datac"
Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa"
Warning (332126): Node "z80_|alu_control_|db[4]~30|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~31|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~32|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~32|combout"
Warning (332126): Node "z80_|bus_control_|db[4]~19|datab"
Warning (332126): Node "z80_|bus_control_|db[4]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datab"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~4|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~27|datab"
Warning (332126): Node "z80_|alu_|db[4]~16|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~30|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~4|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~27|datad"
Warning (332126): Node "z80_|sw1_|db_down[3]~1|datad"
Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~34|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac"
Warning (332126): Node "z80_|alu_|db[3]~10|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~2|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~24|datad"
Warning (332126): Node "z80_|alu_control_|db[1]~24|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|datad"
Warning (332126): Node "z80_|alu_control_|db[1]~26|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~10|datab"
Warning (332126): Node "z80_|bus_control_|db[1]~10|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~11|datac"
Warning (332126): Node "z80_|bus_control_|db[1]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa"
Warning (332126): Node "z80_|alu_control_|db[1]~25|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa"
Warning (332126): Node "z80_|alu_|db[1]~12|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa"
Warning (332126): Node "z80_|alu_|db[0]~18|datac"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|datad"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~9|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa"
Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop.
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -18.123
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -18.123 -549.338 CLOCK_50
Info (332119): -7.533 -284.813 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.740 -42.810 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.210
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.210 0.000 CLOCK_50
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -6.223
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.223 -459.348 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.698
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.698 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.488
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.488 0.000 CLOCK_50
Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.595 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -17.311
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -17.311 -526.609 CLOCK_50
Info (332119): -6.686 -253.661 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.428 -40.009 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.298
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.304 0.000 CLOCK_50
Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -5.744
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -5.744 -423.582 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.374
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.374 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.489
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.489 0.000 CLOCK_50
Info (332119): 19.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -14.971
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.971 -442.545 CLOCK_50
Info (332119): -4.979 -171.124 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -3.775 -35.541 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is -0.053
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.053 -0.089 CLOCK_50
Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -4.693
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.693 -358.284 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 2.518
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.208
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.208 0.000 CLOCK_50
Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings
Info: Peak virtual memory: 437 megabytes
Info: Processing ended: Fri Apr 1 18:55:48 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
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