115 lines
3.1 KiB
Verilog
115 lines
3.1 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 11:59:39 2014"
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module alu_select(
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ctl_alu_oe,
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ctl_alu_shift_oe,
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ctl_alu_op2_oe,
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ctl_alu_res_oe,
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ctl_alu_op1_oe,
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ctl_alu_bs_oe,
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ctl_alu_op1_sel_bus,
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ctl_alu_op1_sel_low,
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ctl_alu_op1_sel_zero,
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ctl_alu_op2_sel_zero,
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ctl_alu_op2_sel_bus,
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ctl_alu_op2_sel_lq,
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ctl_alu_sel_op2_neg,
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ctl_alu_sel_op2_high,
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ctl_alu_core_R,
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ctl_alu_core_V,
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ctl_alu_core_S,
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alu_oe,
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alu_shift_oe,
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alu_op2_oe,
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alu_res_oe,
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alu_op1_oe,
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alu_bs_oe,
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alu_op1_sel_bus,
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alu_op1_sel_low,
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alu_op1_sel_zero,
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alu_op2_sel_zero,
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alu_op2_sel_bus,
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alu_op2_sel_lq,
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alu_sel_op2_neg,
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alu_sel_op2_high,
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alu_core_R,
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alu_core_V,
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alu_core_S
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);
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input wire ctl_alu_oe;
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input wire ctl_alu_shift_oe;
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input wire ctl_alu_op2_oe;
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input wire ctl_alu_res_oe;
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input wire ctl_alu_op1_oe;
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input wire ctl_alu_bs_oe;
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input wire ctl_alu_op1_sel_bus;
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input wire ctl_alu_op1_sel_low;
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input wire ctl_alu_op1_sel_zero;
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input wire ctl_alu_op2_sel_zero;
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input wire ctl_alu_op2_sel_bus;
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input wire ctl_alu_op2_sel_lq;
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input wire ctl_alu_sel_op2_neg;
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input wire ctl_alu_sel_op2_high;
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input wire ctl_alu_core_R;
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input wire ctl_alu_core_V;
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input wire ctl_alu_core_S;
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output wire alu_oe;
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output wire alu_shift_oe;
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output wire alu_op2_oe;
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output wire alu_res_oe;
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output wire alu_op1_oe;
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output wire alu_bs_oe;
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output wire alu_op1_sel_bus;
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output wire alu_op1_sel_low;
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output wire alu_op1_sel_zero;
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output wire alu_op2_sel_zero;
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output wire alu_op2_sel_bus;
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output wire alu_op2_sel_lq;
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output wire alu_sel_op2_neg;
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output wire alu_sel_op2_high;
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output wire alu_core_R;
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output wire alu_core_V;
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output wire alu_core_S;
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assign alu_oe = ctl_alu_oe;
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assign alu_shift_oe = ctl_alu_shift_oe;
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assign alu_op2_oe = ctl_alu_op2_oe;
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assign alu_res_oe = ctl_alu_res_oe;
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assign alu_op1_oe = ctl_alu_op1_oe;
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assign alu_bs_oe = ctl_alu_bs_oe;
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assign alu_op1_sel_bus = ctl_alu_op1_sel_bus;
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assign alu_op1_sel_low = ctl_alu_op1_sel_low;
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assign alu_op1_sel_zero = ctl_alu_op1_sel_zero;
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assign alu_op2_sel_zero = ctl_alu_op2_sel_zero;
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assign alu_op2_sel_bus = ctl_alu_op2_sel_bus;
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assign alu_op2_sel_lq = ctl_alu_op2_sel_lq;
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assign alu_sel_op2_neg = ctl_alu_sel_op2_neg;
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assign alu_sel_op2_high = ctl_alu_sel_op2_high;
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assign alu_core_R = ctl_alu_core_R;
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assign alu_core_V = ctl_alu_core_V;
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assign alu_core_S = ctl_alu_core_S;
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endmodule
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