53 lines
919 B
Verilog
53 lines
919 B
Verilog
module spectrum(
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input CLOCK_50,
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output wire[7:0] LED
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);
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reg[13:0] address;
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wire[7:0] mem_data;
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rom0 rom(
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.address(address),
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.clock(CLOCK_50),
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.q(mem_data)
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);
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reg [15:0] A; // Global address bus
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wire [7:0] D; // CPU data bus
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wire [7:0] ram_data; // Internal 16K RAM data
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wire RamWE;
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// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;
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assign RamWE = 0;
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wire[12:0] vram_address;
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wire[7:0] vram_data;
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ram16 ram0(
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.clock(CLOCK_50),
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.address_a({12'b0, A[2:0]}),
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.data_a(D),
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.q_a(ram_data),
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.wren_a(0),
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// .address_b({1'b0, vram_address}),
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.address_b(A[13:0]),
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.data_b(8'b0),
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.q_b(vram_data),
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.wren_b(0)
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);
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reg[21:0] counter;
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always @(posedge CLOCK_50)
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begin
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counter <= counter + 1;
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if (counter == 0)
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begin
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address <= address + 1;
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A <= A + 1;
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end
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end
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assign LED[3:0] = ram_data[3:0];
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assign LED[7:4] = mem_data[7:4];
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endmodule |