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de0-zx-spectrum/output_files/spectrum.sta.rpt
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benny 114238753f WIP: sdram support
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TimeQuest Timing Analyzer report for spectrum
Sat Apr 2 14:51:17 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
17. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
21. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
22. Slow 1200mV 85C Model Hold: 'CLOCK_50'
23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
24. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
25. Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
27. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
28. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
29. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
30. Setup Times
31. Hold Times
32. Clock to Output Times
33. Minimum Clock to Output Times
34. Propagation Delay
35. Minimum Propagation Delay
36. Output Enable Times
37. Minimum Output Enable Times
38. Output Disable Times
39. Minimum Output Disable Times
40. Slow 1200mV 85C Model Metastability Report
41. Slow 1200mV 0C Model Fmax Summary
42. Slow 1200mV 0C Model Setup Summary
43. Slow 1200mV 0C Model Hold Summary
44. Slow 1200mV 0C Model Recovery Summary
45. Slow 1200mV 0C Model Removal Summary
46. Slow 1200mV 0C Model Minimum Pulse Width Summary
47. Slow 1200mV 0C Model Setup: 'CLOCK_50'
48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
50. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
51. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
52. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
54. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
55. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
56. Slow 1200mV 0C Model Hold: 'CLOCK_50'
57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
59. Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
60. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
61. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
62. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
63. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
64. Setup Times
65. Hold Times
66. Clock to Output Times
67. Minimum Clock to Output Times
68. Propagation Delay
69. Minimum Propagation Delay
70. Output Enable Times
71. Minimum Output Enable Times
72. Output Disable Times
73. Minimum Output Disable Times
74. Slow 1200mV 0C Model Metastability Report
75. Fast 1200mV 0C Model Setup Summary
76. Fast 1200mV 0C Model Hold Summary
77. Fast 1200mV 0C Model Recovery Summary
78. Fast 1200mV 0C Model Removal Summary
79. Fast 1200mV 0C Model Minimum Pulse Width Summary
80. Fast 1200mV 0C Model Setup: 'CLOCK_50'
81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
83. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
84. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
85. Fast 1200mV 0C Model Hold: 'CLOCK_50'
86. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
88. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
89. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
93. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
94. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
95. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
96. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
97. Setup Times
98. Hold Times
99. Clock to Output Times
100. Minimum Clock to Output Times
101. Propagation Delay
102. Minimum Propagation Delay
103. Output Enable Times
104. Minimum Output Enable Times
105. Output Disable Times
106. Minimum Output Disable Times
107. Fast 1200mV 0C Model Metastability Report
108. Multicorner Timing Analysis Summary
109. Setup Times
110. Hold Times
111. Clock to Output Times
112. Minimum Clock to Output Times
113. Propagation Delay
114. Minimum Propagation Delay
115. Board Trace Model Assignments
116. Input Transition Times
117. Signal Integrity Metrics (Slow 1200mv 0c Model)
118. Signal Integrity Metrics (Slow 1200mv 85c Model)
119. Signal Integrity Metrics (Fast 1200mv 0c Model)
120. Setup Transfers
121. Hold Transfers
122. Recovery Transfers
123. Removal Transfers
124. Report TCCS
125. Report RSKM
126. Unconstrained Paths
127. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; SDC File List ;
+--------------------------------------------------------------------------------+
SDC File Path : spectrum.sdc
Status : OK
Read at : Sat Apr 2 14:51:14 2022
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : beep
Type : Base
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { ula:ula_|beep }
Clock Name : CLOCK_50
Type : Base
Period : 20.000
Frequency : 50.0 MHz
Rise : 0.000
Fall : 10.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 3.000
Fall : 8.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase : 108.0
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 39.716
Frequency : 25.18 MHz
Rise : 0.000
Fall : 19.858
Duty Cycle : 50.00
Divide by : 280
Multiply by : 141
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 71.489
Frequency : 13.99 MHz
Rise : 0.000
Fall : 35.744
Duty Cycle : 50.00
Divide by : 168
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Type : Generated
Period : 41.702
Frequency : 23.98 MHz
Rise : 0.000
Fall : 20.851
Duty Cycle : 50.00
Divide by : 98
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 48.03 MHz
Restricted Fmax : 48.03 MHz
Clock Name : CLOCK_50
Note :
Fmax : 118.6 MHz
Restricted Fmax : 118.6 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 153.92 MHz
Restricted Fmax : 153.92 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 163.48 MHz
Restricted Fmax : 163.48 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 940.73 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -18.571
End Point TNS : -821.372
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -7.747
End Point TNS : -287.138
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.731
End Point TNS : -41.432
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.915
End Point TNS : -2.915
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 3.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.357
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.359
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.373
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -6.212
End Point TNS : -460.730
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.666
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.752
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.488
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.602
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.597
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -18.571
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.393
Slack : -18.455
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.277
Slack : -18.451
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.292
Slack : -18.439
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.261
Slack : -18.432
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 8.001
Slack : -18.426
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.267
Slack : -18.398
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.956
Slack : -18.391
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.950
Slack : -18.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.954
Slack : -18.372
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.194
Slack : -18.364
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.186
Slack : -18.356
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.178
Slack : -18.353
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.194
Slack : -18.347
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.169
Slack : -18.345
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 8.170
Slack : -18.344
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.166
Slack : -18.335
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.157
Slack : -18.314
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.136
Slack : -18.303
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.144
Slack : -18.300
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.122
Slack : -18.275
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.833
Slack : -18.250
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.808
Slack : -18.211
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.033
Slack : -18.206
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.028
Slack : -18.202
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.024
Slack : -18.186
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 7.755
Slack : -18.180
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.002
Slack : -18.178
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 8.000
Slack : -18.177
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.018
Slack : -18.155
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.977
Slack : -18.153
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.975
Slack : -18.147
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.707
Slack : -18.145
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.704
Slack : -18.143
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.708
Slack : -18.107
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.948
Slack : -18.102
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.667
Slack : -18.073
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.895
Slack : -18.071
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.893
Slack : -18.024
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.584
Slack : -18.018
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.578
Slack : -18.010
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.566
Slack : -18.004
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.562
Slack : -18.001
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.823
Slack : -17.982
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.542
Slack : -17.978
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.819
Slack : -17.976
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.541
Slack : -17.956
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.516
Slack : -17.947
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.507
Slack : -17.932
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.754
Slack : -17.932
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.492
Slack : -17.925
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.747
Slack : -17.903
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.744
Slack : -17.890
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.712
Slack : -17.876
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.430
Slack : -17.873
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.423
Slack : -17.872
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.431
Slack : -17.864
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.686
Slack : -17.859
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.681
Slack : -17.850
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.400
Slack : -17.841
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.682
Slack : -17.827
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.668
Slack : -17.807
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.366
Slack : -17.805
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.366
Slack : -17.804
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.645
Slack : -17.794
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.344
Slack : -17.788
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.338
Slack : -17.757
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.316
Slack : -17.746
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.305
Slack : -17.732
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.282
Slack : -17.731
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.572
Slack : -17.706
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.547
Slack : -17.698
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.539
Slack : -17.680
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.521
Slack : -17.670
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.220
Slack : -17.660
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.223
Slack : -17.659
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.500
Slack : -17.636
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.477
Slack : -17.620
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.180
Slack : -17.610
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.173
Slack : -17.600
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.159
Slack : -17.593
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.156
Slack : -17.587
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.146
Slack : -17.580
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.252
Data Delay : 7.402
Slack : -17.569
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.125
Slack : -17.563
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 7.114
Slack : -17.546
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.387
Slack : -17.538
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.088
Slack : -17.528
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.089
Slack : -17.490
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 7.057
Slack : -17.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.045
Slack : -17.486
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.327
Slack : -17.477
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.318
Slack : -17.452
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.293
Slack : -17.450
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.009
Slack : -17.443
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.284
Slack : -17.435
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 6.989
Slack : -17.430
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.989
Slack : -17.401
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.951
Slack : -17.399
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.962
Slack : -17.396
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.237
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -7.747
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 5.558
Slack : -7.745
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 5.551
Slack : -7.636
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 5.495
Slack : -7.634
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 5.488
Slack : -7.563
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.298
Data Delay : 5.373
Slack : -7.492
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 5.303
Slack : -7.475
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 5.296
Slack : -7.464
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.305
Data Delay : 5.267
Slack : -7.437
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 5.246
Slack : -7.436
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 5.265
Slack : -7.401
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 5.218
Slack : -7.381
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 5.208
Slack : -7.356
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 5.215
Slack : -7.345
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 5.151
Slack : -7.333
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 5.150
Slack : -7.320
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 5.126
Slack : -7.316
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 5.125
Slack : -7.296
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 5.109
Slack : -7.289
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 5.113
Slack : -7.233
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 5.052
Slack : -7.232
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 5.097
Slack : -7.222
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 5.087
Slack : -7.177
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 5.040
Slack : -7.165
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.305
Data Delay : 4.968
Slack : -7.163
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.263
Data Delay : 5.008
Slack : -7.159
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.974
Slack : -7.148
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.959
Slack : -7.147
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.972
Slack : -7.143
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 4.949
Slack : -7.136
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.951
Slack : -7.117
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.933
Slack : -7.103
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.275
Data Delay : 4.936
Slack : -7.093
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.947
Slack : -7.091
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 4.909
Slack : -7.085
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.945
Slack : -7.072
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 4.890
Slack : -7.066
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.882
Slack : -7.062
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.247
Data Delay : 4.923
Slack : -7.059
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.874
Slack : -7.038
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.247
Data Delay : 4.899
Slack : -7.037
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.300
Data Delay : 4.845
Slack : -7.020
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.296
Data Delay : 4.832
Slack : -7.018
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.299
Data Delay : 4.827
Slack : -7.015
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.288
Data Delay : 4.835
Slack : -7.006
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.872
Slack : -6.994
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.296
Data Delay : 4.806
Slack : -6.987
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 4.804
Slack : -6.984
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.821
Slack : -6.978
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 4.805
Slack : -6.978
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.260
Data Delay : 4.826
Slack : -6.960
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.294
Data Delay : 4.774
Slack : -6.960
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.300
Data Delay : 4.768
Slack : -6.959
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 4.811
Slack : -6.955
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.819
Slack : -6.953
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.807
Slack : -6.953
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 4.772
Slack : -6.945
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 5.049
Slack : -6.929
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.793
Slack : -6.919
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.775
Slack : -6.917
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.732
Slack : -6.914
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.760
Slack : -6.910
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.775
Slack : -6.909
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.766
Slack : -6.899
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 4.768
Slack : -6.895
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 4.713
Slack : -6.893
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.268
Data Delay : 4.733
Slack : -6.886
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 4.709
Slack : -6.860
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.684
Slack : -6.856
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.712
Slack : -6.854
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.705
Slack : -6.852
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.716
Slack : -6.852
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.294
Data Delay : 4.666
Slack : -6.851
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.714
Slack : -6.836
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.660
Slack : -6.829
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.695
Slack : -6.825
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.234
Data Delay : 4.699
Slack : -6.824
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.640
Slack : -6.824
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.259
Data Delay : 4.673
Slack : -6.822
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 4.633
Slack : -6.807
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.635
Slack : -6.783
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.611
Slack : -6.779
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.266
Data Delay : 4.621
Slack : -6.770
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.236
Data Delay : 4.642
Slack : -6.757
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.572
Slack : -6.723
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.579
Slack : -6.709
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.560
Slack : -6.707
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 4.522
Slack : -6.705
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.255
Data Delay : 4.558
Slack : -6.704
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 4.523
Slack : -6.703
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.547
Slack : -6.678
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 4.547
Slack : -6.655
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.520
Slack : -6.649
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 4.472
Slack : -6.642
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.499
Slack : -6.642
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.470
Slack : -6.633
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.255
Data Delay : 4.486
Slack : -6.617
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.433
Slack : -6.608
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.473
Slack : -6.605
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.471
Slack : -6.597
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.265
Data Delay : 4.440
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.731
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 2.822
Slack : -4.573
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.791
Slack : -4.573
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.791
Slack : -4.102
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.671
Slack : -4.102
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.671
Slack : -4.102
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.671
Slack : -4.102
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.671
Slack : -4.102
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.671
Slack : -3.948
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.166
Slack : -3.097
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.199
Data Delay : 1.675
Slack : 16.635
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.779
Slack : 16.649
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.765
Slack : 16.792
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.622
Slack : 16.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.600
Slack : 16.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.600
Slack : 16.832
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.586
Slack : 16.832
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.586
Slack : 16.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.572
Slack : 16.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.572
Slack : 16.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.572
Slack : 16.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.572
Slack : 16.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.572
Slack : 16.851
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.563
Slack : 16.851
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.563
Slack : 16.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.558
Slack : 16.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.558
Slack : 16.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.558
Slack : 16.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.558
Slack : 16.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.558
Slack : 16.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.549
Slack : 16.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.549
Slack : 16.889
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.525
Slack : 16.975
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.443
Slack : 16.975
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.443
Slack : 16.999
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.415
Slack : 16.999
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.415
Slack : 16.999
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.415
Slack : 16.999
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.415
Slack : 16.999
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.415
Slack : 17.004
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.410
Slack : 17.004
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.410
Slack : 17.072
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.346
Slack : 17.072
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 3.346
Slack : 17.096
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.318
Slack : 17.096
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.318
Slack : 17.096
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.318
Slack : 17.096
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.318
Slack : 17.096
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.318
Slack : 17.105
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.309
Slack : 17.105
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.309
Slack : 17.223
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.073
Data Delay : 3.550
Slack : 17.237
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.073
Data Delay : 3.536
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.170
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.170
Slack : 17.260
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.156
Slack : 17.260
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.156
Slack : 17.297
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.117
Slack : 17.377
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.073
Data Delay : 3.396
Slack : 17.399
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.015
Slack : 17.403
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.013
Slack : 17.403
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.013
Slack : 17.477
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.073
Data Delay : 3.296
Slack : 17.480
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 2.938
Slack : 17.480
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 2.938
Slack : 17.500
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.916
Slack : 17.500
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.916
Slack : 17.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.910
Slack : 17.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.910
Slack : 17.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.910
Slack : 17.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.910
Slack : 17.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.910
Slack : 17.513
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.901
Slack : 17.513
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.901
Slack : 17.559
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.855
Slack : 17.559
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.855
Slack : 17.559
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.855
Slack : 17.559
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.855
Slack : 17.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.841
Slack : 17.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.841
Slack : 17.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.841
Slack : 17.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.841
Slack : 17.582
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 2.836
Slack : 17.582
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.428
Data Delay : 2.836
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.808
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.808
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.808
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.808
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.808
Slack : 17.615
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.799
Slack : 17.615
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.799
Slack : 17.623
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.144
Slack : 17.623
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.144
Slack : 17.623
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.144
Slack : 17.623
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.144
Slack : 17.623
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.144
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.130
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.130
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.130
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.130
Slack : 17.637
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.130
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.915
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.216
Data Delay : 1.509
Slack : 70.426
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.980
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 3.503
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.345
Slack : 3.528
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.320
Slack : 3.604
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.234
Slack : 3.637
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.211
Slack : 3.639
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.199
Slack : 3.658
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.180
Slack : 3.662
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.186
Slack : 3.687
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 6.153
Slack : 3.712
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 6.136
Slack : 3.722
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 6.118
Slack : 3.741
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 6.099
Slack : 3.768
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.070
Slack : 3.768
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.070
Slack : 3.785
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.053
Slack : 3.804
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 6.034
Slack : 3.851
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.989
Slack : 3.851
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.989
Slack : 3.868
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.972
Slack : 3.887
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.953
Slack : 3.892
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.946
Slack : 3.936
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.902
Slack : 3.975
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.865
Slack : 3.988
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.853
Slack : 4.000
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.830
Slack : 4.007
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.831
Slack : 4.019
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.821
Slack : 4.023
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.818
Slack : 4.041
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.797
Slack : 4.042
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.799
Slack : 4.052
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.778
Slack : 4.055
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.790
Slack : 4.068
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.747
Slack : 4.080
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.765
Slack : 4.090
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.750
Slack : 4.103
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.712
Slack : 4.107
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.723
Slack : 4.122
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.693
Slack : 4.124
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.716
Slack : 4.130
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.720
Slack : 4.142
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.703
Slack : 4.152
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.689
Slack : 4.152
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.689
Slack : 4.164
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.679
Slack : 4.167
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.663
Slack : 4.167
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.678
Slack : 4.169
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.672
Slack : 4.176
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.646
Slack : 4.188
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.653
Slack : 4.189
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.656
Slack : 4.196
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.634
Slack : 4.214
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.631
Slack : 4.232
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.583
Slack : 4.232
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.583
Slack : 4.236
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.586
Slack : 4.241
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.609
Slack : 4.243
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.563
Slack : 4.249
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.566
Slack : 4.258
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.548
Slack : 4.262
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.544
Slack : 4.264
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.581
Slack : 4.268
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.547
Slack : 4.276
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.565
Slack : 4.276
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.569
Slack : 4.283
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.539
Slack : 4.301
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.544
Slack : 4.320
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.526
Slack : 4.320
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.521
Slack : 4.343
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.479
Slack : 4.345
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.461
Slack : 4.345
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.501
Slack : 4.351
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 5.494
Slack : 4.353
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.453
Slack : 4.356
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.459
Slack : 4.361
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.056
Data Delay : 5.481
Slack : 4.361
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.056
Data Delay : 5.481
Slack : 4.361
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.479
Slack : 4.372
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.078
Data Delay : 5.450
Slack : 4.389
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 5.443
Slack : 4.391
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.450
Slack : 4.400
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.415
Slack : 4.406
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.400
Slack : 4.423
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.070
Data Delay : 5.407
Slack : 4.425
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.416
Slack : 4.426
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.420
Slack : 4.430
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.376
Slack : 4.454
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.392
Slack : 4.471
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.344
Slack : 4.479
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.367
Slack : 4.480
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.361
Slack : 4.502
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.336
Slack : 4.505
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.085
Data Delay : 5.310
Slack : 4.507
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.299
Slack : 4.509
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 5.317
Slack : 4.512
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.094
Data Delay : 5.294
Slack : 4.529
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 5.317
Slack : 4.535
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.309
Slack : 4.546
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.279
Slack : 4.573
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.087
Data Delay : 5.240
Slack : 4.583
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 5.264
Slack : 4.585
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 5.255
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.575
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.810
Slack : 1.322
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.636
Data Delay : 1.188
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.342
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.342
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.346
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.580
Slack : 0.357
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.362
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.597
Slack : 0.371
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.591
Slack : 0.372
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.592
Slack : 0.372
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.592
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.375
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.595
Slack : 0.376
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.595
Slack : 0.386
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.605
Slack : 0.386
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.605
Slack : 0.439
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.425
Data Delay : 1.021
Slack : 0.460
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.436
Data Delay : 1.053
Slack : 0.510
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.729
Slack : 0.534
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.753
Slack : 0.542
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.762
Slack : 0.542
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.777
Slack : 0.544
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.779
Slack : 0.545
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.780
Slack : 0.550
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.769
Slack : 0.551
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.771
Slack : 0.552
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.772
Slack : 0.552
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.772
Slack : 0.553
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.553
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.553
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.772
Slack : 0.554
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.773
Slack : 0.555
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.790
Slack : 0.558
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.777
Slack : 0.561
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.562
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.781
Slack : 0.570
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.790
Slack : 0.574
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.793
Slack : 0.575
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.794
Slack : 0.582
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.801
Slack : 0.583
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.802
Slack : 0.585
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.819
Slack : 0.588
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.822
Slack : 0.589
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.823
Slack : 0.590
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.459
Data Delay : 1.206
Slack : 0.591
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.825
Slack : 0.607
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.826
Slack : 0.610
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.844
Slack : 0.697
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.457
Data Delay : 1.311
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.920
Slack : 0.703
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.922
Slack : 0.704
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.923
Slack : 0.704
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.939
Slack : 0.708
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.943
Slack : 0.708
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.927
Slack : 0.710
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.929
Slack : 0.712
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.931
Slack : 0.722
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.285
Data Delay : 0.594
Slack : 0.733
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.952
Slack : 0.734
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.953
Slack : 0.740
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.457
Data Delay : 1.354
Slack : 0.753
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.973
Slack : 0.755
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.974
Slack : 0.769
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.051
Data Delay : 0.977
Slack : 0.774
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.993
Slack : 0.789
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.008
Slack : 0.807
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.051
Data Delay : 1.015
Slack : 0.809
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.028
Slack : 0.816
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.035
Slack : 0.817
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.052
Slack : 0.819
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.054
Slack : 0.820
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.039
Slack : 0.830
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.049
Slack : 0.832
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.067
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.834
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.834
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.069
Slack : 0.835
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.070
Slack : 0.840
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.059
Slack : 0.841
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.060
Slack : 0.844
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.063
Slack : 0.847
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.850
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.069
Slack : 0.852
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.073
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.551
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.771
Slack : 0.553
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.587
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.807
Slack : 0.702
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.922
Slack : 0.804
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 1.037
Slack : 0.825
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.045
Slack : 0.877
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.095
Slack : 0.886
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.105
Slack : 0.897
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 0.790
Slack : 0.937
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.155
Slack : 0.976
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.196
Slack : 0.978
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.198
Slack : 1.003
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.221
Slack : 1.010
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.228
Slack : 1.014
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.232
Slack : 1.103
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.323
Slack : 1.108
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.000
Slack : 1.110
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.002
Slack : 1.115
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.007
Slack : 1.141
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.359
Slack : 1.148
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.366
Slack : 1.157
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.375
Slack : 1.175
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.068
Slack : 1.177
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.070
Slack : 1.195
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.413
Slack : 1.203
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.422
Slack : 1.222
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.441
Slack : 1.229
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.448
Slack : 1.231
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.449
Slack : 1.232
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.450
Slack : 1.237
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.455
Slack : 1.239
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.458
Slack : 1.240
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.132
Slack : 1.256
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.475
Slack : 1.258
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.150
Slack : 1.258
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.476
Slack : 1.258
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.477
Slack : 1.266
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.130
Slack : 1.268
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.132
Slack : 1.270
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.134
Slack : 1.292
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.156
Slack : 1.294
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.158
Slack : 1.294
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.513
Slack : 1.295
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.514
Slack : 1.304
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.168
Slack : 1.322
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.541
Slack : 1.324
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.543
Slack : 1.326
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.545
Slack : 1.332
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.551
Slack : 1.356
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.576
Slack : 1.356
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.576
Slack : 1.364
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.582
Slack : 1.368
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.587
Slack : 1.404
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.624
Slack : 1.414
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.306
Slack : 1.414
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.633
Slack : 1.416
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.636
Slack : 1.416
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.635
Slack : 1.431
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.293
Data Delay : 1.295
Slack : 1.436
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.655
Slack : 1.486
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.705
Slack : 1.496
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.715
Slack : 1.505
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.724
Slack : 1.511
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.731
Slack : 1.518
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.737
Slack : 1.526
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.745
Slack : 1.532
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.752
Slack : 1.533
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.753
Slack : 1.558
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.776
Slack : 1.562
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.782
Slack : 1.575
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 1.467
Slack : 1.582
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.800
Slack : 1.584
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.804
Slack : 1.584
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.804
Slack : 1.584
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.804
Slack : 1.584
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.804
Slack : 1.584
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.804
Slack : 1.588
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.808
Slack : 1.596
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.815
Slack : 1.610
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.829
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
Slack : 1.613
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 2.205
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.359
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.362
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.580
Slack : 0.379
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.597
Slack : 0.521
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.739
Slack : 0.557
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.775
Slack : 0.558
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.776
Slack : 0.558
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.776
Slack : 0.559
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.777
Slack : 0.559
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.777
Slack : 0.560
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.778
Slack : 0.561
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.779
Slack : 0.561
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.779
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.563
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.564
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.782
Slack : 0.570
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.788
Slack : 0.571
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.789
Slack : 0.571
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.789
Slack : 0.572
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.790
Slack : 0.573
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.791
Slack : 0.573
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.791
Slack : 0.575
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.793
Slack : 0.580
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.798
Slack : 0.592
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.810
Slack : 0.594
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.812
Slack : 0.608
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.826
Slack : 0.612
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.830
Slack : 0.612
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.830
Slack : 0.818
From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.037
Slack : 0.822
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.041
Slack : 0.829
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.047
Slack : 0.832
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.050
Slack : 0.832
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.050
Slack : 0.833
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.051
Slack : 0.834
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.834
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.836
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.054
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.064
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.847
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.847
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.066
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.066
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.849
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.851
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.069
Slack : 0.852
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.070
Slack : 0.860
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.078
Slack : 0.860
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.078
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.079
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.862
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.080
Slack : 0.864
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.082
Slack : 0.864
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.082
Slack : 0.864
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.082
Slack : 0.866
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.084
Slack : 0.894
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.112
Slack : 0.909
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.127
Slack : 0.909
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.127
Slack : 0.942
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.160
Slack : 0.942
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.160
Slack : 0.944
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.946
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.956
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.174
Slack : 0.957
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.175
Slack : 0.958
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.176
Slack : 0.959
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.959
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.960
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.178
Slack : 0.960
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.178
Slack : 0.961
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.179
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.964
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.182
Slack : 0.970
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.189
Slack : 0.971
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.189
Slack : 0.972
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.190
Slack : 0.972
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.190
Slack : 0.973
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.191
Slack : 0.974
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.192
Slack : 0.974
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.192
Slack : 0.974
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.192
Slack : 0.974
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.192
Slack : 0.976
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.194
Slack : 0.976
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.194
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.373
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.592
Slack : 0.577
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.637
Data Delay : 3.505
Slack : 0.605
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.640
Data Delay : 3.536
Slack : 0.812
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.636
Data Delay : 3.739
Slack : 0.837
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.637
Data Delay : 3.765
Slack : 1.263
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.357
Data Delay : 3.911
Slack : 1.267
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.643
Data Delay : 4.201
Slack : 1.304
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.648
Data Delay : 4.243
Slack : 1.329
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.181
Slack : 1.335
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.645
Data Delay : 4.271
Slack : 1.345
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.654
Data Delay : 4.290
Slack : 1.345
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.641
Data Delay : 4.277
Slack : 1.346
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.348
Data Delay : 3.985
Slack : 1.356
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.646
Data Delay : 4.293
Slack : 1.359
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.348
Data Delay : 3.998
Slack : 1.360
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.208
Slack : 1.372
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.643
Data Delay : 4.306
Slack : 1.378
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.351
Data Delay : 4.020
Slack : 1.379
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.641
Data Delay : 4.311
Slack : 1.381
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.645
Data Delay : 4.317
Slack : 1.385
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.237
Slack : 1.402
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.646
Data Delay : 4.339
Slack : 1.405
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.269
Slack : 1.407
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.363
Data Delay : 4.061
Slack : 1.409
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.648
Data Delay : 4.348
Slack : 1.411
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.636
Data Delay : 4.338
Slack : 1.413
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.361
Data Delay : 4.065
Slack : 1.415
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.276
Slack : 1.415
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.356
Data Delay : 4.062
Slack : 1.421
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.276
Slack : 1.423
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.271
Slack : 1.426
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.287
Slack : 1.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.632
Data Delay : 4.351
Slack : 1.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.364
Data Delay : 4.083
Slack : 1.429
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.279
Slack : 1.429
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.352
Data Delay : 4.072
Slack : 1.431
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.278
Slack : 1.433
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.294
Slack : 1.434
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.362
Data Delay : 4.087
Slack : 1.436
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.637
Data Delay : 4.364
Slack : 1.438
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.302
Slack : 1.438
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.286
Slack : 1.442
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.339
Data Delay : 4.072
Slack : 1.443
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.307
Slack : 1.443
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.298
Slack : 1.444
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 4.283
Slack : 1.447
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.308
Slack : 1.448
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.292
Slack : 1.450
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.298
Slack : 1.450
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.353
Data Delay : 4.094
Slack : 1.453
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.296
Slack : 1.457
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.321
Slack : 1.458
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.308
Slack : 1.459
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.314
Slack : 1.460
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.312
Slack : 1.462
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.315
Slack : 1.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.632
Data Delay : 4.385
Slack : 1.463
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.315
Slack : 1.464
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.319
Slack : 1.465
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.654
Data Delay : 4.410
Slack : 1.468
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.645
Data Delay : 4.404
Slack : 1.474
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.318
Slack : 1.477
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.634
Data Delay : 4.402
Slack : 1.477
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 4.316
Slack : 1.479
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.334
Slack : 1.479
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.320
Slack : 1.487
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.337
Slack : 1.489
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.344
Slack : 1.494
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 4.333
Slack : 1.497
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.341
Data Delay : 4.129
Slack : 1.500
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.352
Slack : 1.504
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.356
Slack : 1.506
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.370
Slack : 1.508
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.361
Slack : 1.508
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.354
Data Delay : 4.153
Slack : 1.510
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.362
Slack : 1.510
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.354
Slack : 1.513
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.368
Slack : 1.513
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.356
Slack : 1.518
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.362
Slack : 1.519
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.369
Slack : 1.519
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.363
Slack : 1.519
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.360
Slack : 1.520
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.643
Data Delay : 4.454
Slack : 1.521
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.351
Data Delay : 4.163
Slack : 1.523
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.373
Slack : 1.523
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.367
Slack : 1.523
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.352
Data Delay : 4.166
Slack : 1.524
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 4.363
Slack : 1.525
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.373
Slack : 1.526
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 4.365
Slack : 1.527
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.379
Slack : 1.527
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.371
Slack : 1.527
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.382
Slack : 1.527
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.379
Slack : 1.529
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.376
Slack : 1.530
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.371
Slack : 1.531
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.377
Data Delay : 4.199
Slack : 1.534
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.381
Slack : 1.534
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.375
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -6.212
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 4.333
Slack : -6.212
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 4.331
Slack : -6.212
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.330
Slack : -6.212
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 4.329
Slack : -6.211
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.329
Slack : -5.960
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.195
Data Delay : 4.049
Slack : -5.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 4.050
Slack : -5.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.912
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.913
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.913
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.913
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.915
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.159
Data Delay : 3.915
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.911
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.913
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.160
Data Delay : 3.914
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.686
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.149
Data Delay : 3.916
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.911
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.911
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.911
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.911
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.345
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.912
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.913
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.913
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.913
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.913
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.913
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.910
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.910
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.187
Data Delay : 3.910
Slack : -5.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.186
Data Delay : 3.909
Slack : -5.340
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.915
Slack : -5.338
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.199
Data Delay : 3.916
Slack : -5.335
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.199
Data Delay : 3.913
Slack : -5.320
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.212
Data Delay : 3.911
Slack : -5.320
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.212
Data Delay : 3.911
Slack : -5.316
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.218
Data Delay : 3.913
Slack : -5.316
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.218
Data Delay : 3.913
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.666
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.638
Data Delay : 3.545
Slack : 3.666
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.638
Data Delay : 3.545
Slack : 3.668
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.632
Data Delay : 3.541
Slack : 3.668
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.632
Data Delay : 3.541
Slack : 3.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.618
Data Delay : 3.543
Slack : 3.687
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.619
Data Delay : 3.547
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.690
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.546
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.540
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.540
Slack : 3.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.540
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.541
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.541
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.541
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.541
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.539
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.050
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.256
Data Delay : 3.547
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.242
Data Delay : 3.543
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.546
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.245
Data Delay : 3.546
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.280
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.192
Data Delay : 3.657
Slack : 4.280
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.190
Data Delay : 3.655
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 3.909
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.908
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 3.907
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.225
Data Delay : 3.912
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.909
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.753
Actual Width : 4.969
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.758
Actual Width : 4.974
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.758
Actual Width : 4.974
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.759
Actual Width : 4.975
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.759
Actual Width : 4.975
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.759
Actual Width : 4.975
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.830
Actual Width : 4.985
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.830
Actual Width : 4.985
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.833
Actual Width : 4.988
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.840
Actual Width : 5.024
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.840
Actual Width : 5.024
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.840
Actual Width : 5.024
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.840
Actual Width : 5.024
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.840
Actual Width : 5.024
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.843
Actual Width : 5.027
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.845
Actual Width : 5.029
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.845
Actual Width : 5.029
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[4]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.604
Actual Width : 20.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.605
Actual Width : 20.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.610
Actual Width : 20.826
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.610
Actual Width : 20.826
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.693
Actual Width : 20.848
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.693
Actual Width : 20.877
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.694
Actual Width : 20.878
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.694
Actual Width : 20.878
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.548
Fall : 1.931
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.846
Fall : 4.271
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.221
Fall : 1.461
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.814
Fall : 3.095
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.154
Fall : -1.552
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.539
Fall : -2.918
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.395
Fall : -0.661
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.395
Fall : -0.661
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.602
Fall : -0.833
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.346
Fall : -1.585
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.801
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 10.164
Fall : 10.160
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 10.350
Fall : 10.351
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 10.114
Fall : 10.074
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 10.072
Fall : 10.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.376
Fall : 10.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 10.482
Fall : 10.574
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 10.801
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 10.294
Fall : 10.222
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.527
Fall : 10.543
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.022
Fall : 10.010
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 10.153
Fall : 10.157
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 10.039
Fall : 10.024
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.790
Fall : 9.910
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 10.258
Fall : 10.260
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 10.080
Fall : 10.129
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 10.527
Fall : 10.543
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.684
Fall : 9.676
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.430
Fall : 3.345
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.430
Fall : 3.345
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.426
Fall : 3.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.248
Fall : 6.300
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.552
Fall : 5.647
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.839
Fall : 5.898
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.545
Fall : 5.576
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.269
Fall : 5.330
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.626
Fall : 5.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.718
Fall : 5.830
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.584
Fall : 5.653
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.733
Fall : 5.777
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 6.248
Fall : 6.299
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 6.038
Fall : 6.073
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 6.021
Fall : 6.053
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 6.021
Fall : 6.053
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 6.215
Fall : 6.300
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 6.241
Fall : 6.286
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 6.241
Fall : 6.286
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.859
Fall : 5.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.426
Fall : 3.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.525
Fall : 8.506
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.614
Fall : 7.674
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.796
Fall : 7.806
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.092
Fall : 8.080
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.910
Fall : 8.021
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.495
Fall : 8.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.018
Fall : 8.084
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.525
Fall : 8.506
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.947
Fall : 7.936
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.377
Fall : 8.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.472
Fall : 7.524
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.599
Fall : 7.612
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.017
Fall : 8.030
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.628
Fall : 7.694
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.377
Fall : 8.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.619
Fall : 7.643
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.251
Fall : 8.260
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.224
Fall : 7.248
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.645
Fall : 8.352
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.645
Fall : 8.352
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 7.356
Fall : 7.355
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.643
Fall : 6.643
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.647
Fall : 6.639
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.282
Fall : 6.183
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.690
Fall : 6.712
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 7.297
Fall : 7.345
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.937
Fall : 6.925
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 7.297
Fall : 7.345
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.690
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.641
Fall : 6.567
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.830
Fall : 7.818
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.061
Fall : 8.083
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 8.174
Fall : 8.205
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.830
Fall : 7.818
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 8.228
Fall : 8.280
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.428
Fall : 8.466
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.693
Fall : 8.718
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.284
Fall : 8.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 8.683
Fall : 8.600
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.760
Fall : 7.774
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.924
Fall : 7.938
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.985
Fall : 8.020
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.760
Fall : 7.774
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.962
Fall : 7.971
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.306
Fall : 8.338
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.306
Fall : 8.291
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.017
Fall : 8.062
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.101
Fall : 8.081
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.901
Fall : 2.814
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.876
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.009
Fall : 2.924
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.006
Fall : 2.921
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.562
Fall : 4.614
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.973
Fall : 5.061
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.248
Fall : 5.301
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.963
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.700
Fall : 4.753
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.044
Fall : 5.095
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.134
Fall : 5.235
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.945
Fall : 5.002
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.145
Fall : 5.183
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 4.931
Fall : 4.977
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 4.730
Fall : 4.760
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.713
Fall : 4.741
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.713
Fall : 4.741
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 4.900
Fall : 4.977
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.924
Fall : 4.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.924
Fall : 4.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.562
Fall : 4.614
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.006
Fall : 2.921
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.003
Fall : 2.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.164
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.093
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.189
Fall : 6.209
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.676
Fall : 6.693
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.674
Fall : 6.676
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.005
Fall : 6.988
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.630
Fall : 6.784
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.357
Fall : 6.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.848
Fall : 6.958
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.189
Fall : 6.209
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.027
Fall : 7.015
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.922
Fall : 5.969
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.539
Fall : 6.548
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.485
Fall : 6.491
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.935
Fall : 6.944
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.364
Fall : 6.475
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.235
Fall : 6.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.464
Fall : 6.535
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.922
Fall : 5.969
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.372
Fall : 6.397
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 4.408
Fall : 4.397
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 6.411
Fall : 6.112
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.572
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.408
Fall : 4.401
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.413
Fall : 4.397
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.788
Fall : 3.713
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.811
Fall : 3.715
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.788
Fall : 3.713
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.397
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.397
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.461
Fall : 2.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 4.158
Fall : 4.085
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.442
Fall : 4.429
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.462
Fall : 4.423
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 4.205
Fall : 4.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 4.158
Fall : 4.085
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.457
Fall : 2.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.456
Fall : 2.369
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.479
Fall : 4.115
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.458
Fall : 2.371
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.551
Fall : 2.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.629
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.045
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.893
RF :
FR :
FF : 7.253
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 7.004
RF :
FR :
FF : 7.359
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.487
RF :
FR :
FF : 4.751
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.491
RF :
FR :
FF : 4.560
Input Port : SW[2]
Output Port : LED[2]
RR : 3.931
RF :
FR :
FF : 4.082
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.662
RF :
FR :
FF : 7.012
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.765
RF :
FR :
FF : 7.110
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.348
RF :
FR :
FF : 4.609
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.921
Fall : 5.799
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.438
Fall : 6.316
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.438
Fall : 6.316
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 6.070
Fall : 5.937
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.069
Fall : 5.949
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.921
Fall : 5.799
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.085
Fall : 5.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.085
Fall : 5.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.061
Fall : 5.928
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.617
Fall : 4.495
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.113
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.113
Fall : 4.991
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.732
Fall : 4.599
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.754
Fall : 4.634
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.617
Fall : 4.495
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.775
Fall : 4.653
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.775
Fall : 4.653
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.723
Fall : 4.590
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 5.820
1 to Hi-Z : 5.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 6.366
1 to Hi-Z : 6.488
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 6.366
1 to Hi-Z : 6.488
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.976
1 to Hi-Z : 6.109
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 6.042
1 to Hi-Z : 6.162
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.820
1 to Hi-Z : 5.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 5.919
1 to Hi-Z : 6.041
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 5.919
1 to Hi-Z : 6.041
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.948
1 to Hi-Z : 6.081
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.523
1 to Hi-Z : 4.645
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 5.047
1 to Hi-Z : 5.169
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 5.047
1 to Hi-Z : 5.169
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.644
1 to Hi-Z : 4.777
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.731
1 to Hi-Z : 4.851
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 4.523
1 to Hi-Z : 4.645
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.617
1 to Hi-Z : 4.739
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.617
1 to Hi-Z : 4.739
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.617
1 to Hi-Z : 4.750
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 50.7 MHz
Restricted Fmax : 50.7 MHz
Clock Name : CLOCK_50
Note :
Fmax : 132.1 MHz
Restricted Fmax : 132.1 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 170.88 MHz
Restricted Fmax : 170.88 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 180.38 MHz
Restricted Fmax : 180.38 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 1054.85 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -17.727
End Point TNS : -781.205
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.896
End Point TNS : -255.894
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.422
End Point TNS : -38.759
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.786
End Point TNS : -2.786
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.148
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.311
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.312
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.339
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -5.735
End Point TNS : -424.927
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.339
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.748
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.489
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.596
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.591
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.491
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -17.727
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.520
Slack : -17.668
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.479
Slack : -17.643
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.436
Slack : -17.634
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.192
Slack : -17.631
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 7.201
Slack : -17.617
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.428
Slack : -17.598
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.391
Slack : -17.595
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.153
Slack : -17.581
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 7.145
Slack : -17.546
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.338
Slack : -17.546
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.357
Slack : -17.544
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.337
Slack : -17.540
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.332
Slack : -17.535
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.346
Slack : -17.533
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.325
Slack : -17.529
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.322
Slack : -17.521
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.314
Slack : -17.521
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.313
Slack : -17.513
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.071
Slack : -17.502
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.278
Data Delay : 7.298
Slack : -17.481
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.274
Slack : -17.452
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.010
Slack : -17.448
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.259
Slack : -17.426
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.219
Slack : -17.414
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.972
Slack : -17.411
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 6.981
Slack : -17.406
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.198
Slack : -17.384
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.177
Slack : -17.380
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.939
Slack : -17.371
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.164
Slack : -17.363
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.156
Slack : -17.361
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.925
Slack : -17.361
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.925
Slack : -17.359
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.152
Slack : -17.343
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.136
Slack : -17.326
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.137
Slack : -17.298
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.091
Slack : -17.298
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.857
Slack : -17.289
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.848
Slack : -17.281
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 7.092
Slack : -17.279
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.843
Slack : -17.279
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.841
Slack : -17.275
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 7.068
Slack : -17.236
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 7.028
Slack : -17.232
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.790
Slack : -17.227
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.783
Slack : -17.181
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.731
Slack : -17.178
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.737
Slack : -17.170
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.981
Slack : -17.168
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.730
Slack : -17.162
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.721
Slack : -17.152
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.944
Slack : -17.134
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.684
Slack : -17.131
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.924
Slack : -17.128
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.678
Slack : -17.124
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.935
Slack : -17.107
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.900
Slack : -17.106
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.659
Slack : -17.104
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.662
Slack : -17.077
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.635
Slack : -17.075
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.868
Slack : -17.075
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.868
Slack : -17.073
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.633
Slack : -17.054
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.865
Slack : -17.045
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.856
Slack : -17.023
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.573
Slack : -17.022
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.580
Slack : -17.014
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.825
Slack : -16.999
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.810
Slack : -16.991
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.549
Slack : -16.989
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.550
Slack : -16.987
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.537
Slack : -16.979
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.790
Slack : -16.941
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.752
Slack : -16.938
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.749
Slack : -16.920
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.470
Slack : -16.903
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.714
Slack : -16.878
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.439
Slack : -16.876
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.435
Slack : -16.854
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.410
Slack : -16.847
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.405
Slack : -16.844
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.405
Slack : -16.832
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.383
Slack : -16.823
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.616
Slack : -16.817
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.628
Slack : -16.814
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.372
Slack : -16.809
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.367
Slack : -16.805
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.371
Slack : -16.794
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.344
Slack : -16.780
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.340
Slack : -16.748
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.559
Slack : -16.733
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.286
Slack : -16.722
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.533
Slack : -16.718
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.276
Slack : -16.715
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.265
Slack : -16.713
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.524
Slack : -16.712
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.523
Slack : -16.705
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.263
Slack : -16.688
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.499
Slack : -16.672
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.263
Data Delay : 6.483
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.896
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.023
Data Delay : 4.973
Slack : -6.891
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.017
Data Delay : 4.974
Slack : -6.815
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.939
Slack : -6.810
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.940
Slack : -6.744
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.825
Slack : -6.718
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.025
Data Delay : 4.793
Slack : -6.681
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.765
Slack : -6.673
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.765
Slack : -6.636
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.717
Slack : -6.634
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.999
Data Delay : 4.735
Slack : -6.589
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.687
Slack : -6.588
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.676
Slack : -6.564
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.011
Data Delay : 4.653
Slack : -6.561
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.025
Data Delay : 4.636
Slack : -6.556
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 4.685
Slack : -6.555
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 4.634
Slack : -6.518
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.599
Slack : -6.511
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.607
Slack : -6.503
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.588
Slack : -6.483
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.619
Slack : -6.444
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 4.581
Slack : -6.437
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.527
Slack : -6.417
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.504
Slack : -6.405
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.501
Slack : -6.399
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 4.533
Slack : -6.395
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 4.513
Slack : -6.389
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.024
Data Delay : 4.465
Slack : -6.385
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.472
Slack : -6.378
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.017
Data Delay : 4.461
Slack : -6.374
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.022
Data Delay : 4.452
Slack : -6.370
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.996
Data Delay : 4.474
Slack : -6.359
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.440
Slack : -6.351
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.438
Slack : -6.342
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.429
Slack : -6.325
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.019
Data Delay : 4.406
Slack : -6.323
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.449
Slack : -6.315
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.405
Slack : -6.313
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.968
Data Delay : 4.445
Slack : -6.307
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.968
Data Delay : 4.439
Slack : -6.301
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.011
Data Delay : 4.390
Slack : -6.289
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 4.422
Slack : -6.286
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.422
Slack : -6.282
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.368
Slack : -6.264
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.390
Slack : -6.256
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.020
Data Delay : 4.336
Slack : -6.254
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.352
Slack : -6.253
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.338
Slack : -6.252
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.344
Slack : -6.252
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.337
Slack : -6.240
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.368
Slack : -6.229
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.316
Slack : -6.226
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 4.337
Slack : -6.220
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.356
Slack : -6.213
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.337
Slack : -6.198
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.011
Data Delay : 4.287
Slack : -6.197
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.332
Slack : -6.192
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.755
Data Delay : 4.537
Slack : -6.188
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.307
Slack : -6.180
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.320
Slack : -6.174
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.265
Slack : -6.170
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.258
Slack : -6.163
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.298
Slack : -6.155
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.245
Slack : -6.154
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.006
Data Delay : 4.248
Slack : -6.154
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.981
Data Delay : 4.273
Slack : -6.134
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.262
Slack : -6.129
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.018
Data Delay : 4.211
Slack : -6.129
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.241
Slack : -6.128
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.223
Slack : -6.126
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.007
Data Delay : 4.219
Slack : -6.124
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.212
Slack : -6.114
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 4.251
Slack : -6.112
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.199
Slack : -6.099
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.961
Data Delay : 4.238
Slack : -6.098
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.979
Data Delay : 4.219
Slack : -6.094
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 4.228
Slack : -6.093
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 4.220
Slack : -6.076
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.175
Slack : -6.072
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.979
Data Delay : 4.193
Slack : -6.058
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.158
Slack : -6.049
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.955
Data Delay : 4.194
Slack : -6.038
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.154
Slack : -6.027
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.113
Slack : -6.012
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.958
Data Delay : 4.154
Slack : -6.002
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 4.129
Slack : -5.982
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.073
Slack : -5.975
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 4.093
Slack : -5.974
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.099
Slack : -5.966
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.090
Slack : -5.952
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.038
Slack : -5.951
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.087
Slack : -5.949
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 4.085
Slack : -5.945
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.014
Data Delay : 4.031
Slack : -5.938
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.033
Slack : -5.936
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.076
Slack : -5.925
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.051
Slack : -5.903
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.029
Slack : -5.892
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 3.991
Slack : -5.883
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.961
Data Delay : 4.022
Slack : -5.875
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 4.006
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.422
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 2.596
Slack : -4.259
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.551
Slack : -4.259
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.551
Slack : -3.838
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.446
Slack : -3.838
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.446
Slack : -3.838
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.446
Slack : -3.838
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.446
Slack : -3.838
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.446
Slack : -3.705
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 1.997
Slack : -2.924
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 1.538
Slack : 17.066
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.410
Slack : 17.078
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.398
Slack : 17.200
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.276
Slack : 17.223
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.258
Slack : 17.223
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.258
Slack : 17.235
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.246
Slack : 17.235
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.246
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.230
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.230
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.230
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.230
Slack : 17.246
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.230
Slack : 17.255
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.221
Slack : 17.255
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.221
Slack : 17.258
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.218
Slack : 17.258
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.218
Slack : 17.258
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.218
Slack : 17.258
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.218
Slack : 17.258
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.218
Slack : 17.267
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.209
Slack : 17.267
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.209
Slack : 17.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.187
Slack : 17.357
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.124
Slack : 17.357
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.124
Slack : 17.380
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.096
Slack : 17.380
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.096
Slack : 17.380
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.096
Slack : 17.380
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.096
Slack : 17.380
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.096
Slack : 17.389
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.087
Slack : 17.389
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.087
Slack : 17.446
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.035
Slack : 17.446
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 3.035
Slack : 17.469
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.007
Slack : 17.469
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.007
Slack : 17.469
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.007
Slack : 17.469
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.007
Slack : 17.469
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 3.007
Slack : 17.478
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.998
Slack : 17.478
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.998
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.046
Data Delay : 3.215
Slack : 17.597
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.046
Data Delay : 3.203
Slack : 17.613
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.864
Slack : 17.613
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.864
Slack : 17.625
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.852
Slack : 17.625
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.852
Slack : 17.658
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.818
Slack : 17.719
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.046
Data Delay : 3.081
Slack : 17.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.730
Slack : 17.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.730
Slack : 17.752
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.724
Slack : 17.808
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.046
Data Delay : 2.992
Slack : 17.815
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 2.666
Slack : 17.815
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 2.666
Slack : 17.836
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.641
Slack : 17.836
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.641
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.638
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.638
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.638
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.638
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.638
Slack : 17.847
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.629
Slack : 17.847
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.629
Slack : 17.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.582
Slack : 17.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.582
Slack : 17.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.582
Slack : 17.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.582
Slack : 17.906
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.570
Slack : 17.906
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.570
Slack : 17.906
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.570
Slack : 17.906
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.570
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 2.572
Slack : 17.909
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.365
Data Delay : 2.572
Slack : 17.932
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.544
Slack : 17.932
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.544
Slack : 17.932
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.544
Slack : 17.932
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.544
Slack : 17.932
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.544
Slack : 17.941
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.535
Slack : 17.941
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.535
Slack : 17.949
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.844
Slack : 17.949
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.844
Slack : 17.949
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.844
Slack : 17.949
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.844
Slack : 17.949
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.844
Slack : 17.961
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.832
Slack : 17.961
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.832
Slack : 17.961
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.832
Slack : 17.961
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.832
Slack : 17.961
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.832
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.786
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.254
Data Delay : 1.418
Slack : 70.541
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.874
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.148
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 5.708
Slack : 4.171
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 5.685
Slack : 4.243
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 5.613
Slack : 4.282
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.564
Slack : 4.293
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 5.563
Slack : 4.315
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.531
Slack : 4.332
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.047
Data Delay : 5.524
Slack : 4.335
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.511
Slack : 4.351
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.497
Slack : 4.384
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.464
Slack : 4.404
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.444
Slack : 4.444
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.402
Slack : 4.446
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.400
Slack : 4.446
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.400
Slack : 4.463
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.383
Slack : 4.513
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.335
Slack : 4.515
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.333
Slack : 4.515
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.333
Slack : 4.532
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.316
Slack : 4.541
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.305
Slack : 4.571
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.274
Slack : 4.595
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.251
Slack : 4.610
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.238
Slack : 4.617
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.232
Slack : 4.628
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.217
Slack : 4.650
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.199
Slack : 4.661
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.192
Slack : 4.662
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.186
Slack : 4.664
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.056
Data Delay : 5.183
Slack : 4.664
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.181
Slack : 4.670
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.179
Slack : 4.679
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.174
Slack : 4.684
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.169
Slack : 4.690
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.140
Slack : 4.691
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 5.155
Slack : 4.701
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.152
Slack : 4.712
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.141
Slack : 4.721
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.124
Slack : 4.723
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.107
Slack : 4.727
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 5.110
Slack : 4.728
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 5.130
Slack : 4.733
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.116
Slack : 4.743
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.087
Slack : 4.753
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.060
Data Delay : 5.092
Slack : 4.756
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 5.092
Slack : 4.772
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.081
Slack : 4.772
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.077
Slack : 4.780
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.069
Slack : 4.781
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.068
Slack : 4.783
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.070
Slack : 4.784
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 5.053
Slack : 4.798
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 5.051
Slack : 4.806
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.047
Slack : 4.820
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 5.017
Slack : 4.822
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 5.036
Slack : 4.825
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.030
Slack : 4.829
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.024
Slack : 4.848
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 5.007
Slack : 4.850
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.980
Slack : 4.852
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 5.001
Slack : 4.854
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.976
Slack : 4.854
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.976
Slack : 4.858
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.965
Slack : 4.861
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 4.992
Slack : 4.871
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.959
Slack : 4.871
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.952
Slack : 4.873
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.950
Slack : 4.876
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 4.973
Slack : 4.877
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 4.960
Slack : 4.888
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 4.962
Slack : 4.892
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 4.960
Slack : 4.892
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.051
Data Delay : 4.960
Slack : 4.909
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.068
Data Delay : 4.928
Slack : 4.913
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 4.936
Slack : 4.925
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.898
Slack : 4.933
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.890
Slack : 4.947
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 4.908
Slack : 4.949
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.881
Slack : 4.953
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 4.904
Slack : 4.961
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 4.886
Slack : 4.970
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 4.885
Slack : 4.991
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.839
Slack : 4.994
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.829
Slack : 4.999
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 4.851
Slack : 5.007
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 4.840
Slack : 5.007
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 4.842
Slack : 5.015
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.808
Slack : 5.016
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 4.839
Slack : 5.034
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.062
Data Delay : 4.809
Slack : 5.059
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 4.792
Slack : 5.066
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.063
Data Delay : 4.776
Slack : 5.066
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.757
Slack : 5.072
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 4.759
Slack : 5.083
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.057
Data Delay : 4.763
Slack : 5.085
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 4.745
Slack : 5.087
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 4.736
Slack : 5.106
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 4.748
Slack : 5.118
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 4.740
Slack : 5.126
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 4.819
Slack : 5.139
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.059
Data Delay : 4.797
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.517
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.730
Slack : 1.246
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.626
Data Delay : 1.089
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.299
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.323
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.536
Slack : 0.337
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.537
Slack : 0.338
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.338
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.338
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.540
Slack : 0.340
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.341
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.540
Slack : 0.344
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.543
Slack : 0.345
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.544
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.393
Data Delay : 0.951
Slack : 0.415
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.380
Data Delay : 0.939
Slack : 0.473
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.672
Slack : 0.487
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.700
Slack : 0.489
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.702
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.703
Slack : 0.491
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.690
Slack : 0.492
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.692
Slack : 0.494
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.694
Slack : 0.495
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.695
Slack : 0.496
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.696
Slack : 0.497
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.697
Slack : 0.497
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.696
Slack : 0.497
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.696
Slack : 0.497
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.697
Slack : 0.498
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.698
Slack : 0.501
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.714
Slack : 0.502
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.702
Slack : 0.505
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.705
Slack : 0.506
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.706
Slack : 0.511
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.711
Slack : 0.511
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.711
Slack : 0.516
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.716
Slack : 0.520
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.732
Slack : 0.521
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.721
Slack : 0.521
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.721
Slack : 0.528
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.740
Slack : 0.529
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.741
Slack : 0.532
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.744
Slack : 0.544
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.743
Slack : 0.546
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.758
Slack : 0.550
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.413
Data Delay : 1.107
Slack : 0.625
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.824
Slack : 0.627
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.412
Data Delay : 1.183
Slack : 0.627
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.826
Slack : 0.628
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.827
Slack : 0.632
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.831
Slack : 0.638
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.837
Slack : 0.642
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.841
Slack : 0.644
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.857
Slack : 0.648
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.861
Slack : 0.651
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.255
Data Delay : 0.540
Slack : 0.669
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.412
Data Delay : 1.225
Slack : 0.670
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.870
Slack : 0.671
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.870
Slack : 0.684
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.883
Slack : 0.690
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.890
Slack : 0.694
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.885
Slack : 0.697
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.896
Slack : 0.707
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.907
Slack : 0.724
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.924
Slack : 0.727
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.918
Slack : 0.730
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.929
Slack : 0.731
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.944
Slack : 0.735
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.948
Slack : 0.738
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.937
Slack : 0.738
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.951
Slack : 0.739
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.939
Slack : 0.740
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.953
Slack : 0.745
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.958
Slack : 0.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.960
Slack : 0.748
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.948
Slack : 0.748
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.948
Slack : 0.752
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.753
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.953
Slack : 0.755
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.954
Slack : 0.759
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.959
Slack : 0.760
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.960
Slack : 0.761
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.496
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.696
Slack : 0.498
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.698
Slack : 0.528
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.728
Slack : 0.640
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.840
Slack : 0.727
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.938
Slack : 0.741
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.941
Slack : 0.808
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.005
Slack : 0.808
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.715
Slack : 0.813
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.012
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.056
Slack : 0.875
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.075
Slack : 0.882
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.082
Slack : 0.922
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.119
Slack : 0.925
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.122
Slack : 0.925
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.122
Slack : 1.003
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.203
Slack : 1.008
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.915
Slack : 1.015
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.922
Slack : 1.018
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.925
Slack : 1.030
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.227
Slack : 1.035
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.232
Slack : 1.047
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.954
Slack : 1.052
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.249
Slack : 1.054
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 0.961
Slack : 1.096
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.293
Slack : 1.104
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.303
Slack : 1.115
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.313
Slack : 1.118
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.315
Slack : 1.119
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.316
Slack : 1.124
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 1.031
Slack : 1.124
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.321
Slack : 1.124
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.322
Slack : 1.126
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.323
Slack : 1.134
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.332
Slack : 1.140
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.337
Slack : 1.141
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.339
Slack : 1.151
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 1.058
Slack : 1.155
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.263
Data Delay : 1.036
Slack : 1.156
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.036
Slack : 1.157
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.037
Slack : 1.178
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.058
Slack : 1.180
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.263
Data Delay : 1.061
Slack : 1.182
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.380
Slack : 1.183
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.380
Slack : 1.183
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.380
Slack : 1.186
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.066
Slack : 1.202
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.400
Slack : 1.208
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.406
Slack : 1.221
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.419
Slack : 1.228
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.426
Slack : 1.230
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.428
Slack : 1.233
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.432
Slack : 1.233
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.432
Slack : 1.257
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.455
Slack : 1.267
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.466
Slack : 1.268
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.468
Slack : 1.278
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.476
Slack : 1.280
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.478
Slack : 1.298
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 1.205
Slack : 1.316
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.264
Data Delay : 1.196
Slack : 1.351
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.551
Slack : 1.353
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.553
Slack : 1.353
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.551
Slack : 1.353
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.551
Slack : 1.370
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.568
Slack : 1.373
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.571
Slack : 1.382
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.582
Slack : 1.385
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.585
Slack : 1.413
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.611
Slack : 1.413
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.610
Slack : 1.414
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.612
Slack : 1.421
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.620
Slack : 1.426
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.626
Slack : 1.437
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.237
Data Delay : 1.344
Slack : 1.446
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.645
Slack : 1.446
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.645
Slack : 1.446
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.645
Slack : 1.446
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.645
Slack : 1.446
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.645
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
Slack : 1.463
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|attr_prefetch[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.390
Data Delay : 1.997
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.312
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.313
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.511
Slack : 0.313
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.511
Slack : 0.313
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.511
Slack : 0.321
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.519
Slack : 0.337
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.536
Slack : 0.470
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.668
Slack : 0.500
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.500
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.698
Slack : 0.501
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.700
Slack : 0.502
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.502
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.502
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.700
Slack : 0.503
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.505
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.505
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.506
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.705
Slack : 0.512
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.710
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.514
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.712
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.518
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.717
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.716
Slack : 0.533
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.731
Slack : 0.535
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.733
Slack : 0.544
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.742
Slack : 0.547
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.745
Slack : 0.548
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.746
Slack : 0.744
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.746
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.945
Slack : 0.746
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.945
Slack : 0.748
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.946
Slack : 0.748
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.946
Slack : 0.748
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.749
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.947
Slack : 0.749
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.947
Slack : 0.750
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.948
Slack : 0.751
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.751
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.752
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.754
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.755
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.954
Slack : 0.757
From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.955
Slack : 0.757
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.955
Slack : 0.757
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.955
Slack : 0.758
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.758
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.759
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.761
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.959
Slack : 0.761
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.763
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.961
Slack : 0.763
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.961
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.769
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.967
Slack : 0.770
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.968
Slack : 0.770
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.968
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.776
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.974
Slack : 0.778
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.976
Slack : 0.808
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.006
Slack : 0.813
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.012
Slack : 0.818
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.016
Slack : 0.833
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.032
Slack : 0.835
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.034
Slack : 0.835
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.034
Slack : 0.837
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.035
Slack : 0.837
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.036
Slack : 0.840
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.039
Slack : 0.842
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.041
Slack : 0.842
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.041
Slack : 0.844
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.042
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.044
Slack : 0.847
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.046
Slack : 0.847
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.046
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.047
Slack : 0.850
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.048
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.049
Slack : 0.853
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.051
Slack : 0.854
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.053
Slack : 0.855
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.054
Slack : 0.857
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.055
Slack : 0.857
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.056
Slack : 0.858
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.056
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.057
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.057
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.061
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.061
Slack : 0.865
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.063
Slack : 0.866
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.064
Slack : 0.866
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.064
Slack : 0.867
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.065
Slack : 0.870
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.068
Slack : 0.870
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.068
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.339
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.616
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.314
Data Delay : 3.203
Slack : 0.649
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.317
Data Delay : 3.239
Slack : 0.837
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.313
Data Delay : 3.423
Slack : 0.859
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.315
Data Delay : 3.447
Slack : 1.264
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.318
Data Delay : 3.855
Slack : 1.268
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.070
Data Delay : 3.611
Slack : 1.292
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.807
Slack : 1.306
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.325
Data Delay : 3.904
Slack : 1.317
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.318
Data Delay : 3.908
Slack : 1.319
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.322
Data Delay : 3.914
Slack : 1.324
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.835
Slack : 1.328
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.062
Data Delay : 3.663
Slack : 1.331
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.855
Slack : 1.332
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.331
Data Delay : 3.936
Slack : 1.335
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.323
Data Delay : 3.931
Slack : 1.337
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.855
Slack : 1.339
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.850
Slack : 1.342
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.062
Data Delay : 3.677
Slack : 1.348
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.866
Slack : 1.349
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.864
Slack : 1.356
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.062
Data Delay : 3.691
Slack : 1.358
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.882
Slack : 1.358
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.869
Slack : 1.360
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.318
Data Delay : 3.951
Slack : 1.364
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.889
Slack : 1.365
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.890
Slack : 1.375
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.066
Data Delay : 3.714
Slack : 1.375
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.322
Data Delay : 3.970
Slack : 1.376
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.076
Data Delay : 3.725
Slack : 1.381
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.905
Slack : 1.383
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.894
Slack : 1.383
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.318
Data Delay : 3.974
Slack : 1.384
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.074
Data Delay : 3.731
Slack : 1.385
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.910
Slack : 1.385
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.310
Data Delay : 3.968
Slack : 1.386
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.902
Slack : 1.391
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.067
Data Delay : 3.731
Slack : 1.391
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.323
Data Delay : 3.987
Slack : 1.392
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.077
Data Delay : 3.742
Slack : 1.395
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.313
Data Delay : 3.981
Slack : 1.396
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.054
Data Delay : 3.723
Slack : 1.397
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.055
Data Delay : 3.725
Slack : 1.398
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.069
Data Delay : 3.740
Slack : 1.400
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.075
Data Delay : 3.748
Slack : 1.401
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.916
Slack : 1.402
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.325
Data Delay : 4.000
Slack : 1.405
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.922
Slack : 1.405
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.908
Slack : 1.408
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.933
Slack : 1.408
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.925
Slack : 1.411
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.926
Slack : 1.419
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.930
Slack : 1.421
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.315
Data Delay : 4.009
Slack : 1.423
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.933
Slack : 1.427
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.251
Data Delay : 3.951
Slack : 1.427
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.310
Data Delay : 4.010
Slack : 1.430
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.941
Slack : 1.432
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.939
Slack : 1.434
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.937
Slack : 1.436
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.331
Data Delay : 4.040
Slack : 1.438
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.953
Slack : 1.442
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.967
Slack : 1.442
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.960
Slack : 1.449
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.952
Slack : 1.449
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.955
Slack : 1.450
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.322
Data Delay : 4.045
Slack : 1.451
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.245
Data Delay : 3.969
Slack : 1.451
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.310
Data Delay : 4.034
Slack : 1.451
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.065
Data Delay : 3.789
Slack : 1.454
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.971
Slack : 1.456
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.962
Slack : 1.456
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.971
Slack : 1.458
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.971
Slack : 1.459
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.975
Slack : 1.461
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.972
Slack : 1.462
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.977
Slack : 1.466
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.982
Slack : 1.468
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.971
Slack : 1.469
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.977
Slack : 1.470
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.066
Data Delay : 3.809
Slack : 1.471
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.974
Slack : 1.474
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.985
Slack : 1.475
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.983
Slack : 1.477
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.992
Slack : 1.481
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.998
Slack : 1.481
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.234
Data Delay : 3.988
Slack : 1.481
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.989
Slack : 1.481
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.996
Slack : 1.484
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.992
Slack : 1.486
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 4.001
Slack : 1.486
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.067
Data Delay : 3.826
Slack : 1.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.084
Data Delay : 3.844
Slack : 1.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.065
Data Delay : 3.825
Slack : 1.487
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.990
Slack : 1.487
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 4.002
Slack : 1.488
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.998
Slack : 1.488
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.999
Slack : 1.488
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.233
Data Delay : 3.994
Slack : 1.488
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.063
Data Delay : 3.824
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -5.735
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.934
Slack : -5.735
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.932
Slack : -5.735
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.931
Slack : -5.734
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.930
Slack : -5.734
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.092
Data Delay : 3.929
Slack : -5.485
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 3.659
Slack : -5.485
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.116
Data Delay : 3.658
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.540
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.540
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.540
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.543
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.539
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.539
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.539
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.539
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.539
Slack : -5.248
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.540
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.539
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.083
Data Delay : 3.543
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.083
Data Delay : 3.543
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.538
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.247
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.542
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -5.242
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.076
Data Delay : 3.545
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.950
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.226
Data Delay : 3.539
Slack : -4.934
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.224
Data Delay : 3.537
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.539
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.539
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.539
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.539
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.539
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.545
Slack : -4.928
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.236
Data Delay : 3.543
Slack : -4.927
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.235
Data Delay : 3.541
Slack : -4.910
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.250
Data Delay : 3.539
Slack : -4.910
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.250
Data Delay : 3.539
Slack : -4.904
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.256
Data Delay : 3.539
Slack : -4.904
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.256
Data Delay : 3.539
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.339
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.628
Data Delay : 3.195
Slack : 3.339
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.628
Data Delay : 3.195
Slack : 3.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.194
Slack : 3.344
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.194
Slack : 3.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.607
Data Delay : 3.196
Slack : 3.362
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.608
Data Delay : 3.198
Slack : 3.365
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.199
Slack : 3.367
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.195
Slack : 3.367
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.195
Slack : 3.367
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.195
Slack : 3.367
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.195
Slack : 3.367
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.195
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.597
Data Delay : 3.194
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.596
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.378
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.193
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.283
Data Delay : 3.199
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.275
Data Delay : 3.198
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.193
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.695
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.197
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.196
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.196
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.196
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.196
Slack : 3.883
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.226
Data Delay : 3.282
Slack : 3.884
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.227
Data Delay : 3.284
Slack : 4.105
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.254
Data Delay : 3.529
Slack : 4.105
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.252
Data Delay : 3.527
Slack : 4.105
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.525
Slack : 4.105
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.251
Data Delay : 3.526
Slack : 4.105
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.525
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.750
Actual Width : 4.966
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.751
Actual Width : 4.967
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.843
Actual Width : 4.998
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.843
Actual Width : 4.998
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.844
Actual Width : 4.999
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.848
Actual Width : 5.032
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.848
Actual Width : 5.032
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.851
Actual Width : 5.001
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.851
Actual Width : 5.001
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.496
Actual Width : 9.726
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.596
Actual Width : 19.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.598
Actual Width : 19.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[9]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[9]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[2]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[6]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[10]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[11]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[12]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[2]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[6]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[8]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[9]
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[0]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[1]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[2]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[3]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[4]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[5]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[7]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.591
Actual Width : 20.807
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.592
Actual Width : 20.808
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.603
Actual Width : 20.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.695
Actual Width : 20.845
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.696
Actual Width : 20.846
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.697
Actual Width : 20.852
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.698
Actual Width : 20.882
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.700
Actual Width : 20.855
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.701
Actual Width : 20.885
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.701
Actual Width : 20.885
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.701
Actual Width : 20.885
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.701
Actual Width : 20.885
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.701
Actual Width : 20.885
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.514
Fall : 1.791
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.526
Fall : 3.809
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.868
Fall : 1.149
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.868
Fall : 1.149
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.088
Fall : 1.288
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.501
Fall : 2.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.142
Fall : -1.415
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.326
Fall : -2.595
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.319
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.319
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.536
Fall : -0.733
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.185
Fall : -1.411
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 9.704
Fall : 9.567
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 9.147
Fall : 9.032
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.316
Fall : 9.197
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 9.155
Fall : 9.002
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 9.152
Fall : 9.158
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 9.351
Fall : 9.246
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 9.507
Fall : 9.411
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 9.704
Fall : 9.567
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.309
Fall : 9.150
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.484
Fall : 9.425
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.018
Fall : 8.912
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.123
Fall : 9.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.044
Fall : 8.917
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.866
Fall : 8.821
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.269
Fall : 9.179
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.131
Fall : 9.026
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.484
Fall : 9.425
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.703
Fall : 8.604
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.063
Fall : 2.969
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.992
Fall : 2.917
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.974
Fall : 2.902
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.063
Fall : 2.969
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.972
Fall : 2.900
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.612
Fall : 5.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.021
Fall : 5.022
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.298
Fall : 5.247
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.067
Fall : 5.018
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.792
Fall : 4.786
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.108
Fall : 5.074
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.184
Fall : 5.190
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.057
Fall : 5.041
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.242
Fall : 5.220
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.612
Fall : 5.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.433
Fall : 5.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.415
Fall : 5.507
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.415
Fall : 5.507
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.584
Fall : 5.735
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.606
Fall : 5.727
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.606
Fall : 5.727
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.216
Fall : 5.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.057
Fall : 2.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.468
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.400
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.742
Fall : 7.609
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.921
Fall : 6.836
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.061
Fall : 6.953
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.363
Fall : 7.240
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.236
Fall : 7.218
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.691
Fall : 7.577
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.301
Fall : 7.220
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.742
Fall : 7.609
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.255
Fall : 7.167
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.609
Fall : 7.510
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.792
Fall : 6.716
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.868
Fall : 6.801
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.252
Fall : 7.155
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 6.950
Fall : 6.881
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.609
Fall : 7.510
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.928
Fall : 6.839
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.522
Fall : 7.467
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.553
Fall : 6.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 7.801
Fall : 7.387
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 7.801
Fall : 7.387
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.721
Fall : 6.643
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.058
Fall : 5.994
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.058
Fall : 5.988
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.378
Fall : 6.216
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 5.722
Fall : 5.601
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.100
Fall : 6.052
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.378
Fall : 6.216
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.378
Fall : 6.216
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.597
Fall : 2.522
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.652
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.325
Fall : 6.242
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.652
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.096
Fall : 5.995
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.056
Fall : 5.943
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.595
Fall : 2.520
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.361
Fall : 3.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.594
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.647
Fall : 2.553
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.648
Fall : 2.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.096
Fall : 6.975
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.264
Fall : 7.182
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.371
Fall : 7.296
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.096
Fall : 6.975
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.441
Fall : 7.404
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.615
Fall : 7.537
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.847
Fall : 7.749
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.468
Fall : 7.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.876
Fall : 7.722
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.991
Fall : 6.894
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.141
Fall : 7.067
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.186
Fall : 7.151
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.991
Fall : 6.894
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.168
Fall : 7.083
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.533
Fall : 7.468
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.485
Fall : 7.379
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.255
Fall : 7.231
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.296
Fall : 7.199
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.621
Fall : 2.545
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.602
Fall : 2.530
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.690
Fall : 2.596
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.046
Fall : 4.162
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.494
Fall : 4.492
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.759
Fall : 4.708
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.536
Fall : 4.486
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.273
Fall : 4.266
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.576
Fall : 4.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.651
Fall : 4.654
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.474
Fall : 4.453
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.705
Fall : 4.681
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 4.425
Fall : 4.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 4.254
Fall : 4.343
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.236
Fall : 4.323
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.236
Fall : 4.323
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 4.398
Fall : 4.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.419
Fall : 4.534
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.419
Fall : 4.534
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.046
Fall : 4.162
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.685
Fall : 2.591
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.091
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.022
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.643
Fall : 5.545
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.051
Fall : 5.942
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.097
Fall : 5.993
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 6.444
Fall : 6.297
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.074
Fall : 6.074
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.795
Fall : 5.719
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.263
Fall : 6.207
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.643
Fall : 5.545
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.436
Fall : 6.340
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.430
Fall : 5.409
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.928
Fall : 5.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.912
Fall : 5.848
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.339
Fall : 6.216
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.801
Fall : 5.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.713
Fall : 5.650
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.904
Fall : 5.840
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.430
Fall : 5.409
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.794
Fall : 5.736
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 4.034
Fall : 3.964
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.778
Fall : 5.365
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 4.250
Fall : 4.133
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.034
Fall : 3.970
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.034
Fall : 3.964
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.467
Fall : 3.356
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.489
Fall : 3.376
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.467
Fall : 3.356
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.119
Fall : 3.966
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.119
Fall : 3.966
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.241
Fall : 2.165
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.812
Fall : 3.704
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.071
Fall : 3.991
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.084
Fall : 4.001
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.851
Fall : 3.754
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.812
Fall : 3.704
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.237
Fall : 2.161
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.236
Fall : 2.160
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.005
Fall : 3.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.238
Fall : 2.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.290
Fall : 2.196
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.291
Fall : 2.197
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.172
RF :
FR :
FF : 4.298
Input Port : SW[2]
Output Port : LED[2]
RR : 3.641
RF :
FR :
FF : 3.830
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.274
RF :
FR :
FF : 6.463
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.413
RF :
FR :
FF : 6.634
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.080
RF :
FR :
FF : 4.294
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.037
RF :
FR :
FF : 4.165
Input Port : SW[2]
Output Port : LED[2]
RR : 3.527
RF :
FR :
FF : 3.716
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.051
RF :
FR :
FF : 6.240
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.182
RF :
FR :
FF : 6.405
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.944
RF :
FR :
FF : 4.156
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.323
Fall : 5.181
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.805
Fall : 5.663
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.805
Fall : 5.663
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.488
Fall : 5.363
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.500
Fall : 5.389
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.323
Fall : 5.181
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.512
Fall : 5.370
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.512
Fall : 5.370
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.495
Fall : 5.370
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.160
Fall : 4.018
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.623
Fall : 4.481
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.623
Fall : 4.481
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.286
Fall : 4.161
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.326
Fall : 4.215
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.160
Fall : 4.018
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.341
Fall : 4.199
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.341
Fall : 4.199
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.293
Fall : 4.168
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 5.156
1 to Hi-Z : 5.298
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 5.644
1 to Hi-Z : 5.786
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 5.644
1 to Hi-Z : 5.786
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.349
1 to Hi-Z : 5.474
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 5.397
1 to Hi-Z : 5.508
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.156
1 to Hi-Z : 5.298
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 5.257
1 to Hi-Z : 5.399
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 5.257
1 to Hi-Z : 5.399
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.335
1 to Hi-Z : 5.460
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 3.999
1 to Hi-Z : 4.141
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 4.467
1 to Hi-Z : 4.609
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 4.467
1 to Hi-Z : 4.609
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.153
1 to Hi-Z : 4.278
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.229
1 to Hi-Z : 4.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 3.999
1 to Hi-Z : 4.141
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.096
1 to Hi-Z : 4.238
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.096
1 to Hi-Z : 4.238
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.139
1 to Hi-Z : 4.264
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -15.243
End Point TNS : -641.328
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -4.921
End Point TNS : -171.346
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -3.770
End Point TNS : -34.841
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.784
End Point TNS : -2.784
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 6.261
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.098
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.177
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.177
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.684
End Point TNS : -358.844
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 2.507
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.783
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.208
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.609
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.535
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -15.243
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.289
Slack : -15.162
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.208
Slack : -15.156
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.202
Slack : -15.144
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 5.194
Slack : -15.131
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.177
Slack : -15.128
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.174
Slack : -15.126
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.172
Slack : -15.110
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.156
Slack : -15.104
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.150
Slack : -15.097
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.143
Slack : -15.090
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.136
Slack : -15.069
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.115
Slack : -15.047
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.093
Slack : -15.044
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.090
Slack : -15.028
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.074
Slack : -15.022
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.068
Slack : -15.021
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.067
Slack : -15.008
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.054
Slack : -15.005
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.051
Slack : -14.970
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 5.016
Slack : -14.969
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 5.030
Slack : -14.959
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.859
Slack : -14.952
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.857
Slack : -14.952
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.848
Slack : -14.948
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.994
Slack : -14.919
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.980
Slack : -14.911
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.807
Slack : -14.908
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.954
Slack : -14.900
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.946
Slack : -14.886
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.932
Slack : -14.886
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.947
Slack : -14.874
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.770
Slack : -14.869
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.930
Slack : -14.866
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.912
Slack : -14.859
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.759
Slack : -14.853
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.899
Slack : -14.852
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.898
Slack : -14.852
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.757
Slack : -14.852
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.748
Slack : -14.846
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.907
Slack : -14.838
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.734
Slack : -14.800
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.700
Slack : -14.786
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.847
Slack : -14.774
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.670
Slack : -14.769
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.666
Slack : -14.749
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.644
Slack : -14.733
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.633
Slack : -14.729
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.625
Slack : -14.727
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.627
Slack : -14.700
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.593
Slack : -14.697
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.743
Slack : -14.696
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.593
Slack : -14.689
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.589
Slack : -14.685
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.581
Slack : -14.681
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.742
Slack : -14.644
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.705
Slack : -14.637
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.698
Slack : -14.636
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.531
Slack : -14.632
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.521
Slack : -14.625
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.521
Slack : -14.614
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.509
Slack : -14.611
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.672
Slack : -14.607
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.504
Slack : -14.582
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.473
Slack : -14.567
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.457
Slack : -14.544
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.605
Slack : -14.542
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.603
Slack : -14.541
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.436
Slack : -14.541
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.602
Slack : -14.538
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.429
Slack : -14.536
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.434
Slack : -14.535
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.581
Slack : -14.517
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.578
Slack : -14.504
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.399
Slack : -14.502
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.548
Slack : -14.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.389
Slack : -14.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.560
Slack : -14.492
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.390
Slack : -14.488
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.383
Slack : -14.472
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.361
Slack : -14.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.357
Slack : -14.455
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.516
Slack : -14.439
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.329
Slack : -14.438
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.334
Slack : -14.438
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.499
Slack : -14.415
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.310
Slack : -14.413
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.306
Slack : -14.401
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.299
Slack : -14.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.278
Slack : -14.387
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.284
Slack : -14.382
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.279
Slack : -14.380
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.283
Slack : -14.374
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.435
Slack : -14.357
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.418
Slack : -14.355
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.416
Slack : -14.350
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.240
Slack : -14.346
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.241
Slack : -14.330
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.013
Data Delay : 4.391
Slack : -14.328
From Node : ula:ula_|video:video_|attr[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.374
Slack : -14.325
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.228
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -4.921
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.058
Data Delay : 2.952
Slack : -4.920
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.062
Data Delay : 2.947
Slack : -4.682
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.053
Data Delay : 2.718
Slack : -4.553
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 3.261
Slack : -4.552
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.385
Data Delay : 3.256
Slack : -4.500
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 2.535
Slack : -4.470
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 3.176
Slack : -4.454
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.387
Data Delay : 3.156
Slack : -4.454
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 3.198
Slack : -4.453
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 3.158
Slack : -4.453
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 3.193
Slack : -4.451
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 3.156
Slack : -4.427
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 3.149
Slack : -4.427
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 3.142
Slack : -4.408
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 3.129
Slack : -4.386
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.385
Data Delay : 3.090
Slack : -4.363
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 3.073
Slack : -4.346
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.388
Data Delay : 3.047
Slack : -4.343
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 3.063
Slack : -4.320
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 3.029
Slack : -4.320
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.385
Data Delay : 3.024
Slack : -4.314
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 3.027
Slack : -4.312
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.346
Data Delay : 3.055
Slack : -4.292
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 3.006
Slack : -4.280
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 3.030
Slack : -4.269
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.978
Slack : -4.265
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.997
Slack : -4.261
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 3.010
Slack : -4.249
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 2.957
Slack : -4.233
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.387
Data Delay : 2.935
Slack : -4.226
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.364
Data Delay : 2.951
Slack : -4.221
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.926
Slack : -4.215
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.964
Slack : -4.205
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.922
Slack : -4.200
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 2.908
Slack : -4.199
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.910
Slack : -4.196
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.944
Slack : -4.178
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.892
Slack : -4.177
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.892
Slack : -4.173
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.382
Data Delay : 2.880
Slack : -4.172
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.882
Slack : -4.168
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.906
Slack : -4.164
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.876
Slack : -4.163
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.908
Slack : -4.162
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.874
Slack : -4.159
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.875
Slack : -4.158
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.884
Slack : -4.158
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.892
Slack : -4.155
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.897
Slack : -4.146
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.892
Slack : -4.143
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.857
Slack : -4.136
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.880
Slack : -4.134
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.855
Slack : -4.133
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.839
Slack : -4.132
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.841
Slack : -4.132
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.844
Slack : -4.132
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.848
Slack : -4.129
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 2.837
Slack : -4.115
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.862
Slack : -4.115
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.361
Data Delay : 2.843
Slack : -4.095
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.835
Slack : -4.079
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.336
Data Delay : 2.832
Slack : -4.065
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.805
Slack : -4.061
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.793
Slack : -4.058
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.807
Slack : -4.058
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.770
Slack : -4.057
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.773
Slack : -4.052
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.769
Slack : -4.051
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 2.764
Slack : -4.046
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.802
Slack : -4.043
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.784
Slack : -4.042
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.779
Slack : -4.040
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.757
Slack : -4.039
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.755
Slack : -4.036
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.208
Data Delay : 2.917
Slack : -4.033
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.781
Slack : -4.031
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.779
Slack : -4.027
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.334
Data Delay : 2.782
Slack : -4.022
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.756
Slack : -4.021
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.735
Slack : -4.020
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.379
Data Delay : 2.730
Slack : -4.015
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.747
Slack : -4.002
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.750
Slack : -4.000
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.741
Slack : -3.996
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.717
Slack : -3.991
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.738
Slack : -3.990
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.741
Slack : -3.989
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.700
Slack : -3.979
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.700
Slack : -3.979
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.701
Slack : -3.970
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.703
Slack : -3.963
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.682
Slack : -3.962
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.335
Data Delay : 2.716
Slack : -3.956
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.705
Slack : -3.945
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.378
Data Delay : 2.656
Slack : -3.937
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.676
Slack : -3.929
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.670
Slack : -3.928
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.644
Slack : -3.924
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.656
Slack : -3.918
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.656
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -3.770
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 1.846
Slack : -3.712
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.857
Slack : -3.712
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.857
Slack : -3.473
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.805
Slack : -3.473
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.805
Slack : -3.473
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.805
Slack : -3.473
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.805
Slack : -3.473
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.805
Slack : -3.355
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.500
Slack : -2.927
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 1.269
Slack : 18.452
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 2.108
Slack : 18.460
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 2.100
Slack : 18.530
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 2.030
Slack : 18.563
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 2.002
Slack : 18.563
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 2.002
Slack : 18.563
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.997
Slack : 18.563
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.997
Slack : 18.565
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.995
Slack : 18.565
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.995
Slack : 18.565
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.995
Slack : 18.565
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.995
Slack : 18.565
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.995
Slack : 18.571
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.994
Slack : 18.571
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.994
Slack : 18.571
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.989
Slack : 18.571
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.989
Slack : 18.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.987
Slack : 18.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.987
Slack : 18.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.987
Slack : 18.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.987
Slack : 18.573
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.987
Slack : 18.588
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.972
Slack : 18.641
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.919
Slack : 18.641
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.919
Slack : 18.643
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.917
Slack : 18.643
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.917
Slack : 18.643
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.917
Slack : 18.643
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.917
Slack : 18.643
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.917
Slack : 18.651
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.914
Slack : 18.651
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.914
Slack : 18.699
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.861
Slack : 18.699
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.861
Slack : 18.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.859
Slack : 18.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.859
Slack : 18.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.859
Slack : 18.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.859
Slack : 18.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.859
Slack : 18.709
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.856
Slack : 18.709
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.856
Slack : 18.780
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.083
Data Delay : 1.975
Slack : 18.788
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.083
Data Delay : 1.967
Slack : 18.815
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.748
Slack : 18.815
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.748
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.740
Slack : 18.823
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.740
Slack : 18.839
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.721
Slack : 18.858
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.083
Data Delay : 1.897
Slack : 18.893
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.670
Slack : 18.893
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.670
Slack : 18.898
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.662
Slack : 18.916
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.083
Data Delay : 1.839
Slack : 18.936
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.629
Slack : 18.936
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.629
Slack : 18.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.610
Slack : 18.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.610
Slack : 18.951
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.612
Slack : 18.951
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.612
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.608
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.608
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.608
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.608
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.608
Slack : 18.970
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.590
Slack : 18.970
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.590
Slack : 18.970
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.590
Slack : 18.970
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.590
Slack : 18.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.582
Slack : 18.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.582
Slack : 18.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.582
Slack : 18.978
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.582
Slack : 18.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.577
Slack : 18.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.273
Data Delay : 1.577
Slack : 19.006
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.744
Slack : 19.006
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.744
Slack : 19.006
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.744
Slack : 19.006
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.744
Slack : 19.006
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.744
Slack : 19.009
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.551
Slack : 19.009
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.551
Slack : 19.011
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.549
Slack : 19.011
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.549
Slack : 19.011
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.549
Slack : 19.011
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.549
Slack : 19.011
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.549
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.736
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.736
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.736
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.736
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.736
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.784
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : -0.021
Data Delay : 1.133
Slack : 70.891
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.539
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 6.261
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.647
Slack : 6.273
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.635
Slack : 6.330
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.578
Slack : 6.342
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.566
Slack : 6.363
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.536
Slack : 6.366
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.031
Data Delay : 3.542
Slack : 6.378
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.521
Slack : 6.388
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.511
Slack : 6.390
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.510
Slack : 6.405
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.495
Slack : 6.415
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.485
Slack : 6.437
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.462
Slack : 6.438
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.461
Slack : 6.456
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.443
Slack : 6.464
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.435
Slack : 6.464
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.436
Slack : 6.465
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.435
Slack : 6.483
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.417
Slack : 6.491
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.409
Slack : 6.513
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.386
Slack : 6.524
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.375
Slack : 6.540
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.360
Slack : 6.551
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.349
Slack : 6.561
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.340
Slack : 6.566
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.334
Slack : 6.576
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.325
Slack : 6.578
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.321
Slack : 6.581
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.318
Slack : 6.586
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.315
Slack : 6.590
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.309
Slack : 6.593
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.308
Slack : 6.606
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.279
Slack : 6.608
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.298
Slack : 6.608
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.292
Slack : 6.614
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.036
Data Delay : 3.289
Slack : 6.615
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.029
Data Delay : 3.295
Slack : 6.620
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.286
Slack : 6.621
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.264
Slack : 6.631
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.254
Slack : 6.635
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.266
Slack : 6.636
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.265
Slack : 6.647
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.252
Slack : 6.654
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.247
Slack : 6.659
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.240
Slack : 6.662
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.239
Slack : 6.671
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.234
Slack : 6.677
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.229
Slack : 6.680
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.029
Data Delay : 3.230
Slack : 6.680
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.205
Slack : 6.681
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.204
Slack : 6.682
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.224
Slack : 6.683
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.216
Slack : 6.683
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.222
Slack : 6.688
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.039
Data Delay : 3.212
Slack : 6.689
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.217
Slack : 6.699
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.186
Slack : 6.707
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.178
Slack : 6.711
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.190
Slack : 6.713
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.193
Slack : 6.714
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.043
Data Delay : 3.183
Slack : 6.722
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.179
Slack : 6.732
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.147
Slack : 6.737
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.142
Slack : 6.738
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.037
Data Delay : 3.164
Slack : 6.738
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.037
Data Delay : 3.164
Slack : 6.739
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.160
Slack : 6.740
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.165
Slack : 6.741
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.138
Slack : 6.750
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 3.142
Slack : 6.752
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.153
Slack : 6.756
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.129
Slack : 6.762
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 3.130
Slack : 6.764
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.037
Data Delay : 3.138
Slack : 6.767
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.118
Slack : 6.768
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.138
Slack : 6.776
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.035
Data Delay : 3.128
Slack : 6.776
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.034
Data Delay : 3.129
Slack : 6.779
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.038
Data Delay : 3.122
Slack : 6.780
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.126
Slack : 6.799
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.037
Data Delay : 3.103
Slack : 6.804
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.075
Slack : 6.809
From Node : sdram_controller:sdram_|r.init_counter[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.077
Slack : 6.812
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.067
Slack : 6.814
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 3.078
Slack : 6.824
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.061
Slack : 6.825
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.045
Data Delay : 3.070
Slack : 6.829
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.050
Slack : 6.831
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 3.061
Slack : 6.837
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.069
Slack : 6.842
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.046
Data Delay : 3.052
Slack : 6.842
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.037
Slack : 6.849
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.048
Data Delay : 3.043
Slack : 6.849
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.057
Slack : 6.850
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.097
Slack : 6.852
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.047
Slack : 6.863
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.041
Data Delay : 3.036
Slack : 6.865
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.082
Slack : 6.867
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.019
Slack : 6.873
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.033
Data Delay : 3.033
Slack : 6.875
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.040
Data Delay : 3.072
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.098
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.563
Data Delay : 1.869
Slack : 0.136
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 1.910
Slack : 0.194
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.237
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.562
Data Delay : 2.007
Slack : 0.244
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.016
Slack : 0.537
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.572
Data Delay : 2.317
Slack : 0.538
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 2.312
Slack : 0.544
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.158
Slack : 0.545
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.569
Data Delay : 2.322
Slack : 0.551
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.577
Data Delay : 2.336
Slack : 0.556
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.328
Slack : 0.567
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.401
Data Delay : 2.176
Slack : 0.568
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.569
Data Delay : 2.345
Slack : 0.574
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.570
Data Delay : 2.352
Slack : 0.577
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.562
Data Delay : 2.347
Slack : 0.584
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.356
Slack : 0.591
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.561
Data Delay : 2.360
Slack : 0.593
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.400
Data Delay : 2.201
Slack : 0.596
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.368
Slack : 0.597
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.570
Data Delay : 2.375
Slack : 0.599
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.572
Data Delay : 2.379
Slack : 0.599
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.408
Data Delay : 2.215
Slack : 0.600
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 2.374
Slack : 0.600
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.402
Data Delay : 2.210
Slack : 0.605
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.558
Data Delay : 2.371
Slack : 0.609
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.398
Data Delay : 2.215
Slack : 0.610
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.224
Slack : 0.613
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.335
Slack : 0.616
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.395
Data Delay : 2.219
Slack : 0.627
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.352
Slack : 0.628
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.412
Data Delay : 2.248
Slack : 0.631
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.348
Slack : 0.632
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.349
Slack : 0.633
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.577
Data Delay : 2.418
Slack : 0.637
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.366
Slack : 0.639
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.369
Slack : 0.639
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.407
Data Delay : 2.254
Slack : 0.640
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.359
Slack : 0.642
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.571
Data Delay : 2.421
Slack : 0.642
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.569
Data Delay : 2.419
Slack : 0.645
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.558
Data Delay : 2.411
Slack : 0.646
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.579
Data Delay : 2.433
Slack : 0.647
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.368
Slack : 0.649
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.410
Data Delay : 2.267
Slack : 0.650
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.382
Slack : 0.655
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.378
Slack : 0.657
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.523
Data Delay : 2.388
Slack : 0.657
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.413
Data Delay : 2.278
Slack : 0.660
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.274
Slack : 0.661
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.275
Slack : 0.666
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.405
Data Delay : 2.279
Slack : 0.669
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.393
Slack : 0.669
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.385
Slack : 0.671
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.392
Slack : 0.678
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.411
Data Delay : 2.297
Slack : 0.679
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.390
Slack : 0.682
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.421
Data Delay : 2.311
Slack : 0.685
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.417
Slack : 0.685
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.426
Data Delay : 2.319
Slack : 0.686
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.404
Slack : 0.687
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.416
Slack : 0.687
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.518
Data Delay : 2.413
Slack : 0.687
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.561
Data Delay : 2.456
Slack : 0.688
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.523
Data Delay : 2.419
Slack : 0.688
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.409
Data Delay : 2.305
Slack : 0.688
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.420
Data Delay : 2.316
Slack : 0.689
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.403
Data Delay : 2.300
Slack : 0.690
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.579
Data Delay : 2.477
Slack : 0.691
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.421
Slack : 0.691
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.415
Slack : 0.693
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.404
Data Delay : 2.305
Slack : 0.694
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.518
Data Delay : 2.420
Slack : 0.694
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.507
Data Delay : 2.409
Slack : 0.694
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.410
Slack : 0.695
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.309
Slack : 0.696
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.573
Data Delay : 2.477
Slack : 0.697
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.502
Data Delay : 2.407
Slack : 0.698
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.422
Data Delay : 2.328
Slack : 0.700
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.406
Data Delay : 2.314
Slack : 0.701
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.403
Data Delay : 2.312
Slack : 0.703
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.422
Data Delay : 2.333
Slack : 0.705
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.426
Slack : 0.706
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.438
Slack : 0.708
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.433
Slack : 0.708
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.405
Data Delay : 2.321
Slack : 0.709
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.433
Slack : 0.710
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.433
Slack : 0.711
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.436
Slack : 0.711
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.429
Slack : 0.712
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.414
Data Delay : 2.334
Slack : 0.713
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.427
Slack : 0.714
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.444
Slack : 0.716
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.438
Slack : 0.717
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.413
Data Delay : 2.338
Slack : 0.718
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.442
Slack : 0.718
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.442
Slack : 0.719
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.448
Slack : 0.719
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.444
Slack : 0.719
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.428
Data Delay : 2.355
Slack : 0.721
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.437
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.177
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.436
Slack : 1.186
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.233
Data Delay : 0.576
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.177
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.177
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.178
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.183
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.314
Slack : 0.184
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.317
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.192
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.313
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.196
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.317
Slack : 0.197
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.317
Slack : 0.203
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.323
Slack : 0.203
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.323
Slack : 0.226
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.541
Slack : 0.243
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.240
Data Delay : 0.567
Slack : 0.261
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.381
Slack : 0.271
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.391
Slack : 0.278
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.399
Slack : 0.287
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.418
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.409
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.419
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.410
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.420
Slack : 0.293
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.414
Slack : 0.294
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.294
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.294
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.294
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.295
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.426
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.416
Slack : 0.296
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.416
Slack : 0.299
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.304
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.249
Data Delay : 0.639
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.428
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.428
Slack : 0.310
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.431
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.432
Slack : 0.315
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.443
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.447
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.448
Slack : 0.321
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.449
Slack : 0.325
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.446
Slack : 0.328
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.456
Slack : 0.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.500
Slack : 0.371
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.491
Slack : 0.372
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.502
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.494
Slack : 0.375
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.246
Data Delay : 0.705
Slack : 0.375
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.495
Slack : 0.375
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.495
Slack : 0.378
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.498
Slack : 0.380
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.500
Slack : 0.381
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.149
Data Delay : 0.316
Slack : 0.386
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.506
Slack : 0.388
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.508
Slack : 0.395
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.516
Slack : 0.396
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.246
Data Delay : 0.726
Slack : 0.401
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.521
Slack : 0.402
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.030
Data Delay : 0.516
Slack : 0.412
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.532
Slack : 0.424
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.030
Data Delay : 0.538
Slack : 0.426
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.547
Slack : 0.427
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.548
Slack : 0.435
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.555
Slack : 0.435
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.556
Slack : 0.436
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.556
Slack : 0.436
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.567
Slack : 0.437
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.568
Slack : 0.443
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.566
Slack : 0.444
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.567
Slack : 0.447
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.578
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.579
Slack : 0.450
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.581
Slack : 0.451
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.571
Slack : 0.451
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.582
Slack : 0.453
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.573
Slack : 0.455
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.575
Slack : 0.455
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.187
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.193
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.198
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.318
Slack : 0.276
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.397
Slack : 0.296
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.417
Slack : 0.296
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.417
Slack : 0.297
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.417
Slack : 0.298
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.418
Slack : 0.298
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.299
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.420
Slack : 0.301
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.301
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.421
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.428
Slack : 0.309
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.429
Slack : 0.317
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.438
Slack : 0.318
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.439
Slack : 0.324
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.445
Slack : 0.328
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.449
Slack : 0.328
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.449
Slack : 0.424
From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.545
Slack : 0.427
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.548
Slack : 0.440
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.561
Slack : 0.446
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.566
Slack : 0.447
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.567
Slack : 0.448
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.448
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
Slack : 0.453
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.574
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.456
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.576
Slack : 0.457
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.578
Slack : 0.458
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.579
Slack : 0.459
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.579
Slack : 0.459
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.579
Slack : 0.459
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.579
Slack : 0.460
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.580
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.581
Slack : 0.462
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.582
Slack : 0.463
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.584
Slack : 0.463
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.584
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.585
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.585
Slack : 0.465
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.586
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.588
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.588
Slack : 0.473
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.594
Slack : 0.483
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.state[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.604
Slack : 0.497
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.617
Slack : 0.509
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.629
Slack : 0.510
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.631
Slack : 0.510
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.630
Slack : 0.511
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.631
Slack : 0.511
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.631
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.632
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.634
Slack : 0.513
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.633
Slack : 0.514
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.634
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.637
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.639
Slack : 0.519
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.640
Slack : 0.521
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.642
Slack : 0.522
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.643
Slack : 0.522
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.642
Slack : 0.523
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.643
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.644
Slack : 0.525
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.645
Slack : 0.525
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.645
Slack : 0.527
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.647
Slack : 0.528
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.648
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.530
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.651
Slack : 0.530
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.651
Slack : 0.531
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.652
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.294
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.295
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.319
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.440
Slack : 0.368
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.489
Slack : 0.418
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.547
Slack : 0.443
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.564
Slack : 0.457
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.577
Slack : 0.465
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.585
Slack : 0.481
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.425
Slack : 0.494
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.614
Slack : 0.520
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.641
Slack : 0.523
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.644
Slack : 0.531
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.651
Slack : 0.535
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.655
Slack : 0.535
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.655
Slack : 0.567
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.688
Slack : 0.593
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.537
Slack : 0.594
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.538
Slack : 0.594
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.538
Slack : 0.603
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.723
Slack : 0.608
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.728
Slack : 0.613
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.732
Slack : 0.626
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vga_hc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.747
Slack : 0.634
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.578
Slack : 0.637
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.581
Slack : 0.637
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.757
Slack : 0.648
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.767
Slack : 0.656
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.775
Slack : 0.656
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.775
Slack : 0.656
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.776
Slack : 0.659
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.778
Slack : 0.662
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.781
Slack : 0.664
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.608
Slack : 0.669
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.613
Slack : 0.669
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.788
Slack : 0.674
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.604
Slack : 0.676
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.606
Slack : 0.679
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.609
Slack : 0.680
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.799
Slack : 0.683
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.802
Slack : 0.686
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.616
Slack : 0.686
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.616
Slack : 0.689
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.808
Slack : 0.689
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.808
Slack : 0.697
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.627
Slack : 0.701
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.820
Slack : 0.705
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.824
Slack : 0.711
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.830
Slack : 0.714
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.833
Slack : 0.717
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.838
Slack : 0.717
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.838
Slack : 0.746
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.865
Slack : 0.748
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.869
Slack : 0.749
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.869
Slack : 0.754
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.698
Slack : 0.760
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.879
Slack : 0.763
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.882
Slack : 0.765
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.695
Slack : 0.773
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.894
Slack : 0.776
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.897
Slack : 0.777
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.896
Slack : 0.797
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.916
Slack : 0.797
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.916
Slack : 0.801
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.922
Slack : 0.815
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.934
Slack : 0.825
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.945
Slack : 0.826
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.945
Slack : 0.827
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.948
Slack : 0.837
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.958
Slack : 0.837
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.958
Slack : 0.849
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.140
Data Delay : 0.793
Slack : 0.857
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.977
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.980
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.980
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.980
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.980
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.980
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.979
Slack : 0.860
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.979
Slack : 0.875
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.996
Slack : 0.881
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.002
Slack : 0.885
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.006
Slack : 0.886
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.007
Slack : 0.888
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_hc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.008
Slack : 0.888
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.008
Slack : 0.894
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vga_hc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 1.016
Slack : 0.899
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.020
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.782
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.780
Slack : -4.684
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.230
Data Delay : 2.777
Slack : -4.683
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.780
Slack : -4.683
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.778
Slack : -4.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 2.642
Slack : -4.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.251
Data Delay : 2.639
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.571
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.224
Data Delay : 2.568
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.224
Data Delay : 2.568
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.421
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.563
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.565
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.565
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.565
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.562
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.565
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.420
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.570
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.417
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.215
Data Delay : 2.573
Slack : -4.233
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.565
Slack : -4.233
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.565
Slack : -4.233
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.565
Slack : -4.233
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.565
Slack : -4.233
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.565
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.567
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.567
Slack : -4.232
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.567
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.035
Data Delay : 2.567
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.035
Data Delay : 2.567
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.035
Data Delay : 2.567
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.035
Data Delay : 2.567
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.566
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.034
Data Delay : 2.568
Slack : -4.231
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.573
Slack : -4.227
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.029
Data Delay : 2.569
Slack : -4.221
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.025
Data Delay : 2.567
Slack : -4.221
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.025
Data Delay : 2.567
Slack : -4.220
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.026
Data Delay : 2.565
Slack : -4.220
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.026
Data Delay : 2.565
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
Slack : -4.193
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.563
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.935
Slack : 2.541
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 1.937
Slack : 2.541
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.228
Data Delay : 1.937
Slack : 2.542
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.229
Data Delay : 1.939
Slack : 2.542
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.229
Data Delay : 1.939
Slack : 2.548
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.940
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.224
Data Delay : 1.943
Slack : 2.552
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.219
Data Delay : 1.939
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.553
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.938
Slack : 2.554
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.216
Data Delay : 1.938
Slack : 2.556
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.937
Slack : 2.556
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.937
Slack : 2.556
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.937
Slack : 2.556
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.937
Slack : 2.556
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.937
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.030
Data Delay : 1.943
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.942
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.021
Data Delay : 1.939
Slack : 2.750
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.021
Data Delay : 1.939
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.937
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.937
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.937
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.935
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.937
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.751
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.942
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.752
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.935
Slack : 2.884
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.016
Data Delay : 2.010
Slack : 2.886
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.019
Data Delay : 2.009
Slack : 2.997
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.009
Data Delay : 2.146
Slack : 2.997
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.144
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.145
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.005
Data Delay : 2.143
Slack : 2.998
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.004
Data Delay : 2.142
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.783
Actual Width : 4.999
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.787
Actual Width : 5.003
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.787
Actual Width : 5.003
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.787
Actual Width : 5.003
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.787
Actual Width : 5.003
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.788
Actual Width : 5.004
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.788
Actual Width : 5.004
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.810
Actual Width : 4.994
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.810
Actual Width : 4.994
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.810
Actual Width : 4.994
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.810
Actual Width : 4.994
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.810
Actual Width : 4.994
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.811
Actual Width : 4.995
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.812
Actual Width : 4.996
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.815
Actual Width : 4.970
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.815
Actual Width : 4.970
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.815
Actual Width : 4.970
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 19.612
Actual Width : 19.842
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.640
Actual Width : 20.824
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.640
Actual Width : 20.824
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.640
Actual Width : 20.824
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.645
Actual Width : 20.829
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.655
Actual Width : 20.871
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.658
Actual Width : 20.874
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.660
Actual Width : 20.876
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.664
Actual Width : 20.848
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.664
Actual Width : 20.848
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.664
Actual Width : 20.848
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.664
Actual Width : 20.848
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.664
Actual Width : 20.848
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 0.815
Fall : 1.610
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 2.160
Fall : 2.981
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.624
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.624
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 0.702
Fall : 1.291
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.571
Fall : 2.134
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.561
Fall : -1.355
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.405
Fall : -2.156
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.788
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.788
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.342
Fall : -0.923
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.737
Fall : -1.290
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.253
Fall : 6.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.922
Fall : 6.005
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.981
Fall : 6.082
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.884
Fall : 5.994
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.749
Fall : 6.050
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.022
Fall : 6.135
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.138
Fall : 6.337
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.253
Fall : 6.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.955
Fall : 6.115
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.140
Fall : 6.286
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.857
Fall : 5.936
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.902
Fall : 5.999
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.854
Fall : 5.950
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.617
Fall : 5.863
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.936
Fall : 6.062
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.889
Fall : 6.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.140
Fall : 6.286
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.639
Fall : 5.759
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.061
Fall : 1.989
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.001
Fall : 1.946
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.979
Fall : 1.928
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.052
Fall : 1.980
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.061
Fall : 1.989
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.977
Fall : 1.926
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.998
Fall : 1.943
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.059
Fall : 1.987
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.748
Fall : 3.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.219
Fall : 3.327
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.352
Fall : 3.462
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.199
Fall : 3.311
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.049
Fall : 3.160
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.251
Fall : 3.356
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.329
Fall : 3.459
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.243
Fall : 3.342
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.337
Fall : 3.469
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 3.748
Fall : 3.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 3.617
Fall : 3.572
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 3.607
Fall : 3.563
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 3.607
Fall : 3.563
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 3.738
Fall : 3.680
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 3.739
Fall : 3.675
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 3.739
Fall : 3.675
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 3.495
Fall : 3.473
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.059
Fall : 1.987
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.057
Fall : 1.985
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.958
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.905
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.941
Fall : 5.043
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.372
Fall : 4.489
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.445
Fall : 4.546
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.681
Fall : 4.807
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.459
Fall : 4.699
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.870
Fall : 4.993
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.675
Fall : 4.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.941
Fall : 5.043
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.571
Fall : 4.718
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.828
Fall : 4.943
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.307
Fall : 4.420
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.366
Fall : 4.463
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.651
Fall : 4.763
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.327
Fall : 4.512
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.784
Fall : 4.920
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.430
Fall : 4.536
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.828
Fall : 4.943
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.190
Fall : 4.281
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 5.317
Fall : 5.146
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.317
Fall : 5.146
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 4.196
Fall : 4.364
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.803
Fall : 3.875
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.804
Fall : 3.876
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.981
Fall : 4.019
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.588
Fall : 3.585
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.818
Fall : 3.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.981
Fall : 4.019
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.981
Fall : 4.019
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 4.161
Fall : 4.356
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.960
Fall : 4.022
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.161
Fall : 4.356
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.817
Fall : 3.844
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.782
Fall : 3.804
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.712
Fall : 1.657
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.709
Fall : 1.654
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.708
Fall : 1.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.245
Fall : 2.951
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.711
Fall : 1.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.755
Fall : 1.683
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.758
Fall : 1.686
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.607
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.624
Fall : 4.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.670
Fall : 4.779
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.607
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.700
Fall : 4.843
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.819
Fall : 4.940
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.988
Fall : 5.131
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.747
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.935
Fall : 5.065
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.461
Fall : 4.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.562
Fall : 4.652
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.593
Fall : 4.698
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.461
Fall : 4.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.577
Fall : 4.666
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.732
Fall : 4.867
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.749
Fall : 4.851
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.637
Fall : 4.728
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.808
Fall : 1.737
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.805
Fall : 1.734
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.705
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.876
Fall : 2.979
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 3.108
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.854
Fall : 2.959
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 2.709
Fall : 2.815
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.908
Fall : 3.006
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 2.981
Fall : 3.104
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.865
Fall : 2.958
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 2.986
Fall : 3.112
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 2.944
Fall : 2.881
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 2.819
Fall : 2.774
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.809
Fall : 2.765
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.809
Fall : 2.765
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 2.935
Fall : 2.878
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.936
Fall : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.936
Fall : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.705
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.805
Fall : 1.734
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.484
Fall : 3.630
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.729
Fall : 3.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.734
Fall : 3.824
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.908
Fall : 4.032
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.717
Fall : 3.979
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.745
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.905
Fall : 4.039
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.484
Fall : 3.630
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.918
Fall : 4.056
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.373
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.667
Fall : 3.756
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.657
Fall : 3.743
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.881
Fall : 3.993
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.594
Fall : 3.802
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.491
Fall : 3.672
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.669
Fall : 3.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.373
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.537
Fall : 2.596
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 4.052
Fall : 3.869
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.650
Fall : 2.713
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.537
Fall : 2.596
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.538
Fall : 2.597
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.171
Fall : 2.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.181
Fall : 2.190
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.171
Fall : 2.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.558
Fall : 2.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.558
Fall : 2.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.368
Fall : 2.401
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.539
Fall : 2.610
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.620
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.402
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.368
Fall : 2.401
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.819
RF :
FR :
FF : 3.181
Input Port : SW[2]
Output Port : LED[2]
RR : 2.438
RF :
FR :
FF : 2.867
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 3.977
RF :
FR :
FF : 4.754
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 4.061
RF :
FR :
FF : 4.868
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.656
RF :
FR :
FF : 3.282
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.733
RF :
FR :
FF : 3.101
Input Port : SW[2]
Output Port : LED[2]
RR : 2.367
RF :
FR :
FF : 2.799
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 3.843
RF :
FR :
FF : 4.611
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.920
RF :
FR :
FF : 4.717
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.572
RF :
FR :
FF : 3.193
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.466
Fall : 3.373
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.753
Fall : 3.660
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.753
Fall : 3.660
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.566
Fall : 3.492
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.562
Fall : 3.497
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.466
Fall : 3.373
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.529
Fall : 3.436
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.529
Fall : 3.436
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.532
Fall : 3.458
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.680
Fall : 2.587
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.956
Fall : 2.863
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 2.956
Fall : 2.863
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.767
Fall : 2.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 2.769
Fall : 2.704
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.680
Fall : 2.587
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 2.741
Fall : 2.648
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.741
Fall : 2.648
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 2.734
Fall : 2.660
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 3.461
1 to Hi-Z : 3.554
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 3.795
1 to Hi-Z : 3.888
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 3.795
1 to Hi-Z : 3.888
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 3.575
1 to Hi-Z : 3.649
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 3.611
1 to Hi-Z : 3.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 3.461
1 to Hi-Z : 3.554
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 3.506
1 to Hi-Z : 3.599
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 3.506
1 to Hi-Z : 3.599
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 3.554
1 to Hi-Z : 3.628
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 2.675
1 to Hi-Z : 2.768
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 2.996
1 to Hi-Z : 3.089
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 2.996
1 to Hi-Z : 3.089
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 2.775
1 to Hi-Z : 2.849
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 2.817
1 to Hi-Z : 2.882
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 2.675
1 to Hi-Z : 2.768
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 2.718
1 to Hi-Z : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 2.718
1 to Hi-Z : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 2.755
1 to Hi-Z : 2.829
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -18.571
Hold : 0.098
Recovery : -6.212
Removal : 2.507
Minimum Pulse Width : 4.748
Clock : CLOCK_50
Setup : -18.571
Hold : 0.098
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 9.208
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 3.503
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 4.748
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -7.747
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 19.596
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.915
Hold : 0.177
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 35.491
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -4.731
Hold : 0.177
Recovery : -6.212
Removal : 2.507
Minimum Pulse Width : 20.591
Clock : Design-wide TNS
Setup : -1152.857
Hold : 0.0
Recovery : -460.73
Removal : 0.0
Minimum Pulse Width : 0.0
Clock : CLOCK_50
Setup : -821.372
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 0.000
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -287.138
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.915
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -41.432
Hold : 0.000
Recovery : -460.730
Removal : 0.000
Minimum Pulse Width : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.548
Fall : 1.931
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.846
Fall : 4.271
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.221
Fall : 1.461
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.814
Fall : 3.095
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.561
Fall : -1.355
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.405
Fall : -2.156
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.342
Fall : -0.733
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.737
Fall : -1.290
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.801
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 10.164
Fall : 10.160
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 10.350
Fall : 10.351
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 10.114
Fall : 10.074
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 10.072
Fall : 10.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.376
Fall : 10.386
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 10.482
Fall : 10.574
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 10.801
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 10.294
Fall : 10.222
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.527
Fall : 10.543
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.022
Fall : 10.010
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 10.153
Fall : 10.157
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 10.039
Fall : 10.024
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.790
Fall : 9.910
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 10.258
Fall : 10.260
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 10.080
Fall : 10.129
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 10.527
Fall : 10.543
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.684
Fall : 9.676
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.430
Fall : 3.345
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.430
Fall : 3.345
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.426
Fall : 3.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.248
Fall : 6.300
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.552
Fall : 5.647
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.839
Fall : 5.898
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.545
Fall : 5.576
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.269
Fall : 5.330
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.626
Fall : 5.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.718
Fall : 5.830
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.584
Fall : 5.653
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.733
Fall : 5.777
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 6.248
Fall : 6.299
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 6.038
Fall : 6.073
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 6.021
Fall : 6.053
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 6.021
Fall : 6.053
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 6.215
Fall : 6.300
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 6.241
Fall : 6.286
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 6.241
Fall : 6.286
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.859
Fall : 5.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.426
Fall : 3.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.525
Fall : 8.506
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.614
Fall : 7.674
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.796
Fall : 7.806
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.092
Fall : 8.080
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.910
Fall : 8.021
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.495
Fall : 8.500
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.018
Fall : 8.084
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.525
Fall : 8.506
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.947
Fall : 7.936
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.377
Fall : 8.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.472
Fall : 7.524
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.599
Fall : 7.612
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.017
Fall : 8.030
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.628
Fall : 7.694
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.377
Fall : 8.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.619
Fall : 7.643
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.251
Fall : 8.260
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.224
Fall : 7.248
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.645
Fall : 8.352
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.645
Fall : 8.352
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 7.356
Fall : 7.355
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.643
Fall : 6.643
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.647
Fall : 6.639
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.282
Fall : 6.183
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.690
Fall : 6.712
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.988
Fall : 6.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 7.297
Fall : 7.345
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.937
Fall : 6.925
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 7.297
Fall : 7.345
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.690
Fall : 6.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.641
Fall : 6.567
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.607
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.624
Fall : 4.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.670
Fall : 4.779
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.488
Fall : 4.607
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.700
Fall : 4.843
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.819
Fall : 4.940
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.988
Fall : 5.131
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.747
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.935
Fall : 5.065
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.461
Fall : 4.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.562
Fall : 4.652
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.593
Fall : 4.698
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.461
Fall : 4.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.577
Fall : 4.666
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.732
Fall : 4.867
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.749
Fall : 4.851
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.637
Fall : 4.728
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.808
Fall : 1.737
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.805
Fall : 1.734
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.705
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.876
Fall : 2.979
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 3.108
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.854
Fall : 2.959
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 2.709
Fall : 2.815
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.908
Fall : 3.006
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 2.981
Fall : 3.104
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.865
Fall : 2.958
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 2.986
Fall : 3.112
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 2.944
Fall : 2.881
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 2.819
Fall : 2.774
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.809
Fall : 2.765
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.809
Fall : 2.765
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 2.935
Fall : 2.878
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.936
Fall : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.936
Fall : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.705
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.805
Fall : 1.734
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.484
Fall : 3.630
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.729
Fall : 3.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.734
Fall : 3.824
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.908
Fall : 4.032
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.717
Fall : 3.979
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.745
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.905
Fall : 4.039
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.484
Fall : 3.630
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.918
Fall : 4.056
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.373
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.667
Fall : 3.756
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.657
Fall : 3.743
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.881
Fall : 3.993
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.594
Fall : 3.802
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.491
Fall : 3.672
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.669
Fall : 3.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.373
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.537
Fall : 2.596
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 4.052
Fall : 3.869
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.650
Fall : 2.713
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.537
Fall : 2.596
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.538
Fall : 2.597
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.171
Fall : 2.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.181
Fall : 2.190
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.171
Fall : 2.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.558
Fall : 2.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.558
Fall : 2.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.368
Fall : 2.401
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.539
Fall : 2.610
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.620
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.402
Fall : 2.440
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.368
Fall : 2.401
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.629
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.045
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.893
RF :
FR :
FF : 7.253
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 7.004
RF :
FR :
FF : 7.359
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.487
RF :
FR :
FF : 4.751
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.733
RF :
FR :
FF : 3.101
Input Port : SW[2]
Output Port : LED[2]
RR : 2.367
RF :
FR :
FF : 2.799
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 3.843
RF :
FR :
FF : 4.611
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.920
RF :
FR :
FF : 4.717
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.572
RF :
FR :
FF : 3.193
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : SW[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : raw_loader_in
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_DAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_CLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : AUD_ADCDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 300
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1201
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1926
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 272
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1070
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1437
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 300
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1201
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1926
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 272
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1070
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1437
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Recovery Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Removal Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 2
Hold : 2
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 0
Hold : 0
Property : Unconstrained Output Port Paths
Setup : 0
Hold : 0
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sat Apr 2 14:51:13 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'spectrum.sdc'
Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port
Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection
Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]}
Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin
Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock
Warning (332125): Found combinational loop of 513 nodes
Warning (332126): Node "z80_|bus_control_|db[2]~13|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datad"
Warning (332126): Node "z80_|alu_control_|db[2]~29|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~30|datad"
Warning (332126): Node "z80_|alu_control_|db[2]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac"
Warning (332126): Node "z80_|bus_control_|db[2]~12|datac"
Warning (332126): Node "z80_|bus_control_|db[2]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~13|datac"
Warning (332126): Node "z80_|alu_|db[2]~11|datad"
Warning (332126): Node "z80_|alu_|db[2]~11|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|datac"
Warning (332126): Node "z80_|alu_|db[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~18|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~19|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~20|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datac"
Warning (332126): Node "z80_|alu_|db[1]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa"
Warning (332126): Node "z80_|alu_control_|db[1]~25|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa"
Warning (332126): Node "z80_|alu_control_|db[1]~26|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~27|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~27|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa"
Warning (332126): Node "z80_|bus_control_|db[1]~10|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa"
Warning (332126): Node "z80_|bus_control_|db[1]~11|combout"
Warning (332126): Node "z80_|sw1_|db_down[1]~2|dataa"
Warning (332126): Node "z80_|sw1_|db_down[1]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~27|datad"
Warning (332126): Node "z80_|alu_|db[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db[1]~15|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~19|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~27|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~27|combout"
Warning (332126): Node "z80_|alu_|db[0]~17|datac"
Warning (332126): Node "z80_|alu_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_|db[0]~18|datab"
Warning (332126): Node "z80_|alu_|db[0]~18|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datac"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~21|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~2|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~3|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~3|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~6|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~7|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|datad"
Warning (332126): Node "z80_|alu_|db[7]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~3|datab"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~8|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~8|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~13|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~2|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~16|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~16|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~19|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|dataa"
Warning (332126): Node "z80_|alu_|db[5]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~8|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|combout"
Warning (332126): Node "z80_|alu_|db[5]~23|dataa"
Warning (332126): Node "z80_|alu_|db[5]~23|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~17|datad"
Warning (332126): Node "z80_|alu_control_|db[5]~17|combout"
Warning (332126): Node "z80_|bus_control_|db[5]~15|dataa"
Warning (332126): Node "z80_|bus_control_|db[5]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~14|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~15|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~20|datad"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~11|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~7|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~7|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~8|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~8|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~26|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~26|combout"
Warning (332126): Node "z80_|alu_|db[3]~13|dataa"
Warning (332126): Node "z80_|alu_|db[3]~13|combout"
Warning (332126): Node "z80_|alu_|db[3]~14|datab"
Warning (332126): Node "z80_|alu_|db[3]~14|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~36|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datad"
Warning (332126): Node "z80_|alu_control_|db[3]~35|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~36|datad"
Warning (332126): Node "z80_|alu_|db[3]~14|datad"
Warning (332126): Node "z80_|bus_control_|db[3]~21|datac"
Warning (332126): Node "z80_|bus_control_|db[3]~21|combout"
Warning (332126): Node "z80_|sw1_|db_down[3]~3|datab"
Warning (332126): Node "z80_|sw1_|db_down[3]~3|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~14|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~13|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~13|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~14|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~14|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~25|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|datad"
Warning (332126): Node "z80_|alu_|db[4]~10|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~31|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~32|datac"
Warning (332126): Node "z80_|alu_control_|db[4]~32|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~33|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~33|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datac"
Warning (332126): Node "z80_|alu_|db[4]~8|datac"
Warning (332126): Node "z80_|alu_|db[4]~8|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|datac"
Warning (332126): Node "z80_|bus_control_|db[4]~19|datac"
Warning (332126): Node "z80_|bus_control_|db[4]~19|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~33|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~15|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~25|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~25|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~27|datac"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~16|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datac"
Warning (332126): Node "z80_|alu_|db[4]~8|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~4|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~4|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~22|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~5|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datac"
Warning (332126): Node "z80_|alu_|db[3]~13|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~9|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~10|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~14|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~13|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~16|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab"
Warning (332126): Node "z80_|alu_|db[5]~23|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~22|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datac"
Warning (332126): Node "z80_|alu_|db[6]~21|datac"
Warning (332126): Node "z80_|alu_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datad"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_control_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~23|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~8|datad"
Warning (332126): Node "z80_|bus_control_|db[6]~8|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa"
Warning (332126): Node "z80_|bus_control_|db[6]~9|combout"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|datac"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datad"
Warning (332126): Node "z80_|alu_|db[6]~21|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|datad"
Warning (332126): Node "z80_|alu_|db[7]~19|dataa"
Warning (332126): Node "z80_|alu_|db[7]~19|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa"
Warning (332126): Node "z80_|alu_control_|db[7]~18|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~19|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~19|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~20|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~20|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~37|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~37|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~5|datab"
Warning (332126): Node "z80_|bus_control_|db[7]~5|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa"
Warning (332126): Node "z80_|bus_control_|db[7]~7|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~20|datab"
Warning (332126): Node "z80_|alu_|db[7]~19|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~19|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|datad"
Warning (332126): Node "z80_|alu_control_|db[0]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa"
Warning (332126): Node "z80_|alu_control_|db[0]~14|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~17|datab"
Warning (332126): Node "z80_|bus_control_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~10|datad"
Warning (332126): Node "z80_|alu_control_|db[0]~10|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa"
Warning (332126): Node "z80_|alu_|db[0]~18|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~18|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout"
Warning (332126): Node "z80_|alu_|db[0]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~9|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout"
Warning (332126): Node "z80_|alu_|db[1]~15|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datac"
Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa"
Warning (332126): Node "z80_|alu_control_|db[2]~28|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout"
Warning (332126): Node "z80_|alu_|db[2]~11|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~4|datac"
Critical Warning (332081): Design contains combinational loop of 513 nodes. Estimating the delays through the loop.
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -18.571
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -18.571 -821.372 CLOCK_50
Info (332119): -7.747 -287.138 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.731 -41.432 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.915 -2.915 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 3.503 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is 0.342
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.359 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.373 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -6.212
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.212 -460.730 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.666
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.666 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.752
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.488 0.000 CLOCK_50
Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -17.727
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -17.727 -781.205 CLOCK_50
Info (332119): -6.896 -255.894 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.422 -38.759 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.786 -2.786 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 4.148 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is 0.298
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.339 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -5.735
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -5.735 -424.927 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.339
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.339 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.748
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.748 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.489 0.000 CLOCK_50
Info (332119): 19.596 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -15.243
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -15.243 -641.328 CLOCK_50
Info (332119): -4.921 -171.346 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -3.770 -34.841 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 6.261 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is 0.098
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.098 0.000 CLOCK_50
Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -4.684
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.684 -358.844 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 2.507
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 2.507 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.783
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.783 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.208 0.000 CLOCK_50
Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 534 warnings
Info: Peak virtual memory: 445 megabytes
Info: Processing ended: Sat Apr 2 14:51:17 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
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