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TimeQuest Timing Analyzer report for spectrum
Wed Mar 30 14:56:17 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1200mV 85C Model Setup Summary
8. Slow 1200mV 85C Model Hold Summary
9. Slow 1200mV 85C Model Recovery Summary
10. Slow 1200mV 85C Model Removal Summary
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
12. Slow 1200mV 85C Model Setup: 'CLOCK_50'
13. Slow 1200mV 85C Model Hold: 'CLOCK_50'
14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
15. Clock to Output Times
16. Minimum Clock to Output Times
17. Slow 1200mV 85C Model Metastability Report
18. Slow 1200mV 0C Model Fmax Summary
19. Slow 1200mV 0C Model Setup Summary
20. Slow 1200mV 0C Model Hold Summary
21. Slow 1200mV 0C Model Recovery Summary
22. Slow 1200mV 0C Model Removal Summary
23. Slow 1200mV 0C Model Minimum Pulse Width Summary
24. Slow 1200mV 0C Model Setup: 'CLOCK_50'
25. Slow 1200mV 0C Model Hold: 'CLOCK_50'
26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
27. Clock to Output Times
28. Minimum Clock to Output Times
29. Slow 1200mV 0C Model Metastability Report
30. Fast 1200mV 0C Model Setup Summary
31. Fast 1200mV 0C Model Hold Summary
32. Fast 1200mV 0C Model Recovery Summary
33. Fast 1200mV 0C Model Removal Summary
34. Fast 1200mV 0C Model Minimum Pulse Width Summary
35. Fast 1200mV 0C Model Setup: 'CLOCK_50'
36. Fast 1200mV 0C Model Hold: 'CLOCK_50'
37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
38. Clock to Output Times
39. Minimum Clock to Output Times
40. Fast 1200mV 0C Model Metastability Report
41. Multicorner Timing Analysis Summary
42. Clock to Output Times
43. Minimum Clock to Output Times
44. Board Trace Model Assignments
45. Input Transition Times
46. Signal Integrity Metrics (Slow 1200mv 0c Model)
47. Signal Integrity Metrics (Slow 1200mv 85c Model)
48. Signal Integrity Metrics (Fast 1200mv 0c Model)
49. Setup Transfers
50. Hold Transfers
51. Report TCCS
52. Report RSKM
53. Unconstrained Paths
54. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : CLOCK_50
Type : Base
Period : 1.000
Frequency : 1000.0 MHz
Rise : 0.000
Fall : 0.500
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 323.83 MHz
Restricted Fmax : 250.0 MHz
Clock Name : CLOCK_50
Note : limit due to minimum period restriction (max I/O toggle rate)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -2.088
End Point TNS : -422.664
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.337
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -3.000
End Point TNS : -532.995
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -2.088
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.238
Data Delay : 3.354
Slack : -2.086
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.243
Data Delay : 3.357
Slack : -2.081
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.262
Data Delay : 3.371
Slack : -2.079
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.267
Data Delay : 3.374
Slack : -2.079
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.236
Data Delay : 3.343
Slack : -2.077
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.241
Data Delay : 3.346
Slack : -2.073
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.246
Data Delay : 3.347
Slack : -2.071
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.251
Data Delay : 3.350
Slack : -2.039
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.237
Data Delay : 3.304
Slack : -2.037
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.242
Data Delay : 3.307
Slack : -1.961
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.237
Data Delay : 3.226
Slack : -1.959
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.242
Data Delay : 3.229
Slack : -1.951
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.237
Data Delay : 3.216
Slack : -1.949
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.242
Data Delay : 3.219
Slack : -1.924
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.120
Data Delay : 2.832
Slack : -1.917
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.118
Data Delay : 2.827
Slack : -1.908
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.118
Data Delay : 2.818
Slack : -1.907
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.117
Data Delay : 2.818
Slack : -1.881
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.244
Data Delay : 3.153
Slack : -1.880
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.243
Data Delay : 3.151
Slack : -1.879
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.249
Data Delay : 3.156
Slack : -1.878
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.248
Data Delay : 3.154
Slack : -1.877
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.249
Data Delay : 3.154
Slack : -1.876
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.248
Data Delay : 3.152
Slack : -1.875
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.254
Data Delay : 3.157
Slack : -1.874
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.253
Data Delay : 3.155
Slack : -1.871
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.247
Data Delay : 3.146
Slack : -1.861
From Node : counter[14]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.792
Slack : -1.861
From Node : counter[14]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.792
Slack : -1.861
From Node : counter[14]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.792
Slack : -1.856
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.233
Data Delay : 3.117
Slack : -1.855
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.248
Data Delay : 3.131
Slack : -1.854
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.238
Data Delay : 3.120
Slack : -1.854
From Node : counter[15]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.785
Slack : -1.854
From Node : counter[15]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.785
Slack : -1.854
From Node : counter[15]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 2.785
Slack : -1.844
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.262
Data Delay : 3.134
Slack : -1.842
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.267
Data Delay : 3.137
Slack : -1.833
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.238
Data Delay : 3.099
Slack : -1.831
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.235
Data Delay : 3.094
Slack : -1.831
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.243
Data Delay : 3.102
Slack : -1.829
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.240
Data Delay : 3.097
Slack : -1.827
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.261
Data Delay : 3.116
Slack : -1.826
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.230
Data Delay : 3.084
Slack : -1.825
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.266
Data Delay : 3.119
Slack : -1.824
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.235
Data Delay : 3.087
Slack : -1.816
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.123
Data Delay : 2.721
Slack : -1.815
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.122
Data Delay : 2.721
Slack : -1.804
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.232
Data Delay : 3.064
Slack : -1.802
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.237
Data Delay : 3.067
Slack : -1.799
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.262
Data Delay : 3.089
Slack : -1.797
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.267
Data Delay : 3.092
Slack : -1.795
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.246
Data Delay : 3.069
Slack : -1.795
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.120
Data Delay : 2.703
Slack : -1.794
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.232
Data Delay : 3.054
Slack : -1.794
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.260
Data Delay : 3.082
Slack : -1.793
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.125
Data Delay : 2.696
Slack : -1.792
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.237
Data Delay : 3.057
Slack : -1.792
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.265
Data Delay : 3.085
Slack : -1.791
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.246
Data Delay : 3.065
Slack : -1.790
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.123
Data Delay : 2.695
Slack : -1.789
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.227
Data Delay : 3.044
Slack : -1.789
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.122
Data Delay : 2.695
Slack : -1.789
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.251
Data Delay : 3.068
Slack : -1.789
From Node : counter[1]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.722
Slack : -1.789
From Node : counter[1]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.722
Slack : -1.789
From Node : counter[1]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.722
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.788
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 2.650
Slack : -1.787
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.232
Data Delay : 3.047
Slack : -1.786
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.245
Data Delay : 3.059
Slack : -1.784
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.250
Data Delay : 3.062
Slack : -1.783
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.128
Data Delay : 2.683
Slack : -1.783
From Node : counter[0]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.716
Slack : -1.783
From Node : counter[0]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.716
Slack : -1.783
From Node : counter[0]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 2.716
Slack : -1.780
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.123
Data Delay : 2.685
Slack : -1.779
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.125
Data Delay : 2.682
Slack : -1.779
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.122
Data Delay : 2.685
Slack : -1.778
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.233
Data Delay : 3.039
Slack : -1.777
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.120
Data Delay : 2.685
Slack : -1.776
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.238
Data Delay : 3.042
Slack : -1.774
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.117
Data Delay : 2.685
Slack : -1.774
From Node : A[10]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.118
Data Delay : 2.684
Slack : -1.773
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.116
Data Delay : 2.685
Slack : -1.772
From Node : A[2]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.119
Data Delay : 2.681
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.337
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.377
Data Delay : 0.901
Slack : 0.358
From Node : A[0]
To Node : A[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.361
From Node : counter[0]
To Node : counter[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.366
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.375
Data Delay : 0.928
Slack : 0.371
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.591
Slack : 0.391
From Node : counter[21]
To Node : counter[21]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.610
Slack : 0.392
From Node : A[0]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 0.977
Slack : 0.429
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.014
Slack : 0.478
From Node : A[4]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.063
Slack : 0.556
From Node : A[12]
To Node : A[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.789
Slack : 0.556
From Node : A[2]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.789
Slack : 0.556
From Node : counter[14]
To Node : counter[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.775
Slack : 0.556
From Node : counter[10]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.775
Slack : 0.556
From Node : counter[8]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.775
Slack : 0.557
From Node : counter[6]
To Node : counter[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.776
Slack : 0.558
From Node : A[10]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.791
Slack : 0.558
From Node : counter[16]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.777
Slack : 0.559
From Node : A[3]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.792
Slack : 0.559
From Node : counter[17]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.559
From Node : counter[4]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.778
Slack : 0.560
From Node : counter[2]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.779
Slack : 0.561
From Node : A[9]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.794
Slack : 0.561
From Node : counter[18]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : counter[15]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : counter[9]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : counter[7]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.561
From Node : counter[3]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.563
From Node : counter[19]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.782
Slack : 0.569
From Node : A[4]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.788
Slack : 0.571
From Node : counter[0]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.790
Slack : 0.572
From Node : counter[11]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.572
From Node : counter[1]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.573
From Node : counter[20]
To Node : counter[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.792
Slack : 0.574
From Node : counter[5]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.793
Slack : 0.575
From Node : A[6]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.808
Slack : 0.576
From Node : A[7]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.809
Slack : 0.577
From Node : A[8]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.810
Slack : 0.579
From Node : A[5]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.812
Slack : 0.580
From Node : A[11]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.813
Slack : 0.588
From Node : A[4]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.173
Slack : 0.589
From Node : A[14]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.808
Slack : 0.590
From Node : A[4]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.175
Slack : 0.593
From Node : A[13]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.812
Slack : 0.614
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.185
Slack : 0.616
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.379
Data Delay : 1.182
Slack : 0.624
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.383
Data Delay : 1.194
Slack : 0.633
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.377
Data Delay : 1.197
Slack : 0.636
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.383
Data Delay : 1.206
Slack : 0.638
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.381
Data Delay : 1.206
Slack : 0.639
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.381
Data Delay : 1.207
Slack : 0.640
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.379
Data Delay : 1.206
Slack : 0.640
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.377
Data Delay : 1.204
Slack : 0.649
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.379
Data Delay : 1.215
Slack : 0.649
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.381
Data Delay : 1.217
Slack : 0.649
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.383
Data Delay : 1.219
Slack : 0.658
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.381
Data Delay : 1.226
Slack : 0.664
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.375
Data Delay : 1.226
Slack : 0.670
From Node : A[0]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.255
Slack : 0.672
From Node : A[0]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.257
Slack : 0.687
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.899
Slack : 0.697
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.023
Data Delay : 0.907
Slack : 0.700
From Node : A[4]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.285
Slack : 0.702
From Node : A[4]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.287
Slack : 0.703
From Node : counter[13]
To Node : counter[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.922
Slack : 0.705
From Node : A[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.917
Slack : 0.708
From Node : A[8]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.920
Slack : 0.710
From Node : A[7]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.922
Slack : 0.712
From Node : counter[12]
To Node : counter[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.931
Slack : 0.721
From Node : A[9]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.933
Slack : 0.727
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : -0.290
Data Delay : 0.594
Slack : 0.736
From Node : A[10]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.948
Slack : 0.752
From Node : A[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.964
Slack : 0.752
From Node : A[1]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.985
Slack : 0.755
From Node : A[11]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 0.967
Slack : 0.784
From Node : A[0]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.369
Slack : 0.806
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.377
Slack : 0.809
From Node : A[5]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.025
Data Delay : 1.021
Slack : 0.812
From Node : A[4]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.397
Slack : 0.814
From Node : A[4]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.399
Slack : 0.829
From Node : counter[10]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.050
Slack : 0.830
From Node : A[2]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 1.063
Slack : 0.831
From Node : counter[14]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.050
Slack : 0.831
From Node : counter[8]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.050
Slack : 0.832
From Node : counter[6]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.051
Slack : 0.832
From Node : A[10]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 1.065
Slack : 0.833
From Node : counter[16]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.052
Slack : 0.833
From Node : counter[4]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.052
Slack : 0.834
From Node : counter[2]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
Slack : 0.835
From Node : counter[18]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.054
Slack : 0.846
From Node : counter[1]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.065
Slack : 0.847
From Node : counter[20]
To Node : counter[21]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.847
From Node : counter[17]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.066
Slack : 0.848
From Node : counter[9]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.848
From Node : counter[7]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.848
From Node : counter[15]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.848
From Node : counter[3]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.848
From Node : A[3]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 1.081
Slack : 0.848
From Node : A[9]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 1.081
Slack : 0.848
From Node : counter[9]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.069
Slack : 0.848
From Node : counter[1]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -3.000
Actual Width : 1.000
Required Width : 4.000
Type : Port Rate
Clock : CLOCK_50
Clock Edge : Rise
Target : CLOCK_50
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 10.136
Fall : 10.163
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 9.364
Fall : 9.344
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 9.457
Fall : 9.363
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 8.758
Fall : 8.675
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 9.190
Fall : 9.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 9.262
Fall : 9.197
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 9.193
Fall : 9.075
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 8.870
Fall : 8.811
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 9.462
Fall : 9.314
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 8.169
Fall : 8.165
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 7.769
Fall : 7.723
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 8.654
Fall : 8.577
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 7.536
Fall : 7.508
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 9.266
Fall : 9.145
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 7.532
Fall : 7.515
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 8.347
Fall : 8.356
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 9.800
Fall : 9.526
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 10.073
Fall : 10.080
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 10.136
Fall : 10.163
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 9.933
Fall : 9.935
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 9.469
Fall : 9.489
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 9.418
Fall : 9.420
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 9.271
Fall : 9.281
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 9.411
Fall : 9.307
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 9.604
Fall : 9.643
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 7.405
Fall : 7.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 7.174
Fall : 7.027
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 8.081
Fall : 8.029
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 7.404
Fall : 7.279
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 9.871
Fall : 9.494
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 7.266
Fall : 7.220
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 8.783
Fall : 8.703
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 7.984
Fall : 7.960
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 9.877
Fall : 9.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 9.020
Fall : 9.001
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 9.877
Fall : 9.812
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 9.257
Fall : 9.204
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 9.751
Fall : 9.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 9.463
Fall : 9.405
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 9.458
Fall : 9.165
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 8.163
Fall : 8.217
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 9.615
Fall : 9.395
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 6.360
Fall : 6.264
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 7.571
Fall : 7.524
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 7.674
Fall : 7.662
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 6.587
Fall : 6.485
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 7.472
Fall : 7.493
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 6.932
Fall : 6.845
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 7.271
Fall : 7.209
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 7.721
Fall : 7.687
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 7.056
Fall : 6.973
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 7.006
Fall : 7.030
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 7.319
Fall : 7.267
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 7.174
Fall : 7.096
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 7.071
Fall : 7.007
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 7.020
Fall : 6.970
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 6.552
Fall : 6.571
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 7.330
Fall : 7.264
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 9.122
Fall : 8.826
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 7.438
Fall : 7.443
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 8.053
Fall : 8.034
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 7.917
Fall : 7.950
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 7.827
Fall : 7.840
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 7.624
Fall : 7.581
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 8.099
Fall : 8.146
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 7.850
Fall : 7.807
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 7.358
Fall : 7.390
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 6.452
Fall : 6.387
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 6.360
Fall : 6.264
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 7.130
Fall : 7.063
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 6.876
Fall : 6.794
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 8.852
Fall : 8.482
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 6.830
Fall : 6.740
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 6.970
Fall : 6.880
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 7.284
Fall : 7.186
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 7.067
Fall : 6.992
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 7.241
Fall : 7.195
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 8.077
Fall : 8.094
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 7.067
Fall : 6.992
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 8.010
Fall : 8.144
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 7.213
Fall : 7.223
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 8.481
Fall : 8.223
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 7.151
Fall : 7.129
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 8.941
Fall : 8.699
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 355.49 MHz
Restricted Fmax : 250.0 MHz
Clock Name : CLOCK_50
Note : limit due to minimum period restriction (max I/O toggle rate)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -1.813
End Point TNS : -354.793
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.312
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -3.000
End Point TNS : -532.816
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -1.813
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 3.044
Slack : -1.813
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 3.040
Slack : -1.781
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.229
Data Delay : 3.030
Slack : -1.780
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.233
Data Delay : 3.033
Slack : -1.748
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.215
Data Delay : 2.983
Slack : -1.747
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.219
Data Delay : 2.986
Slack : -1.746
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.206
Data Delay : 2.972
Slack : -1.745
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.210
Data Delay : 2.975
Slack : -1.731
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 2.958
Slack : -1.730
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 2.961
Slack : -1.700
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 2.931
Slack : -1.700
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 2.927
Slack : -1.663
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 2.890
Slack : -1.662
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 2.893
Slack : -1.650
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.115
Data Delay : 2.555
Slack : -1.640
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.112
Data Delay : 2.548
Slack : -1.627
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.111
Data Delay : 2.536
Slack : -1.627
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.110
Data Delay : 2.537
Slack : -1.596
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.208
Data Delay : 2.824
Slack : -1.596
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.204
Data Delay : 2.820
Slack : -1.594
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 2.825
Slack : -1.594
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 2.821
Slack : -1.592
From Node : counter[14]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.530
Slack : -1.592
From Node : counter[14]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.530
Slack : -1.592
From Node : counter[14]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.530
Slack : -1.585
From Node : counter[15]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.523
Slack : -1.585
From Node : counter[15]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.523
Slack : -1.585
From Node : counter[15]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 2.523
Slack : -1.576
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.212
Data Delay : 2.808
Slack : -1.576
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.216
Data Delay : 2.812
Slack : -1.576
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.213
Data Delay : 2.809
Slack : -1.574
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.216
Data Delay : 2.810
Slack : -1.570
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.222
Data Delay : 2.812
Slack : -1.570
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.219
Data Delay : 2.809
Slack : -1.569
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.204
Data Delay : 2.793
Slack : -1.569
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.200
Data Delay : 2.789
Slack : -1.569
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.218
Data Delay : 2.807
Slack : -1.568
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.222
Data Delay : 2.810
Slack : -1.566
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.216
Data Delay : 2.802
Slack : -1.565
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.229
Data Delay : 2.814
Slack : -1.565
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.217
Data Delay : 2.802
Slack : -1.564
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.233
Data Delay : 2.817
Slack : -1.561
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.228
Data Delay : 2.809
Slack : -1.560
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.232
Data Delay : 2.812
Slack : -1.560
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.115
Data Delay : 2.465
Slack : -1.554
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.205
Data Delay : 2.779
Slack : -1.554
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.201
Data Delay : 2.775
Slack : -1.547
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.205
Data Delay : 2.772
Slack : -1.547
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.201
Data Delay : 2.768
Slack : -1.546
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.117
Data Delay : 2.449
Slack : -1.546
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.116
Data Delay : 2.450
Slack : -1.543
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.117
Data Delay : 2.446
Slack : -1.543
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.116
Data Delay : 2.447
Slack : -1.539
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.199
Data Delay : 2.758
Slack : -1.539
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.195
Data Delay : 2.754
Slack : -1.538
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.231
Data Delay : 2.789
Slack : -1.538
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.227
Data Delay : 2.785
Slack : -1.533
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.218
Data Delay : 2.771
Slack : -1.533
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.214
Data Delay : 2.767
Slack : -1.533
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.119
Data Delay : 2.434
Slack : -1.532
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.205
Data Delay : 2.757
Slack : -1.531
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.208
Data Delay : 2.759
Slack : -1.531
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.204
Data Delay : 2.755
Slack : -1.531
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.209
Data Delay : 2.760
Slack : -1.530
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.117
Data Delay : 2.433
Slack : -1.530
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.116
Data Delay : 2.434
Slack : -1.527
From Node : counter[1]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.467
Slack : -1.527
From Node : counter[1]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.467
Slack : -1.527
From Node : counter[1]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.467
Slack : -1.526
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.229
Data Delay : 2.775
Slack : -1.525
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.233
Data Delay : 2.778
Slack : -1.521
From Node : counter[0]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.461
Slack : -1.521
From Node : counter[0]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.461
Slack : -1.521
From Node : counter[0]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 2.461
Slack : -1.518
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.126
Data Delay : 2.412
Slack : -1.518
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.211
Data Delay : 2.749
Slack : -1.518
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.207
Data Delay : 2.745
Slack : -1.515
From Node : A[10]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.112
Data Delay : 2.423
Slack : -1.514
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.210
Data Delay : 2.744
Slack : -1.514
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.206
Data Delay : 2.740
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.068
Data Delay : 2.381
Slack : -1.511
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.111
Data Delay : 2.420
Slack : -1.511
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.110
Data Delay : 2.421
Slack : -1.510
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.122
Data Delay : 2.408
Slack : -1.509
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.113
Data Delay : 2.416
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.312
From Node : A[0]
To Node : A[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.320
From Node : counter[0]
To Node : counter[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.324
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.337
Data Delay : 0.830
Slack : 0.338
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.537
Slack : 0.348
From Node : counter[21]
To Node : counter[21]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.547
Slack : 0.352
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.333
Data Delay : 0.854
Slack : 0.365
From Node : A[0]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 0.893
Slack : 0.399
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 0.927
Slack : 0.426
From Node : A[4]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 0.954
Slack : 0.499
From Node : A[12]
To Node : A[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.711
Slack : 0.499
From Node : A[2]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.711
Slack : 0.499
From Node : counter[10]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.698
Slack : 0.500
From Node : counter[14]
To Node : counter[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.500
From Node : counter[8]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.500
From Node : counter[6]
To Node : counter[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.501
From Node : counter[16]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.700
Slack : 0.502
From Node : A[10]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.714
Slack : 0.502
From Node : A[3]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.714
Slack : 0.503
From Node : counter[17]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : counter[9]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : counter[7]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : counter[4]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.503
From Node : counter[2]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.504
From Node : A[9]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.716
Slack : 0.504
From Node : counter[18]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : counter[15]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.505
From Node : counter[19]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : counter[3]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.511
From Node : A[4]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.710
Slack : 0.514
From Node : counter[11]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.713
Slack : 0.514
From Node : counter[0]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.713
Slack : 0.515
From Node : A[4]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.043
Slack : 0.515
From Node : counter[20]
To Node : counter[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.714
Slack : 0.516
From Node : A[6]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.728
Slack : 0.516
From Node : counter[5]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.715
Slack : 0.516
From Node : counter[1]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.715
Slack : 0.517
From Node : A[7]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.729
Slack : 0.519
From Node : A[8]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.731
Slack : 0.520
From Node : A[5]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.732
Slack : 0.521
From Node : A[11]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.733
Slack : 0.522
From Node : A[4]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.050
Slack : 0.529
From Node : A[14]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.728
Slack : 0.534
From Node : A[13]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.733
Slack : 0.579
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.344
Data Delay : 1.092
Slack : 0.579
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.339
Data Delay : 1.087
Slack : 0.587
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.343
Data Delay : 1.099
Slack : 0.595
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.343
Data Delay : 1.107
Slack : 0.598
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.337
Data Delay : 1.104
Slack : 0.600
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.337
Data Delay : 1.106
Slack : 0.603
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.342
Data Delay : 1.114
Slack : 0.604
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.342
Data Delay : 1.115
Slack : 0.604
From Node : A[0]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.132
Slack : 0.606
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.339
Data Delay : 1.114
Slack : 0.608
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.339
Data Delay : 1.116
Slack : 0.608
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.342
Data Delay : 1.119
Slack : 0.611
From Node : A[0]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.139
Slack : 0.611
From Node : A[4]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.139
Slack : 0.612
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.343
Data Delay : 1.124
Slack : 0.614
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.342
Data Delay : 1.125
Slack : 0.618
From Node : A[4]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.146
Slack : 0.627
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.333
Data Delay : 1.129
Slack : 0.638
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.828
Slack : 0.645
From Node : counter[13]
To Node : counter[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.844
Slack : 0.649
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.017
Data Delay : 0.835
Slack : 0.650
From Node : counter[12]
To Node : counter[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.849
Slack : 0.656
From Node : A[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.846
Slack : 0.657
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.540
Slack : 0.660
From Node : A[7]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.850
Slack : 0.660
From Node : A[8]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.850
Slack : 0.675
From Node : A[9]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.865
Slack : 0.683
From Node : A[10]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.873
Slack : 0.684
From Node : A[1]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.896
Slack : 0.701
From Node : A[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.891
Slack : 0.701
From Node : A[11]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.891
Slack : 0.707
From Node : A[0]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.235
Slack : 0.707
From Node : A[4]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.235
Slack : 0.714
From Node : A[4]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.242
Slack : 0.741
From Node : counter[10]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 0.942
Slack : 0.744
From Node : counter[8]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.744
From Node : counter[6]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.744
From Node : counter[14]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.744
From Node : A[2]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.956
Slack : 0.745
From Node : counter[16]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.944
Slack : 0.747
From Node : A[10]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.959
Slack : 0.748
From Node : counter[2]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.748
From Node : counter[4]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.749
From Node : counter[18]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.948
Slack : 0.751
From Node : A[5]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.021
Data Delay : 0.941
Slack : 0.751
From Node : counter[1]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.752
From Node : counter[9]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.752
From Node : counter[7]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.752
From Node : counter[17]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.753
From Node : counter[15]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.753
From Node : A[9]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.965
Slack : 0.753
From Node : counter[0]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.754
From Node : counter[3]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.754
From Node : counter[19]
To Node : counter[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.757
From Node : counter[9]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 0.958
Slack : 0.758
From Node : A[3]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.970
Slack : 0.758
From Node : counter[1]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -3.000
Actual Width : 1.000
Required Width : 4.000
Type : Port Rate
Clock : CLOCK_50
Clock Edge : Rise
Target : CLOCK_50
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~PORTBDATAOUT0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_datain_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : -2.174
Actual Width : 1.000
Required Width : 3.174
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 9.137
Fall : 9.069
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 8.429
Fall : 8.365
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 8.542
Fall : 8.421
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 7.890
Fall : 7.771
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 8.302
Fall : 8.265
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 8.357
Fall : 8.233
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 8.299
Fall : 8.154
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 8.033
Fall : 7.897
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 8.543
Fall : 8.355
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 7.417
Fall : 7.301
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 7.041
Fall : 6.908
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 7.794
Fall : 7.668
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 6.828
Fall : 6.706
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 8.327
Fall : 8.170
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 6.829
Fall : 6.733
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 7.582
Fall : 7.472
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 8.811
Fall : 8.378
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 9.137
Fall : 9.009
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 9.135
Fall : 9.069
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 9.006
Fall : 8.944
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 8.525
Fall : 8.432
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 8.503
Fall : 8.432
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 8.406
Fall : 8.301
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 8.512
Fall : 8.360
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 8.655
Fall : 8.593
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 6.693
Fall : 6.594
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 6.481
Fall : 6.347
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 7.334
Fall : 7.229
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 6.690
Fall : 6.530
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 8.878
Fall : 8.400
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 6.560
Fall : 6.444
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 7.920
Fall : 7.797
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 7.220
Fall : 7.099
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 8.923
Fall : 8.865
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 8.116
Fall : 8.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 8.923
Fall : 8.813
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 8.364
Fall : 8.245
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 8.832
Fall : 8.865
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 8.480
Fall : 8.355
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 8.508
Fall : 8.062
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 7.411
Fall : 7.341
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 8.646
Fall : 8.260
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 5.719
Fall : 5.621
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 6.832
Fall : 6.743
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 6.935
Fall : 6.848
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 5.936
Fall : 5.782
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 6.753
Fall : 6.676
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 6.256
Fall : 6.096
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 6.560
Fall : 6.429
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 6.992
Fall : 6.854
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 6.370
Fall : 6.221
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 6.339
Fall : 6.296
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 6.622
Fall : 6.528
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 6.478
Fall : 6.327
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 6.408
Fall : 6.287
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 6.322
Fall : 6.213
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 5.924
Fall : 5.871
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 6.649
Fall : 6.505
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 8.181
Fall : 7.735
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 6.743
Fall : 6.618
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 7.307
Fall : 7.199
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 7.163
Fall : 7.142
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 7.087
Fall : 6.997
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 6.904
Fall : 6.791
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 7.347
Fall : 7.286
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 7.119
Fall : 6.970
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 6.640
Fall : 6.575
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 5.830
Fall : 5.723
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 5.719
Fall : 5.621
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 6.441
Fall : 6.356
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 6.186
Fall : 6.052
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 7.918
Fall : 7.455
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 6.144
Fall : 6.018
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 6.282
Fall : 6.137
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 6.586
Fall : 6.436
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 6.391
Fall : 6.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 6.532
Fall : 6.437
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 7.301
Fall : 7.224
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 6.391
Fall : 6.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 7.262
Fall : 7.252
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 6.470
Fall : 6.392
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 7.605
Fall : 7.202
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 6.484
Fall : 6.378
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 8.022
Fall : 7.620
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -0.824
End Point TNS : -117.237
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.169
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -3.000
End Point TNS : -347.907
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -0.824
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.145
Data Delay : 1.978
Slack : -0.822
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.148
Data Delay : 1.979
Slack : -0.811
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.129
Data Delay : 1.949
Slack : -0.809
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.134
Data Delay : 1.952
Slack : -0.809
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.132
Data Delay : 1.950
Slack : -0.807
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.137
Data Delay : 1.953
Slack : -0.807
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.753
Slack : -0.797
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.746
Slack : -0.795
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.744
Slack : -0.793
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.058
Data Delay : 1.744
Slack : -0.779
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.130
Data Delay : 1.918
Slack : -0.777
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.133
Data Delay : 1.919
Slack : -0.775
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.129
Data Delay : 1.913
Slack : -0.773
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.132
Data Delay : 1.914
Slack : -0.735
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.130
Data Delay : 1.874
Slack : -0.733
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.133
Data Delay : 1.875
Slack : -0.733
From Node : A[10]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.682
Slack : -0.733
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.679
Slack : -0.726
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.133
Data Delay : 1.868
Slack : -0.725
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.136
Data Delay : 1.870
Slack : -0.725
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.137
Data Delay : 1.871
Slack : -0.725
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.135
Data Delay : 1.869
Slack : -0.724
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.065
Data Delay : 1.668
Slack : -0.722
From Node : A[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.668
Slack : -0.719
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.065
Data Delay : 1.663
Slack : -0.718
From Node : A[10]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.664
Slack : -0.717
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.138
Data Delay : 1.864
Slack : -0.717
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.137
Data Delay : 1.863
Slack : -0.717
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.065
Data Delay : 1.661
Slack : -0.717
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.663
Slack : -0.716
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.140
Data Delay : 1.865
Slack : -0.715
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.141
Data Delay : 1.865
Slack : -0.715
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 1.657
Slack : -0.715
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.661
Slack : -0.714
From Node : A[13]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.142
Data Delay : 1.865
Slack : -0.711
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.138
Data Delay : 1.858
Slack : -0.707
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.073
Data Delay : 1.643
Slack : -0.705
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.061
Data Delay : 1.653
Slack : -0.702
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.074
Data Delay : 1.637
Slack : -0.702
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.641
Slack : -0.700
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.057
Data Delay : 1.652
Slack : -0.698
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 1.652
Slack : -0.698
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 1.640
Slack : -0.697
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.065
Data Delay : 1.641
Slack : -0.696
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.054
Data Delay : 1.651
Slack : -0.695
From Node : A[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.641
Slack : -0.695
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.061
Data Delay : 1.643
Slack : -0.694
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.052
Data Delay : 1.651
Slack : -0.694
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.064
Data Delay : 1.639
Slack : -0.693
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.077
Data Delay : 1.625
Slack : -0.693
From Node : A[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.059
Data Delay : 1.643
Slack : -0.692
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.062
Data Delay : 1.639
Slack : -0.692
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.638
Slack : -0.689
From Node : A[2]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.061
Data Delay : 1.637
Slack : -0.686
From Node : A[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.069
Data Delay : 1.626
Slack : -0.686
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.625
Slack : -0.685
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 1.627
Slack : -0.684
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.074
Data Delay : 1.619
Slack : -0.682
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.631
Slack : -0.682
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.621
Slack : -0.681
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.056
Data Delay : 1.634
Slack : -0.680
From Node : A[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.058
Data Delay : 1.631
Slack : -0.680
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.629
Slack : -0.680
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.063
Data Delay : 1.626
Slack : -0.679
From Node : A[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.054
Data Delay : 1.634
Slack : -0.678
From Node : A[11]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.072
Data Delay : 1.615
Slack : -0.677
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 1.619
Slack : -0.674
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.129
Data Delay : 1.812
Slack : -0.673
From Node : A[9]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.612
Slack : -0.672
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.132
Data Delay : 1.813
Slack : -0.672
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.072
Data Delay : 1.609
Slack : -0.672
From Node : A[8]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.621
Slack : -0.672
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.611
Slack : -0.670
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.069
Data Delay : 1.610
Slack : -0.669
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.074
Data Delay : 1.604
Slack : -0.668
From Node : A[13]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.135
Data Delay : 1.812
Slack : -0.667
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.145
Data Delay : 1.821
Slack : -0.665
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.148
Data Delay : 1.822
Slack : -0.665
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.145
Data Delay : 1.819
Slack : -0.663
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.148
Data Delay : 1.820
Slack : -0.662
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.144
Data Delay : 1.815
Slack : -0.661
From Node : A[9]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.071
Data Delay : 1.599
Slack : -0.660
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.147
Data Delay : 1.816
Slack : -0.660
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.055
Data Delay : 1.614
Slack : -0.658
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.053
Data Delay : 1.614
Slack : -0.658
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.061
Data Delay : 1.606
Slack : -0.654
From Node : A[12]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.061
Data Delay : 1.602
Slack : -0.653
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.073
Data Delay : 1.589
Slack : -0.652
From Node : A[9]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.591
Slack : -0.651
From Node : A[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.600
Slack : -0.650
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.134
Data Delay : 1.793
Slack : -0.649
From Node : A[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.058
Data Delay : 1.600
Slack : -0.648
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.060
Data Delay : 1.597
Slack : -0.648
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.071
Data Delay : 1.586
Slack : -0.648
From Node : A[13]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.137
Data Delay : 1.794
Slack : -0.646
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.128
Data Delay : 1.783
Slack : -0.646
From Node : A[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.058
Data Delay : 1.597
Slack : -0.645
From Node : A[3]
To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.070
Data Delay : 1.584
Slack : -0.644
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : 0.131
Data Delay : 1.784
Slack : -0.644
From Node : A[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 1.000
Clock Skew : -0.067
Data Delay : 1.586
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.169
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.219
Data Delay : 0.492
Slack : 0.185
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.216
Data Delay : 0.505
Slack : 0.186
From Node : A[0]
To Node : A[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.192
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.313
Slack : 0.193
From Node : counter[0]
To Node : counter[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.199
From Node : A[0]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.518
Slack : 0.204
From Node : counter[21]
To Node : counter[21]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.325
Slack : 0.208
From Node : A[14]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.526
Slack : 0.256
From Node : A[4]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.574
Slack : 0.295
From Node : counter[10]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.296
From Node : A[12]
To Node : A[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.425
Slack : 0.296
From Node : A[2]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.425
Slack : 0.296
From Node : counter[8]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.417
Slack : 0.297
From Node : counter[16]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.297
From Node : counter[14]
To Node : counter[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.297
From Node : counter[6]
To Node : counter[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.298
From Node : A[10]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.427
Slack : 0.298
From Node : A[9]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.427
Slack : 0.298
From Node : A[3]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.427
Slack : 0.298
From Node : counter[9]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : counter[4]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : counter[3]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : counter[2]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.299
From Node : counter[18]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : counter[17]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : counter[15]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : counter[7]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.300
From Node : counter[19]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.304
From Node : counter[1]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.305
From Node : A[4]
To Node : A[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.425
Slack : 0.305
From Node : counter[11]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.305
From Node : counter[0]
To Node : counter[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.306
From Node : counter[20]
To Node : counter[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.306
From Node : counter[5]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.308
From Node : A[6]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.437
Slack : 0.309
From Node : A[8]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.438
Slack : 0.309
From Node : A[7]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.438
Slack : 0.310
From Node : A[11]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.439
Slack : 0.310
From Node : A[5]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.439
Slack : 0.317
From Node : A[14]
To Node : A[14]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.437
Slack : 0.319
From Node : A[13]
To Node : A[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.439
Slack : 0.319
From Node : A[4]
To Node : A[6]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.637
Slack : 0.322
From Node : A[4]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.640
Slack : 0.327
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.219
Data Delay : 0.650
Slack : 0.332
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.225
Data Delay : 0.661
Slack : 0.332
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.657
Slack : 0.336
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.226
Data Delay : 0.666
Slack : 0.341
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.221
Data Delay : 0.666
Slack : 0.341
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.225
Data Delay : 0.670
Slack : 0.344
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.223
Data Delay : 0.671
Slack : 0.345
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.218
Data Delay : 0.667
Slack : 0.346
From Node : A[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.223
Data Delay : 0.673
Slack : 0.346
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.222
Data Delay : 0.672
Slack : 0.350
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.224
Data Delay : 0.678
Slack : 0.350
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.222
Data Delay : 0.676
Slack : 0.352
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.220
Data Delay : 0.676
Slack : 0.352
From Node : A[0]
To Node : A[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.671
Slack : 0.354
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.215
Data Delay : 0.673
Slack : 0.355
From Node : A[0]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.674
Slack : 0.359
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.492
Slack : 0.368
From Node : A[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.026
Data Delay : 0.498
Slack : 0.368
From Node : A[2]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.501
Slack : 0.371
From Node : counter[13]
To Node : counter[13]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.492
Slack : 0.372
From Node : A[8]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.505
Slack : 0.373
From Node : A[7]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.506
Slack : 0.373
From Node : counter[12]
To Node : counter[12]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.494
Slack : 0.376
From Node : A[9]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.509
Slack : 0.385
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : -0.153
Data Delay : 0.316
Slack : 0.385
From Node : A[4]
To Node : A[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.703
Slack : 0.387
From Node : A[10]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.520
Slack : 0.388
From Node : A[4]
To Node : A[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.706
Slack : 0.390
From Node : A[3]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.523
Slack : 0.394
From Node : A[1]
To Node : A[1]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.523
Slack : 0.398
From Node : A[11]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.531
Slack : 0.421
From Node : A[0]
To Node : A[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.740
Slack : 0.431
From Node : A[5]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.564
Slack : 0.433
From Node : A[4]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.222
Data Delay : 0.759
Slack : 0.442
From Node : counter[10]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.565
Slack : 0.445
From Node : counter[8]
To Node : counter[9]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.566
Slack : 0.445
From Node : A[2]
To Node : A[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.574
Slack : 0.446
From Node : counter[16]
To Node : counter[17]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : counter[14]
To Node : counter[15]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : counter[6]
To Node : counter[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.447
From Node : counter[2]
To Node : counter[3]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : counter[4]
To Node : counter[5]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : A[10]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.576
Slack : 0.448
From Node : counter[18]
To Node : counter[19]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.569
Slack : 0.451
From Node : A[4]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.769
Slack : 0.454
From Node : A[4]
To Node : A[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.234
Data Delay : 0.772
Slack : 0.455
From Node : counter[20]
To Node : counter[21]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.456
From Node : counter[9]
To Node : counter[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.456
From Node : counter[3]
To Node : counter[4]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.456
From Node : counter[1]
To Node : counter[2]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.456
From Node : A[9]
To Node : A[10]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.585
Slack : 0.457
From Node : counter[7]
To Node : counter[8]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.457
From Node : counter[15]
To Node : counter[16]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.457
From Node : counter[17]
To Node : counter[18]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.457
From Node : A[6]
To Node : A[7]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.586
Slack : 0.457
From Node : counter[9]
To Node : counter[11]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.580
Slack : 0.458
From Node : counter[19]
To Node : counter[20]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.579
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -3.000
Actual Width : 1.000
Required Width : 4.000
Type : Port Rate
Clock : CLOCK_50
Clock Edge : Rise
Target : CLOCK_50
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[0]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[10]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[11]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[12]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[13]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[14]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[1]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[2]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[3]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[4]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[5]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[6]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[7]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[8]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : A[9]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[0]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[10]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[11]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[12]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[13]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[14]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[15]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[16]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[17]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[18]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[19]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[1]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[20]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[21]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[2]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[3]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[4]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[5]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[6]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[7]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[8]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : counter[9]
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4
Slack : -1.000
Actual Width : 1.000
Required Width : 2.000
Type : Min Period
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4~PORTBDATAOUT0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 6.082
Fall : 6.081
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 5.573
Fall : 5.638
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 5.626
Fall : 5.669
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 5.194
Fall : 5.221
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 5.475
Fall : 5.590
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 5.464
Fall : 5.517
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 5.468
Fall : 5.485
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 5.212
Fall : 5.287
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 5.640
Fall : 5.626
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 4.757
Fall : 4.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 4.513
Fall : 4.647
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 5.130
Fall : 5.141
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 4.369
Fall : 4.467
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 5.513
Fall : 5.499
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 4.376
Fall : 4.495
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 4.860
Fall : 5.016
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 6.070
Fall : 5.956
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 6.081
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 5.937
Fall : 6.072
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 5.814
Fall : 5.988
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 5.581
Fall : 5.665
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 5.531
Fall : 5.631
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 5.463
Fall : 5.580
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 5.534
Fall : 5.586
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 5.710
Fall : 5.809
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 4.299
Fall : 4.392
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 4.239
Fall : 4.202
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 4.707
Fall : 4.867
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 4.365
Fall : 4.344
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 6.082
Fall : 5.937
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 4.227
Fall : 4.292
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 5.180
Fall : 5.215
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 4.627
Fall : 4.744
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 5.942
Fall : 6.003
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 5.367
Fall : 5.404
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 5.883
Fall : 5.967
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 5.479
Fall : 5.535
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 5.807
Fall : 6.003
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 5.652
Fall : 5.660
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 5.818
Fall : 5.728
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 4.735
Fall : 4.914
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 5.942
Fall : 5.866
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 3.706
Fall : 3.729
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 4.396
Fall : 4.507
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 4.455
Fall : 4.582
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 3.819
Fall : 3.860
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 4.372
Fall : 4.496
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 3.988
Fall : 4.055
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 4.203
Fall : 4.287
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 4.444
Fall : 4.573
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 4.090
Fall : 4.150
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 4.085
Fall : 4.185
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 4.238
Fall : 4.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 4.152
Fall : 4.224
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 4.092
Fall : 4.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 4.067
Fall : 4.130
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 3.816
Fall : 3.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 4.256
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 5.667
Fall : 5.519
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 4.353
Fall : 4.463
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 4.650
Fall : 4.762
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 4.587
Fall : 4.766
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 4.544
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 4.413
Fall : 4.491
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 4.703
Fall : 4.828
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 4.504
Fall : 4.604
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 4.319
Fall : 4.415
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 3.761
Fall : 3.760
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 3.706
Fall : 3.729
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 4.126
Fall : 4.166
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 3.985
Fall : 4.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 5.493
Fall : 5.301
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 3.962
Fall : 3.977
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 4.032
Fall : 4.088
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 4.207
Fall : 4.225
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 4.093
Fall : 4.161
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 4.198
Fall : 4.283
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 4.701
Fall : 4.868
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 4.093
Fall : 4.161
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 4.690
Fall : 4.893
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 4.204
Fall : 4.288
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 5.262
Fall : 5.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 4.137
Fall : 4.202
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 5.544
Fall : 5.435
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -2.088
Hold : 0.169
Recovery : N/A
Removal : N/A
Minimum Pulse Width : -3.000
Clock : CLOCK_50
Setup : -2.088
Hold : 0.169
Recovery : N/A
Removal : N/A
Minimum Pulse Width : -3.000
Clock : Design-wide TNS
Setup : -422.664
Hold : 0.0
Recovery : 0.0
Removal : 0.0
Minimum Pulse Width : -532.995
Clock : CLOCK_50
Setup : -422.664
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : -532.995
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 10.136
Fall : 10.163
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 9.364
Fall : 9.344
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 9.457
Fall : 9.363
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 8.758
Fall : 8.675
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 9.190
Fall : 9.237
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 9.262
Fall : 9.197
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 9.193
Fall : 9.075
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 8.870
Fall : 8.811
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 9.462
Fall : 9.314
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 8.169
Fall : 8.165
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 7.769
Fall : 7.723
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 8.654
Fall : 8.577
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 7.536
Fall : 7.508
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 9.266
Fall : 9.145
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 7.532
Fall : 7.515
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 8.347
Fall : 8.356
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 9.800
Fall : 9.526
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 10.073
Fall : 10.080
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 10.136
Fall : 10.163
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 9.933
Fall : 9.935
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 9.469
Fall : 9.489
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 9.418
Fall : 9.420
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 9.271
Fall : 9.281
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 9.411
Fall : 9.307
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 9.604
Fall : 9.643
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 7.405
Fall : 7.367
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 7.174
Fall : 7.027
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 8.081
Fall : 8.029
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 7.404
Fall : 7.279
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 9.871
Fall : 9.494
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 7.266
Fall : 7.220
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 8.783
Fall : 8.703
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 7.984
Fall : 7.960
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 9.877
Fall : 9.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 9.020
Fall : 9.001
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 9.877
Fall : 9.812
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 9.257
Fall : 9.204
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 9.751
Fall : 9.916
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 9.463
Fall : 9.405
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 9.458
Fall : 9.165
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 8.163
Fall : 8.217
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 9.615
Fall : 9.395
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_0[*]
Clock Port : CLOCK_50
Rise : 3.706
Fall : 3.729
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[0]
Clock Port : CLOCK_50
Rise : 4.396
Fall : 4.507
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[1]
Clock Port : CLOCK_50
Rise : 4.455
Fall : 4.582
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[2]
Clock Port : CLOCK_50
Rise : 3.819
Fall : 3.860
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[3]
Clock Port : CLOCK_50
Rise : 4.372
Fall : 4.496
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[4]
Clock Port : CLOCK_50
Rise : 3.988
Fall : 4.055
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[5]
Clock Port : CLOCK_50
Rise : 4.203
Fall : 4.287
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[6]
Clock Port : CLOCK_50
Rise : 4.444
Fall : 4.573
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[7]
Clock Port : CLOCK_50
Rise : 4.090
Fall : 4.150
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[8]
Clock Port : CLOCK_50
Rise : 4.085
Fall : 4.185
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[9]
Clock Port : CLOCK_50
Rise : 4.238
Fall : 4.302
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[10]
Clock Port : CLOCK_50
Rise : 4.152
Fall : 4.224
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[11]
Clock Port : CLOCK_50
Rise : 4.092
Fall : 4.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[12]
Clock Port : CLOCK_50
Rise : 4.067
Fall : 4.130
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[13]
Clock Port : CLOCK_50
Rise : 3.816
Fall : 3.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[14]
Clock Port : CLOCK_50
Rise : 4.256
Fall : 4.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[15]
Clock Port : CLOCK_50
Rise : 5.667
Fall : 5.519
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[16]
Clock Port : CLOCK_50
Rise : 4.353
Fall : 4.463
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[17]
Clock Port : CLOCK_50
Rise : 4.650
Fall : 4.762
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[18]
Clock Port : CLOCK_50
Rise : 4.587
Fall : 4.766
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[19]
Clock Port : CLOCK_50
Rise : 4.544
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[20]
Clock Port : CLOCK_50
Rise : 4.413
Fall : 4.491
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[21]
Clock Port : CLOCK_50
Rise : 4.703
Fall : 4.828
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[22]
Clock Port : CLOCK_50
Rise : 4.504
Fall : 4.604
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[23]
Clock Port : CLOCK_50
Rise : 4.319
Fall : 4.415
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[24]
Clock Port : CLOCK_50
Rise : 3.761
Fall : 3.760
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[25]
Clock Port : CLOCK_50
Rise : 3.706
Fall : 3.729
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[26]
Clock Port : CLOCK_50
Rise : 4.126
Fall : 4.166
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[27]
Clock Port : CLOCK_50
Rise : 3.985
Fall : 4.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[28]
Clock Port : CLOCK_50
Rise : 5.493
Fall : 5.301
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[29]
Clock Port : CLOCK_50
Rise : 3.962
Fall : 3.977
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[30]
Clock Port : CLOCK_50
Rise : 4.032
Fall : 4.088
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_0[31]
Clock Port : CLOCK_50
Rise : 4.207
Fall : 4.225
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[*]
Clock Port : CLOCK_50
Rise : 4.093
Fall : 4.161
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[0]
Clock Port : CLOCK_50
Rise : 4.198
Fall : 4.283
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[1]
Clock Port : CLOCK_50
Rise : 4.701
Fall : 4.868
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[2]
Clock Port : CLOCK_50
Rise : 4.093
Fall : 4.161
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[3]
Clock Port : CLOCK_50
Rise : 4.690
Fall : 4.893
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[4]
Clock Port : CLOCK_50
Rise : 4.204
Fall : 4.288
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[5]
Clock Port : CLOCK_50
Rise : 5.262
Fall : 5.126
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[6]
Clock Port : CLOCK_50
Rise : 4.137
Fall : 4.202
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : LED[7]
Clock Port : CLOCK_50
Rise : 5.544
Fall : 5.435
Clock Edge : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[32]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_0[33]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 2.5 V
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 2.5 V
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 2.32 V
Steady State Vol at FPGA Pin : 5.61e-09 V
Voh Max at FPGA Pin : 2.38 V
Vol Min at FPGA Pin : -0.00274 V
Ringback Voltage on Rise at FPGA Pin : 0.141 V
Ringback Voltage on Fall at FPGA Pin : 0.006 V
10-90 Rise Time at FPGA Pin : 4.7e-10 s
90-10 Fall Time at FPGA Pin : 6.02e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 2.32 V
Steady State Vol at Far-end : 5.61e-09 V
Voh Max at Far-end : 2.38 V
Vol Min at Far-end : -0.00274 V
Ringback Voltage on Rise at Far-end : 0.141 V
Ringback Voltage on Fall at Far-end : 0.006 V
10-90 Rise Time at Far-end : 4.7e-10 s
90-10 Fall Time at Far-end : 6.02e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : Yes
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_0[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 2.5 V
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 2.32 V
Steady State Vol at FPGA Pin : 9.45e-07 V
Voh Max at FPGA Pin : 2.35 V
Vol Min at FPGA Pin : -0.00643 V
Ringback Voltage on Rise at FPGA Pin : 0.081 V
Ringback Voltage on Fall at FPGA Pin : 0.031 V
10-90 Rise Time at FPGA Pin : 5.31e-10 s
90-10 Fall Time at FPGA Pin : 7.59e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 2.32 V
Steady State Vol at Far-end : 9.45e-07 V
Voh Max at Far-end : 2.35 V
Vol Min at Far-end : -0.00643 V
Ringback Voltage on Rise at Far-end : 0.081 V
Ringback Voltage on Fall at Far-end : 0.031 V
10-90 Rise Time at Far-end : 5.31e-10 s
90-10 Fall Time at Far-end : 7.59e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : Yes
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_0[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 2.5 V
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 2.62 V
Steady State Vol at FPGA Pin : 3.54e-08 V
Voh Max at FPGA Pin : 2.7 V
Vol Min at FPGA Pin : -0.00943 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.035 V
10-90 Rise Time at FPGA Pin : 3.19e-10 s
90-10 Fall Time at FPGA Pin : 4.99e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 2.62 V
Steady State Vol at Far-end : 3.54e-08 V
Voh Max at Far-end : 2.7 V
Vol Min at Far-end : -0.00943 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.035 V
10-90 Rise Time at Far-end : 3.19e-10 s
90-10 Fall Time at Far-end : 4.99e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 2035
FR Paths : 0
RF Paths : 0
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 2035
FR Paths : 0
RF Paths : 0
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 0
Hold : 0
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 40
Hold : 40
Property : Unconstrained Output Port Paths
Setup : 144
Hold : 144
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 14:56:15 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.088
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.088 -422.664 CLOCK_50
Info (332146): Worst-case hold slack is 0.337
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.337 0.000 CLOCK_50
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.000 -532.995 CLOCK_50
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.813
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.813 -354.793 CLOCK_50
Info (332146): Worst-case hold slack is 0.312
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.312 0.000 CLOCK_50
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.000 -532.816 CLOCK_50
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -0.824
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.824 -117.237 CLOCK_50
Info (332146): Worst-case hold slack is 0.169
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.169 0.000 CLOCK_50
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.000 -347.907 CLOCK_50
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 420 megabytes
Info: Processing ended: Wed Mar 30 14:56:17 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
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