515 lines
19 KiB
VHDL
515 lines
19 KiB
VHDL
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-- FSM for a SDRAM controller
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--
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-- Version 0.1 - Ready to simulate
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--
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-- Author: Mike Field (hamster@snap.net.nz)
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--
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-- Feel free to use it however you would like, but
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-- just drop me an email to say thanks.
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-------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity sdram_controller is
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PORT (
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CLOCK_50 : IN STD_LOGIC;
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-- Signals to/from the SDRAM chip
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DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
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DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
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DRAM_CAS_N : OUT STD_LOGIC;
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DRAM_CKE : OUT STD_LOGIC;
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DRAM_CLK : OUT STD_LOGIC;
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DRAM_CS_N : OUT STD_LOGIC;
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DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
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DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
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DRAM_RAS_N : OUT STD_LOGIC;
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DRAM_WE_N : OUT STD_LOGIC;
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--- Inputs from rest of the system
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address : IN STD_LOGIC_VECTOR (23 downto 0);
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req_read : IN STD_LOGIC;
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req_write : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
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data_out_valid : OUT STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR (31 downto 0)
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);
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end entity;
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architecture rtl of sdram_controller is
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type reg is record
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state : std_logic_vector(8 downto 0);
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address : std_logic_vector(12 downto 0);
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bank : std_logic_vector( 1 downto 0);
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init_counter: std_logic_vector(14 downto 0);
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rf_counter : std_logic_vector( 9 downto 0);
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rf_pending : std_logic;
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rd_pending : std_logic;
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wr_pending : std_logic;
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act_row : std_logic_vector(12 downto 0);
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data_out_low: std_logic_vector(15 downto 0);
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data_out_valid : std_logic;
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dq_masks : std_logic_vector(1 downto 0);
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end record;
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component sdram_clk_gen
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PORT
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(
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inclk0: IN STD_LOGIC;
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c0 : OUT STD_LOGIC;
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c1 : OUT STD_LOGIC
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);
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end component;
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-- note to self - this constant should be "(others => '0')" when not simulating!!!
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-- signal r : reg := ((others => '0'), (others => '0'),
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-- (others => '0'), "000000000001000", (others => '0'),
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-- '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'));
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signal r : reg := ((others => '0'), (others => '0'),
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(others => '0'), (others => '0'), (others => '0'),
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'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'));
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signal n : reg;
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-- Vectors for each SDRAM 'command'
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--- CS_N, RAS_N, CAS_N, WE_N
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constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
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constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
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constant cmd_write : std_logic_vector(3 downto 0) := "0100";
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constant cmd_act : std_logic_vector(3 downto 0) := "0011";
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constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
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constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
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constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
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-- State assignments
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constant s_init_nop : std_logic_vector(8 downto 0) := "00000" & cmd_nop;
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constant s_init_pre : std_logic_vector(8 downto 0) := "00000" & cmd_pre;
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constant s_init_ref : std_logic_vector(8 downto 0) := "00000" & cmd_ref;
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constant s_init_mrs : std_logic_vector(8 downto 0) := "00000" & cmd_mrs;
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constant s_idle : std_logic_vector(8 downto 0) := "00001" & cmd_nop;
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constant s_rf0 : std_logic_vector(8 downto 0) := "00010" & cmd_ref;
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constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
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constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
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constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
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constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
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constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
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constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
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constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
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constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
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constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
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constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
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constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
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constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
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constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
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constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_nop;
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constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
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constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_nop;
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constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
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constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_nop;
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constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
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constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_nop;
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constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
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constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
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constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
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constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
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constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
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constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
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constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
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signal addr_row : std_logic_vector(12 downto 0);
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signal addr_bank: std_logic_vector(1 downto 0);
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signal addr_col : std_logic_vector(9 downto 0);
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signal captured : std_logic_vector(15 downto 0);
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signal clock_100 : std_logic;
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signal clock_100_delayed_3ns : std_logic;
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begin
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-- Addressing is in 32 bit words - twice that of the DRAM width,
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-- so each burst of four access two system words.
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addr_row <= address(23 downto 11);
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addr_bank <= address(10 downto 9);
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addr_col <= address(8 downto 1) & "00";
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sdram_clk_pll: sdram_clk_gen
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-- Generate the 100MHz clock and the same phase shifted by 3ns
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PORT MAP
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(
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inclk0 => CLOCK_50,
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c0 => clock_100,
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c1 => clock_100_delayed_3ns
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);
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DRAM_CLK <= clock_100_delayed_3ns;
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DRAM_CKE <= '1';
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DRAM_CS_N <= r.state(3);
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DRAM_RAS_N <= r.state(2);
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DRAM_CAS_N <= r.state(1);
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DRAM_WE_N <= r.state(0);
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DRAM_ADDR <= r.address;
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DRAM_BA <= r.bank;
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DATA_OUT <= captured & r.data_out_low;
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DRAM_DQM <= r.dq_masks;
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data_out_valid <= r.data_out_valid;
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process (r, address, req_read, req_write, addr_row, addr_bank, addr_col, data_in, captured)
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begin
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-- copy the existing values
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n <= r;
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if req_read = '1' then
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n.rd_pending <= '1';
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n.data_out_valid <= '0';
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end if;
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if req_write = '1' then
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n.wr_pending <= '1';
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n.data_out_valid <= '0';
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end if;
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n.dq_masks <= "11";
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-- first off, do we need to perform a refresh cycle ASAP?
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if r.rf_counter = 770 then -- 781 = 64,000,000ns / 8192 / 10ns
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n.rf_counter <= (others => '0');
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n.rf_pending <= '1';
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else
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-- only start looking for refreshes outside of the initialisation state.
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if not(r.state(8 downto 4) = s_init_nop(8 downto 4)) then
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n.rf_counter <= r.rf_counter + 1;
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end if;
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end if;
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-- Set the data bus into HIZ, high and low bytes masked
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DRAM_DQ <= (others => 'Z');
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n.init_counter <= r.init_counter-1;
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-- Process the FSM
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case r.state(8 downto 4) is
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when s_init_nop(8 downto 4) =>
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n.state <= s_init_nop;
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n.address <= (others => '0');
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n.bank <= (others => '0');
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n.rf_counter <= (others => '0');
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n.data_out_valid <= '1';
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-- T-130, precharge all banks.
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if r.init_counter = "000000010000010" then
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n.state <= s_init_pre;
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n.address(10) <= '1';
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end if;
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-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
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if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
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n.state <= s_init_ref;
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end if;
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-- T-3, the load mode register
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if r.init_counter = 3 then
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n.state <= s_init_mrs;
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-- Mode register is as follows:
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-- resvd wr_b OpMd CAS=3 Seq bust=4
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n.address <= "000" & "0" & "00" & "011" & "0" & "010";
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-- resvd
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n.bank <= "00";
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end if;
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-- T-1 The switch to the FSM (first command will be a NOP
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if r.init_counter = 1 then
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n.state <= s_idle;
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end if;
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------------------------------
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-- The Idle section
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------------------------------
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when s_idle(8 downto 4) =>
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n.state <= s_idle;
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-- do we have to activate a row?
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if r.rd_pending = '1' or r.wr_pending = '1' then
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n.state <= s_ra0;
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n.address <= addr_row;
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n.act_row <= addr_row;
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end if;
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-- refreshes take priority over everything
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if r.rf_pending = '1' then
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n.state <= s_rf0;
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n.rf_pending <= '0';
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end if;
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------------------------------
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-- Row activation
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-- s_ra2 is also the "idle with active row" state and provides
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-- a resting point between operations on the same row
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------------------------------
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when s_ra0(8 downto 4) =>
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n.state <= s_ra1;
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when s_ra1(8 downto 4) =>
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n.state <= s_ra2;
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when s_ra2(8 downto 4) =>
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-- we can stay in this state until we have something to do
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n.state <= s_ra2;
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-- If there is a read pending, deactivate the row
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if r.rd_pending = '1' or r.wr_pending = '1' then
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n.state <= s_dr0;
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n.address(10) <= '1';
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end if;
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-- unless we have a read to perform on the same row? do that instead
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if r.rd_pending = '1' and r.act_row = addr_row then
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n.state <= s_rd0;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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n.dq_masks <= "00";
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n.rd_pending <= '0';
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end if;
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-- unless we have a write on the same row? writes take priroty over reads
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if r.wr_pending = '1' and r.act_row = addr_row then
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n.state <= s_wr0;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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n.dq_masks<= "00";
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n.wr_pending <= '0';
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end if;
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-- But refreshes take piority over everything!
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if r.rf_pending = '1' then
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n.state <= s_dr0;
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n.address(10) <= '1';
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end if;
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------------------------------------------------------
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-- Deactivate the current row and return to idle state
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------------------------------------------------------
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when s_dr0(8 downto 4) =>
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n.state <= s_dr1;
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when s_dr1(8 downto 4) =>
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n.state <= s_idle;
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------------------------------
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-- The Refresh section
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------------------------------
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when s_rf0(8 downto 4) =>
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n.state <= s_rf1;
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when s_rf1(8 downto 4) =>
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n.state <= s_rf2;
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when s_rf2(8 downto 4) =>
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n.state <= s_rf3;
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when s_rf3(8 downto 4) =>
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n.state <= s_rf4;
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when s_rf4(8 downto 4) =>
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n.state <= s_rf5;
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when s_rf5(8 downto 4) =>
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n.state <= s_idle;
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------------------------------
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-- The Write section
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------------------------------
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when s_wr0(8 downto 4) =>
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n.state <= s_wr1;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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DRAM_DQ <= data_in(15 downto 0);
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n.dq_masks<= "00";
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when s_wr1(8 downto 4) =>
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n.state <= s_wr2;
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DRAM_DQ <= data_in(31 downto 16);
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n.dq_masks<= "00";
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when s_wr2(8 downto 4) =>
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DRAM_DQ <= data_in(15 downto 0);
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n.state <= s_wr3;
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n.dq_masks<= "00";
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when s_wr3(8 downto 4) =>
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-- Default to the idle+row active state
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n.state <= s_ra2;
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DRAM_DQ <= data_in(31 downto 16);
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n.dq_masks<= "11";
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-- If there is a read or write then deactivate the row
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if r.rd_pending = '1' or r.wr_pending = '1' then
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n.state <= s_dr0;
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n.address(10) <= '1';
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end if;
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-- But if there is a read pending in the same row, do that
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if r.rd_pending = '1' and r.act_row = addr_row then
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n.state <= s_rd0;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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n.dq_masks <= "00";
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n.rd_pending <= '0';
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end if;
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-- unless there is a write pending in the same row, do that
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if r.wr_pending = '1' and r.act_row = addr_row then
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n.state <= s_wr0;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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n.dq_masks<= "00";
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n.wr_pending <= '0';
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end if;
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-- But always try and refresh if one is pending!
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if r.rf_pending = '1' then
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n.state <= s_dr0;
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n.address(10) <= '1';
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end if;
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------------------------------
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-- The Read section
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------------------------------
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when s_rd0(8 downto 4) =>
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n.state <= s_rd1;
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n.dq_masks <= "00";
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when s_rd1(8 downto 4) =>
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n.state <= s_rd2;
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n.dq_masks <= "00";
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when s_rd2(8 downto 4) =>
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n.state <= s_rd3;
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n.dq_masks <= "00";
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when s_rd3(8 downto 4) =>
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-- default is to end the read with the row open
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n.state <= s_rd7;
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-- otherwise if there is a read or write prepare to deactivate the row.
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-- (This is overridden if the read/write is to the same page)
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if r.rd_pending = '1' or r.wr_pending = '1' then
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n.state <= s_drdr0;
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n.address(10) <= '1';
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end if;
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-- override if the write is from the same row
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if r.wr_pending = '1' and r.act_row = addr_row then
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n.state <= s_rd7;
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end if;
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-- override if the read is from the same row
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if r.rd_pending = '1' and r.act_row = addr_row then
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n.state <= s_rd4;
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n.address <= "000" & addr_col;
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n.bank <= addr_bank;
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n.dq_masks<= "00";
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end if;
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-- If a refresh is pending then always deactivate the row
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if r.rf_pending = '1' then
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n.state <= s_drdr0;
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n.address(10) <= '1';
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end if;
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n.data_out_low <= captured;
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n.data_out_valid <= '1';
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when s_rd4(8 downto 4) =>
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n.state <= s_rd5;
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n.dq_masks<= "00";
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when s_rd5(8 downto 4) =>
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n.state <= s_rd6;
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n.data_out_low <= captured;
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n.data_out_valid <= '1';
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n.dq_masks<= "00";
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when s_rd6(8 downto 4) =>
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n.state <= s_rd3;
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n.dq_masks<= "00";
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when s_rd7(8 downto 4) =>
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n.state <= s_rd8;
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n.data_out_low <= captured;
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n.data_out_valid <= '1';
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when s_rd8(8 downto 4) =>
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n.state <= s_rd9;
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when s_rd9(8 downto 4) =>
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-- by default go to the idle-with-row-active state
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n.state <= s_ra2;
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n.data_out_low <= captured;
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n.data_out_valid <= '1';
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-- otherwise if there is a read or write prepare to deactivate the row.
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-- (This is overridden if the read/write is to the same row)
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if r.rd_pending = '1' or r.wr_pending = '1' then
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n.state <= s_dr0;
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n.address(10) <= '1';
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end if;
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|
-- this is to catch if a read has turned up since the choices at state s_dr3
|
|
if r.rd_pending = '1' and r.act_row = addr_row then
|
|
n.state <= s_rd0;
|
|
n.address <= "000" & addr_col;
|
|
n.bank <= addr_bank;
|
|
n.dq_masks <= "00";
|
|
n.rd_pending <= '0';
|
|
end if;
|
|
|
|
-- this is to catch if a read has turned up since the choices at state s_dr3
|
|
if r.wr_pending = '1' and r.act_row = addr_row then
|
|
n.state <= s_wr0;
|
|
n.address <= "000" & addr_col;
|
|
n.bank <= addr_bank;
|
|
n.dq_masks<= "00";
|
|
n.wr_pending <= '0';
|
|
end if;
|
|
|
|
if r.rf_pending = '1' then
|
|
n.state <= s_dr0;
|
|
n.address(10) <= '1';
|
|
end if;
|
|
|
|
------------------------------
|
|
-- The Deactivate row during read section
|
|
------------------------------
|
|
when s_drdr0(8 downto 4) =>
|
|
n.state <= s_drdr1;
|
|
when s_drdr1(8 downto 4) =>
|
|
n.state <= s_drdr2;
|
|
n.data_out_low <= captured;
|
|
n.data_out_valid <= '1';
|
|
when s_drdr2(8 downto 4) =>
|
|
n.state <= s_idle;
|
|
|
|
if r.rf_pending = '1' then
|
|
n.state <= s_rf0;
|
|
end if;
|
|
|
|
if r.rd_pending = '1' or r.wr_pending = '1' then
|
|
n.state <= s_ra0;
|
|
n.address <= addr_row;
|
|
n.act_row <= addr_row;
|
|
n.bank <= addr_bank;
|
|
end if;
|
|
|
|
when others =>
|
|
n.state <= s_init_nop;
|
|
end case;
|
|
end process;
|
|
|
|
--- The clock driven logic
|
|
process (clock_100, n)
|
|
begin
|
|
if clock_100'event and clock_100 = '1' then
|
|
r <= n;
|
|
end if;
|
|
end process;
|
|
|
|
process (clock_100_delayed_3ns, dram_dq)
|
|
begin
|
|
if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
|
|
captured <= dram_dq;
|
|
end if;
|
|
end process;
|
|
|
|
end rtl; |