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TimeQuest Timing Analyzer report for spectrum
Sat Apr 2 16:35:59 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
17. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
18. Slow 1200mV 85C Model Hold: 'CLOCK_50'
19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
21. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
22. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
24. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
25. Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
27. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
28. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
29. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
30. Setup Times
31. Hold Times
32. Clock to Output Times
33. Minimum Clock to Output Times
34. Propagation Delay
35. Minimum Propagation Delay
36. Output Enable Times
37. Minimum Output Enable Times
38. Output Disable Times
39. Minimum Output Disable Times
40. Slow 1200mV 85C Model Metastability Report
41. Slow 1200mV 0C Model Fmax Summary
42. Slow 1200mV 0C Model Setup Summary
43. Slow 1200mV 0C Model Hold Summary
44. Slow 1200mV 0C Model Recovery Summary
45. Slow 1200mV 0C Model Removal Summary
46. Slow 1200mV 0C Model Minimum Pulse Width Summary
47. Slow 1200mV 0C Model Setup: 'CLOCK_50'
48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
50. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
51. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
52. Slow 1200mV 0C Model Hold: 'CLOCK_50'
53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
54. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
55. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
56. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
59. Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
60. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
61. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
62. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
63. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
64. Setup Times
65. Hold Times
66. Clock to Output Times
67. Minimum Clock to Output Times
68. Propagation Delay
69. Minimum Propagation Delay
70. Output Enable Times
71. Minimum Output Enable Times
72. Output Disable Times
73. Minimum Output Disable Times
74. Slow 1200mV 0C Model Metastability Report
75. Fast 1200mV 0C Model Setup Summary
76. Fast 1200mV 0C Model Hold Summary
77. Fast 1200mV 0C Model Recovery Summary
78. Fast 1200mV 0C Model Removal Summary
79. Fast 1200mV 0C Model Minimum Pulse Width Summary
80. Fast 1200mV 0C Model Setup: 'CLOCK_50'
81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
83. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
84. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
85. Fast 1200mV 0C Model Hold: 'CLOCK_50'
86. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
88. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
89. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
93. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
94. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
95. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
96. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
97. Setup Times
98. Hold Times
99. Clock to Output Times
100. Minimum Clock to Output Times
101. Propagation Delay
102. Minimum Propagation Delay
103. Output Enable Times
104. Minimum Output Enable Times
105. Output Disable Times
106. Minimum Output Disable Times
107. Fast 1200mV 0C Model Metastability Report
108. Multicorner Timing Analysis Summary
109. Setup Times
110. Hold Times
111. Clock to Output Times
112. Minimum Clock to Output Times
113. Propagation Delay
114. Minimum Propagation Delay
115. Board Trace Model Assignments
116. Input Transition Times
117. Signal Integrity Metrics (Slow 1200mv 0c Model)
118. Signal Integrity Metrics (Slow 1200mv 85c Model)
119. Signal Integrity Metrics (Fast 1200mv 0c Model)
120. Setup Transfers
121. Hold Transfers
122. Recovery Transfers
123. Removal Transfers
124. Report TCCS
125. Report RSKM
126. Unconstrained Paths
127. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; SDC File List ;
+--------------------------------------------------------------------------------+
SDC File Path : spectrum.sdc
Status : OK
Read at : Sat Apr 2 16:35:56 2022
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : beep
Type : Base
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { ula:ula_|beep }
Clock Name : CLOCK_50
Type : Base
Period : 20.000
Frequency : 50.0 MHz
Rise : 0.000
Fall : 10.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 10.000
Frequency : 100.0 MHz
Rise : 3.000
Fall : 8.000
Duty Cycle : 50.00
Divide by : 1
Multiply by : 2
Phase : 108.0
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]
Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 39.716
Frequency : 25.18 MHz
Rise : 0.000
Fall : 19.858
Duty Cycle : 50.00
Divide by : 280
Multiply by : 141
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 71.489
Frequency : 13.99 MHz
Rise : 0.000
Fall : 35.744
Duty Cycle : 50.00
Divide by : 168
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Type : Generated
Period : 41.702
Frequency : 23.98 MHz
Rise : 0.000
Fall : 20.851
Duty Cycle : 50.00
Divide by : 98
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 48.05 MHz
Restricted Fmax : 48.05 MHz
Clock Name : CLOCK_50
Note :
Fmax : 129.33 MHz
Restricted Fmax : 129.33 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 133.33 MHz
Restricted Fmax : 133.33 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 197.71 MHz
Restricted Fmax : 197.71 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 938.97 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -18.257
End Point TNS : -809.639
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -7.550
End Point TNS : -292.429
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.737
End Point TNS : -40.228
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.914
End Point TNS : -2.914
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 2.500
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -0.026
End Point TNS : -0.026
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.343
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.358
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -6.225
End Point TNS : -455.695
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.696
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.752
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.489
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.601
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.596
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -18.257
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.098
Slack : -18.195
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.749
Slack : -18.184
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 8.025
Slack : -18.113
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.954
Slack : -18.106
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.664
Slack : -18.104
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.945
Slack : -18.066
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.620
Slack : -18.063
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.904
Slack : -18.044
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 7.611
Slack : -18.027
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.868
Slack : -18.022
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.863
Slack : -18.015
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.835
Slack : -18.012
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.562
Slack : -18.006
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.564
Slack : -17.976
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.796
Slack : -17.966
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.807
Slack : -17.962
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.803
Slack : -17.961
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.517
Slack : -17.955
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.513
Slack : -17.950
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.526
Data Delay : 7.498
Slack : -17.947
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.505
Slack : -17.941
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.782
Slack : -17.937
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 7.488
Slack : -17.915
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.465
Slack : -17.915
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 7.482
Slack : -17.898
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.739
Slack : -17.887
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 7.439
Slack : -17.885
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.443
Slack : -17.884
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.702
Slack : -17.877
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.435
Slack : -17.861
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.411
Slack : -17.838
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.658
Slack : -17.818
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.376
Slack : -17.797
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.615
Slack : -17.790
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.631
Slack : -17.782
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.623
Slack : -17.761
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.311
Slack : -17.754
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.304
Slack : -17.741
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.259
Data Delay : 7.556
Slack : -17.732
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 7.288
Slack : -17.732
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.552
Slack : -17.721
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.526
Data Delay : 7.269
Slack : -17.717
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 7.270
Slack : -17.712
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.553
Slack : -17.706
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.519
Data Delay : 7.261
Slack : -17.706
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.526
Slack : -17.693
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.254
Slack : -17.691
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.511
Slack : -17.686
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.527
Slack : -17.678
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.228
Slack : -17.672
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 7.225
Slack : -17.669
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.255
Data Delay : 7.488
Slack : -17.663
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.213
Slack : -17.647
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.488
Slack : -17.640
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.255
Data Delay : 7.459
Slack : -17.632
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.473
Slack : -17.631
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.451
Slack : -17.624
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.465
Slack : -17.615
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.433
Slack : -17.610
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.160
Slack : -17.608
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 7.162
Slack : -17.585
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.259
Data Delay : 7.400
Slack : -17.585
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 7.147
Slack : -17.578
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 7.144
Slack : -17.570
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.259
Data Delay : 7.385
Slack : -17.568
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.386
Slack : -17.565
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.406
Slack : -17.560
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.401
Slack : -17.557
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 7.117
Slack : -17.555
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.519
Data Delay : 7.110
Slack : -17.542
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.383
Slack : -17.539
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.254
Data Delay : 7.359
Slack : -17.536
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.354
Slack : -17.529
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.370
Slack : -17.512
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.330
Slack : -17.490
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.055
Slack : -17.488
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 7.041
Slack : -17.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.328
Slack : -17.486
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.045
Slack : -17.482
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.047
Slack : -17.480
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.041
Slack : -17.478
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.037
Slack : -17.472
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.313
Slack : -17.445
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.263
Slack : -17.443
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.996
Slack : -17.430
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.982
Slack : -17.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.986
Slack : -17.394
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.953
Slack : -17.386
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.945
Slack : -17.383
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.944
Slack : -17.376
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.233
Data Delay : 7.217
Slack : -17.374
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.933
Slack : -17.369
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.933
Slack : -17.338
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.259
Data Delay : 7.153
Slack : -17.325
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.888
Slack : -17.291
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.256
Data Delay : 7.109
Slack : -17.275
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.838
Slack : -17.275
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.837
Slack : -17.268
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.834
Slack : -17.267
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.830
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -7.550
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.288
Data Delay : 5.370
Slack : -7.542
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.301
Data Delay : 5.349
Slack : -7.478
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 5.592
Slack : -7.352
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.285
Data Delay : 5.175
Slack : -7.350
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.286
Data Delay : 5.172
Slack : -7.292
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 5.120
Slack : -7.289
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 5.113
Slack : -7.286
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 5.103
Slack : -7.284
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.293
Data Delay : 5.099
Slack : -7.281
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.297
Data Delay : 5.092
Slack : -7.273
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 5.091
Slack : -7.265
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 5.082
Slack : -7.241
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.282
Data Delay : 5.067
Slack : -7.233
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.295
Data Delay : 5.046
Slack : -7.231
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.290
Data Delay : 5.049
Slack : -7.220
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.986
Data Delay : 5.342
Slack : -7.217
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 5.335
Slack : -7.173
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.288
Data Delay : 4.993
Slack : -7.169
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 5.289
Slack : -7.117
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.296
Data Delay : 4.929
Slack : -7.113
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.289
Data Delay : 4.932
Slack : -7.088
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.300
Data Delay : 4.896
Slack : -7.084
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.283
Data Delay : 4.909
Slack : -7.082
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.261
Data Delay : 4.929
Slack : -7.078
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.281
Data Delay : 4.905
Slack : -7.024
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.275
Data Delay : 4.857
Slack : -7.022
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.868
Slack : -7.013
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.867
Slack : -7.011
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 4.863
Slack : -7.008
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.274
Data Delay : 4.842
Slack : -6.982
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.841
Slack : -6.981
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.847
Slack : -6.979
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.278
Data Delay : 4.809
Slack : -6.975
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.270
Data Delay : 4.813
Slack : -6.969
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.308
Data Delay : 4.769
Slack : -6.968
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 4.835
Slack : -6.964
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.276
Data Delay : 4.796
Slack : -6.960
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.826
Slack : -6.926
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 4.793
Slack : -6.860
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.286
Data Delay : 4.682
Slack : -6.848
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.253
Data Delay : 4.703
Slack : -6.848
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.672
Slack : -6.839
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.663
Slack : -6.830
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.667
Slack : -6.812
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.267
Data Delay : 4.653
Slack : -6.803
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.662
Slack : -6.802
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.661
Slack : -6.800
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.253
Data Delay : 4.655
Slack : -6.798
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.652
Slack : -6.794
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.622
Slack : -6.789
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.286
Data Delay : 4.611
Slack : -6.787
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.287
Data Delay : 4.608
Slack : -6.781
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.610
Slack : -6.773
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.280
Data Delay : 4.601
Slack : -6.772
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.272
Data Delay : 4.608
Slack : -6.757
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.608
Slack : -6.755
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.246
Data Delay : 4.617
Slack : -6.752
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.250
Data Delay : 4.610
Slack : -6.748
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.599
Slack : -6.743
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.250
Data Delay : 4.601
Slack : -6.739
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.568
Slack : -6.717
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.568
Slack : -6.715
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.294
Data Delay : 4.529
Slack : -6.704
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.564
Slack : -6.699
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.536
Slack : -6.690
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.527
Slack : -6.688
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.292
Data Delay : 4.504
Slack : -6.687
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.541
Slack : -6.678
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.291
Data Delay : 4.495
Slack : -6.662
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.525
Slack : -6.658
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 4.524
Slack : -6.650
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.271
Data Delay : 4.487
Slack : -6.649
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.513
Slack : -6.644
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.265
Data Delay : 4.487
Slack : -6.641
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.504
Slack : -6.629
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.246
Data Delay : 4.491
Slack : -6.617
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.263
Data Delay : 4.462
Slack : -6.616
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.470
Slack : -6.609
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.269
Data Delay : 4.448
Slack : -6.607
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.453
Slack : -6.607
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.471
Slack : -6.590
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.300
Data Delay : 4.398
Slack : -6.565
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.279
Data Delay : 4.394
Slack : -6.535
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.276
Data Delay : 4.367
Slack : -6.534
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.304
Data Delay : 4.338
Slack : -6.532
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.389
Slack : -6.526
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.385
Slack : -6.521
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.284
Data Delay : 4.345
Slack : -6.519
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.278
Data Delay : 4.349
Slack : -6.515
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.282
Data Delay : 4.341
Slack : -6.510
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.364
Slack : -6.510
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.253
Data Delay : 4.365
Slack : -6.507
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.302
Data Delay : 4.313
Slack : -6.497
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.301
Data Delay : 4.304
Slack : -6.486
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.345
Slack : -6.481
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.278
Data Delay : 4.311
Slack : -6.478
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.341
Slack : -6.474
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.267
Data Delay : 4.315
Slack : -6.469
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.332
Slack : -6.453
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.310
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.737
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 2.828
Slack : -4.251
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.173
Data Delay : 2.803
Slack : -4.251
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.173
Data Delay : 2.803
Slack : -4.052
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.621
Slack : -4.052
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.621
Slack : -4.052
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.621
Slack : -4.052
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.621
Slack : -4.052
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.621
Slack : -3.592
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.203
Data Delay : 2.174
Slack : -3.137
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.177
Data Delay : 1.693
Slack : 16.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.473
Slack : 16.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.473
Slack : 16.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.473
Slack : 16.985
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.473
Slack : 17.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.387
Data Delay : 3.435
Slack : 17.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.387
Data Delay : 3.435
Slack : 17.024
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.387
Data Delay : 3.435
Slack : 17.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.395
Slack : 17.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.388
Data Delay : 3.395
Slack : 17.115
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.300
Slack : 17.115
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.300
Slack : 17.115
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.300
Slack : 17.115
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.300
Slack : 17.148
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.387
Data Delay : 3.311
Slack : 17.148
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.387
Data Delay : 3.311
Slack : 17.157
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.259
Slack : 17.157
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.259
Slack : 17.157
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.259
Slack : 17.203
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.212
Slack : 17.203
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.212
Slack : 17.239
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.176
Slack : 17.239
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.176
Slack : 17.239
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.176
Slack : 17.239
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.176
Slack : 17.278
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.138
Slack : 17.278
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.138
Slack : 17.278
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.138
Slack : 17.280
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.136
Slack : 17.280
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.136
Slack : 17.317
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.098
Slack : 17.317
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.098
Slack : 17.356
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.059
Slack : 17.356
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.059
Slack : 17.356
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.059
Slack : 17.356
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.059
Slack : 17.398
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.018
Slack : 17.398
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.018
Slack : 17.398
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.018
Slack : 17.402
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.014
Slack : 17.402
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.014
Slack : 17.438
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.977
Slack : 17.438
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.977
Slack : 17.521
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.895
Slack : 17.521
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.895
Slack : 17.628
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 3.165
Slack : 17.628
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 3.165
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.036
Data Delay : 3.160
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.036
Data Delay : 3.160
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.036
Data Delay : 3.160
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.036
Data Delay : 3.160
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.036
Data Delay : 3.160
Slack : 17.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 3.003
Slack : 17.747
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 3.003
Slack : 17.764
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.651
Slack : 17.764
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.651
Slack : 17.764
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.651
Slack : 17.764
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.651
Slack : 17.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.998
Slack : 17.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.998
Slack : 17.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.998
Slack : 17.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.998
Slack : 17.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.998
Slack : 17.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.389
Data Delay : 2.683
Slack : 17.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.389
Data Delay : 2.683
Slack : 17.774
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.389
Data Delay : 2.683
Slack : 17.806
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.610
Slack : 17.806
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.610
Slack : 17.806
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.610
Slack : 17.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.559
Slack : 17.856
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.559
Slack : 17.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.550
Slack : 17.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.550
Slack : 17.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.550
Slack : 17.865
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.550
Slack : 17.879
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.419
Data Delay : 2.453
Slack : 17.882
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 2.868
Slack : 17.882
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 2.868
Slack : 17.893
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.521
Slack : 17.893
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.521
Slack : 17.893
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.521
Slack : 17.904
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.863
Slack : 17.904
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.863
Slack : 17.904
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.863
Slack : 17.904
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.863
Slack : 17.904
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 2.863
Slack : 17.907
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.509
Slack : 17.907
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.509
Slack : 17.907
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.509
Slack : 17.915
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.389
Data Delay : 2.542
Slack : 17.918
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.389
Data Delay : 2.539
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.914
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.216
Data Delay : 1.508
Slack : 70.424
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.982
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 2.500
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.983
Slack : 2.646
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 6.835
Slack : 2.851
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.632
Slack : 2.853
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.435
Data Delay : 6.612
Slack : 2.868
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.615
Slack : 2.875
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.608
Slack : 2.883
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 6.583
Slack : 2.918
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.414
Data Delay : 6.566
Slack : 2.990
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.490
Slack : 2.997
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 6.484
Slack : 3.005
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.475
Slack : 3.014
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 6.467
Slack : 3.021
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 6.460
Slack : 3.125
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.358
Slack : 3.149
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.331
Slack : 3.204
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.435
Data Delay : 6.261
Slack : 3.221
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.435
Data Delay : 6.244
Slack : 3.228
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.435
Data Delay : 6.237
Slack : 3.232
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 6.250
Slack : 3.232
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 6.250
Slack : 3.234
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 6.232
Slack : 3.251
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 6.215
Slack : 3.258
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 6.208
Slack : 3.269
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.414
Data Delay : 6.215
Slack : 3.278
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.099
Data Delay : 6.523
Slack : 3.286
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.414
Data Delay : 6.198
Slack : 3.293
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.414
Data Delay : 6.191
Slack : 3.301
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 6.501
Slack : 3.332
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.148
Slack : 3.347
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.133
Slack : 3.391
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.089
Slack : 3.393
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.087
Slack : 3.406
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.074
Slack : 3.408
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 6.072
Slack : 3.410
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 6.048
Slack : 3.450
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.033
Slack : 3.474
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.440
Data Delay : 5.986
Slack : 3.476
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 6.007
Slack : 3.490
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.968
Slack : 3.493
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 5.990
Slack : 3.500
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 5.980
Slack : 3.500
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.415
Data Delay : 5.983
Slack : 3.517
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 5.963
Slack : 3.524
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 5.956
Slack : 3.534
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 6.285
Slack : 3.552
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.437
Data Delay : 5.911
Slack : 3.555
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 6.261
Slack : 3.568
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 6.249
Slack : 3.583
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.899
Slack : 3.583
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.899
Slack : 3.596
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 5.885
Slack : 3.600
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.882
Slack : 3.600
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.882
Slack : 3.606
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 6.212
Slack : 3.606
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 6.212
Slack : 3.607
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.875
Slack : 3.607
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.875
Slack : 3.676
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.099
Data Delay : 6.125
Slack : 3.699
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.098
Data Delay : 6.103
Slack : 3.740
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 6.081
Slack : 3.752
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.417
Data Delay : 5.729
Slack : 3.757
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 6.060
Slack : 3.758
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.416
Data Delay : 5.724
Slack : 3.761
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.697
Slack : 3.774
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 5.692
Slack : 3.778
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.680
Slack : 3.778
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 6.043
Slack : 3.778
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 6.043
Slack : 3.785
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.673
Slack : 3.788
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 6.033
Slack : 3.792
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.666
Slack : 3.803
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.435
Data Delay : 5.662
Slack : 3.816
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.440
Data Delay : 5.644
Slack : 3.832
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.626
Slack : 3.833
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.434
Data Delay : 5.633
Slack : 3.840
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.097
Data Delay : 5.963
Slack : 3.841
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.978
Slack : 3.843
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.978
Slack : 3.865
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 5.615
Slack : 3.868
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.414
Data Delay : 5.616
Slack : 3.870
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.096
Data Delay : 5.934
Slack : 3.875
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.440
Data Delay : 5.585
Slack : 3.877
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.440
Data Delay : 5.583
Slack : 3.880
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.418
Data Delay : 5.600
Slack : 3.891
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.567
Slack : 3.892
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.397
Data Delay : 5.706
Slack : 3.893
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.442
Data Delay : 5.565
Slack : 3.894
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.437
Data Delay : 5.569
Slack : 3.923
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.896
Slack : 3.932
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.887
Slack : 3.944
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.437
Data Delay : 5.519
Slack : 3.945
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.876
Slack : 3.951
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.437
Data Delay : 5.512
Slack : 3.953
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.863
Slack : 3.988
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.833
Slack : 4.003
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.079
Data Delay : 5.816
Slack : 4.004
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.814
Slack : 4.004
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.080
Data Delay : 5.814
Slack : 4.015
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.082
Data Delay : 5.801
Slack : 4.028
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.081
Data Delay : 5.789
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -0.026
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.652
Data Delay : 2.917
Slack : 0.114
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.650
Data Delay : 3.055
Slack : 0.520
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.738
Slack : 0.521
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.658
Data Delay : 3.470
Slack : 0.590
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.651
Data Delay : 3.532
Slack : 1.019
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 3.870
Slack : 1.021
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.362
Data Delay : 3.674
Slack : 1.025
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 3.874
Slack : 1.035
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 3.890
Slack : 1.037
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 3.880
Slack : 1.051
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 3.902
Slack : 1.051
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 3.902
Slack : 1.052
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 3.901
Slack : 1.056
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 3.899
Slack : 1.056
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 3.904
Slack : 1.057
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 3.898
Slack : 1.057
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 3.897
Slack : 1.058
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 3.906
Slack : 1.063
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 3.907
Slack : 1.064
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 3.913
Slack : 1.077
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.912
Slack : 1.078
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.925
Slack : 1.081
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.549
Data Delay : 3.921
Slack : 1.084
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.931
Slack : 1.085
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.547
Data Delay : 3.923
Slack : 1.087
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 3.942
Slack : 1.091
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 3.939
Slack : 1.100
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 3.936
Slack : 1.100
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 3.955
Slack : 1.105
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.940
Slack : 1.105
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.652
Data Delay : 4.048
Slack : 1.107
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.547
Data Delay : 3.945
Slack : 1.107
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 3.951
Slack : 1.107
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 3.952
Slack : 1.110
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 3.947
Slack : 1.113
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.960
Slack : 1.116
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.951
Slack : 1.117
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.964
Slack : 1.117
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 3.953
Slack : 1.119
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.363
Data Delay : 3.773
Slack : 1.122
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 3.967
Slack : 1.122
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 3.968
Slack : 1.124
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 3.972
Slack : 1.127
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.962
Slack : 1.128
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 3.965
Slack : 1.129
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.976
Slack : 1.129
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 3.977
Slack : 1.130
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.548
Data Delay : 3.969
Slack : 1.136
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.543
Data Delay : 3.970
Slack : 1.139
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.974
Slack : 1.141
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.988
Slack : 1.143
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.978
Slack : 1.144
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.543
Data Delay : 3.978
Slack : 1.145
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.547
Data Delay : 3.983
Slack : 1.146
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.362
Data Delay : 3.799
Slack : 1.148
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.003
Slack : 1.150
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 3.997
Slack : 1.151
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 3.986
Slack : 1.151
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 3.987
Slack : 1.151
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.001
Slack : 1.153
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.000
Slack : 1.153
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 3.989
Slack : 1.153
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 3.989
Slack : 1.154
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 3.991
Slack : 1.156
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.005
Slack : 1.157
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.543
Data Delay : 3.991
Slack : 1.159
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.003
Slack : 1.161
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.360
Data Delay : 3.812
Slack : 1.162
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.355
Data Delay : 3.808
Slack : 1.164
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 4.000
Slack : 1.164
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.011
Slack : 1.165
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.014
Slack : 1.166
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.011
Slack : 1.170
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.015
Slack : 1.171
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.018
Slack : 1.171
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.547
Data Delay : 4.009
Slack : 1.171
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.015
Slack : 1.173
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.029
Slack : 1.176
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.545
Data Delay : 4.012
Slack : 1.177
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.358
Data Delay : 3.826
Slack : 1.177
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 4.014
Slack : 1.178
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.030
Slack : 1.180
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 4.017
Slack : 1.180
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.638
Data Delay : 4.109
Slack : 1.182
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.033
Slack : 1.184
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.543
Data Delay : 4.018
Slack : 1.186
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 4.023
Slack : 1.189
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.036
Slack : 1.190
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 4.025
Slack : 1.193
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 4.028
Slack : 1.193
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.544
Data Delay : 4.028
Slack : 1.193
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.543
Data Delay : 4.027
Slack : 1.193
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.038
Slack : 1.194
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.043
Slack : 1.195
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.547
Data Delay : 4.033
Slack : 1.196
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.037
Slack : 1.198
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.045
Slack : 1.199
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.557
Data Delay : 4.047
Slack : 1.200
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.565
Data Delay : 4.056
Slack : 1.201
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.546
Data Delay : 4.038
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.546
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 0.767
Slack : 0.547
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.782
Slack : 0.552
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.772
Slack : 0.553
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.657
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.876
Slack : 0.787
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.008
Slack : 0.826
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.046
Slack : 0.859
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.084
Slack : 0.866
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.086
Slack : 0.873
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.108
Slack : 0.968
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.194
Slack : 0.986
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.209
Slack : 0.998
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.224
Slack : 1.070
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.291
Slack : 1.087
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.308
Slack : 1.088
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 0.989
Slack : 1.088
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 0.989
Slack : 1.100
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.321
Slack : 1.115
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 1.016
Slack : 1.133
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.353
Slack : 1.142
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.284
Data Delay : 1.015
Slack : 1.142
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.367
Slack : 1.191
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 1.060
Slack : 1.193
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 1.062
Slack : 1.202
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 1.426
Slack : 1.215
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.440
Slack : 1.215
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.802
Slack : 1.216
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.441
Slack : 1.229
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.449
Slack : 1.231
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 1.132
Slack : 1.234
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.459
Slack : 1.242
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.829
Slack : 1.249
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.475
Slack : 1.249
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.475
Slack : 1.253
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 1.154
Slack : 1.257
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 1.158
Slack : 1.257
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.483
Slack : 1.267
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.284
Data Delay : 1.140
Slack : 1.269
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.495
Slack : 1.271
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.497
Slack : 1.276
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.284
Data Delay : 1.149
Slack : 1.276
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.502
Slack : 1.278
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.285
Data Delay : 1.150
Slack : 1.288
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.284
Data Delay : 1.161
Slack : 1.295
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.516
Slack : 1.303
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.285
Data Delay : 1.175
Slack : 1.316
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.542
Slack : 1.316
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.542
Slack : 1.331
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.554
Slack : 1.336
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.256
Data Delay : 1.237
Slack : 1.347
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.570
Slack : 1.360
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.585
Slack : 1.369
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.595
Slack : 1.369
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 1.593
Slack : 1.371
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.597
Slack : 1.379
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.605
Slack : 1.381
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.607
Slack : 1.381
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.607
Slack : 1.391
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.617
Slack : 1.398
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.624
Slack : 1.400
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.987
Slack : 1.400
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.626
Slack : 1.402
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.628
Slack : 1.404
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 1.991
Slack : 1.408
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.634
Slack : 1.423
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.648
Slack : 1.472
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.430
Data Delay : 2.059
Slack : 1.481
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.707
Slack : 1.483
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 1.708
Slack : 1.491
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.717
Slack : 1.495
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 1.719
Slack : 1.512
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.738
Slack : 1.513
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 1.382
Slack : 1.515
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 1.384
Slack : 1.516
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.739
Slack : 1.520
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.066
Data Delay : 1.743
Slack : 1.527
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.285
Data Delay : 1.399
Slack : 1.538
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.758
Slack : 1.551
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.772
Slack : 1.558
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.784
Slack : 1.558
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.784
Slack : 1.559
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.785
Slack : 1.564
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.784
Slack : 1.565
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.785
Slack : 1.571
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.797
Slack : 1.571
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 1.797
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.576
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.811
Slack : 1.324
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.636
Data Delay : 1.190
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.343
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.577
Slack : 0.343
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.577
Slack : 0.344
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.577
Slack : 0.346
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.580
Slack : 0.346
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.580
Slack : 0.346
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.580
Slack : 0.347
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.580
Slack : 0.357
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.591
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.592
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.359
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.593
Slack : 0.359
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.593
Slack : 0.359
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.593
Slack : 0.359
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.593
Slack : 0.360
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.594
Slack : 0.360
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.594
Slack : 0.360
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.362
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.597
Slack : 0.373
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.594
Slack : 0.378
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.076
Data Delay : 0.611
Slack : 0.394
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.628
Slack : 0.407
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.626
Slack : 0.478
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.698
Slack : 0.534
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.753
Slack : 0.535
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.769
Slack : 0.536
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.770
Slack : 0.538
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.772
Slack : 0.538
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.772
Slack : 0.540
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.774
Slack : 0.543
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.778
Slack : 0.543
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.778
Slack : 0.545
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.780
Slack : 0.553
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.757
Slack : 0.556
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.790
Slack : 0.559
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.779
Slack : 0.562
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.782
Slack : 0.571
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.805
Slack : 0.571
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.790
Slack : 0.573
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.793
Slack : 0.574
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.794
Slack : 0.576
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.810
Slack : 0.582
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.802
Slack : 0.589
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.823
Slack : 0.592
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.412
Data Delay : 1.161
Slack : 0.594
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.828
Slack : 0.594
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.813
Slack : 0.598
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.832
Slack : 0.605
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.825
Slack : 0.607
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.826
Slack : 0.609
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.828
Slack : 0.618
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.852
Slack : 0.618
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.837
Slack : 0.623
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.857
Slack : 0.648
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.868
Slack : 0.672
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.875
Slack : 0.686
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.120
Data Delay : 0.963
Slack : 0.688
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.907
Slack : 0.694
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.897
Slack : 0.701
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.936
Slack : 0.727
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.947
Slack : 0.736
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.955
Slack : 0.755
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.443
Data Delay : 1.355
Slack : 0.764
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.983
Slack : 0.777
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.412
Data Delay : 1.346
Slack : 0.803
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.049
Data Delay : 1.009
Slack : 0.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.053
Slack : 0.819
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.054
Slack : 0.831
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.052
Slack : 0.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.066
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.834
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.054
Slack : 0.834
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.054
Slack : 0.836
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.070
Slack : 0.837
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.058
Slack : 0.837
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.058
Slack : 0.838
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.072
Slack : 0.838
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.072
Slack : 0.839
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.060
Slack : 0.841
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.075
Slack : 0.844
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.065
Slack : 0.845
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.066
Slack : 0.845
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.079
Slack : 0.846
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.066
Slack : 0.848
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.068
Slack : 0.849
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.068
Slack : 0.850
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.070
Slack : 0.855
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.074
Slack : 0.863
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.097
Slack : 0.865
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 1.099
Slack : 0.881
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.100
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.358
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.359
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.577
Slack : 0.361
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.380
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.598
Slack : 0.420
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.638
Slack : 0.502
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.720
Slack : 0.557
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.776
Slack : 0.558
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.776
Slack : 0.558
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.777
Slack : 0.559
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.777
Slack : 0.559
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.777
Slack : 0.560
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.778
Slack : 0.560
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.779
Slack : 0.561
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.562
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.780
Slack : 0.563
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.563
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.781
Slack : 0.569
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.788
Slack : 0.570
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.789
Slack : 0.570
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.789
Slack : 0.571
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.790
Slack : 0.572
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.572
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.572
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.791
Slack : 0.574
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.793
Slack : 0.574
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.793
Slack : 0.580
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.798
Slack : 0.687
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.905
Slack : 0.832
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.051
Slack : 0.833
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.052
Slack : 0.833
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.051
Slack : 0.833
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.051
Slack : 0.834
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.052
Slack : 0.836
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.054
Slack : 0.838
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.056
Slack : 0.844
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.063
Slack : 0.845
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.064
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.065
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.065
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.065
Slack : 0.847
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.065
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.066
Slack : 0.848
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.067
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.067
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.068
Slack : 0.851
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.069
Slack : 0.852
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.070
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.078
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.078
Slack : 0.860
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.079
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.080
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.080
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.080
Slack : 0.861
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.080
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.082
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.082
Slack : 0.891
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.109
Slack : 0.942
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.161
Slack : 0.943
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.161
Slack : 0.943
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.161
Slack : 0.944
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.162
Slack : 0.944
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.163
Slack : 0.945
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.163
Slack : 0.945
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.163
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.946
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.164
Slack : 0.947
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.166
Slack : 0.955
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.174
Slack : 0.956
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.175
Slack : 0.956
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.175
Slack : 0.956
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.175
Slack : 0.957
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.176
Slack : 0.958
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.177
Slack : 0.958
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.177
Slack : 0.959
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.177
Slack : 0.960
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.178
Slack : 0.961
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.179
Slack : 0.961
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.179
Slack : 0.962
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.180
Slack : 0.963
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.181
Slack : 0.964
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.182
Slack : 0.970
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.189
Slack : 0.971
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.190
Slack : 0.971
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.190
Slack : 0.972
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.191
Slack : 0.973
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.192
Slack : 0.973
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.192
Slack : 0.973
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.192
Slack : 0.973
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.192
Slack : 0.975
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.194
Slack : 0.975
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.194
Slack : 0.990
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.209
Slack : 0.997
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.215
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -6.225
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.343
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 4.344
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 4.342
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.341
Slack : -6.223
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 4.340
Slack : -5.985
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 4.076
Slack : -5.971
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.195
Data Delay : 4.060
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.142
Data Delay : 3.944
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.924
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.922
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.706
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.155
Data Delay : 3.930
Slack : -5.397
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.149
Data Delay : 3.922
Slack : -5.384
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.167
Data Delay : 3.930
Slack : -5.380
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.177
Data Delay : 3.936
Slack : -5.372
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.173
Data Delay : 3.924
Slack : -5.372
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.173
Data Delay : 3.924
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.197
Data Delay : 3.932
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.919
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.919
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.919
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.196
Data Delay : 3.931
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.923
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.923
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.923
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.923
Slack : -5.356
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.923
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.185
Data Delay : 3.919
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.185
Data Delay : 3.919
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.184
Data Delay : 3.918
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.924
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.924
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.924
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.924
Slack : -5.355
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.924
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.203
Data Delay : 3.924
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.203
Data Delay : 3.924
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.203
Data Delay : 3.924
Slack : -5.342
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.203
Data Delay : 3.924
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.559
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.559
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.559
Slack : 3.696
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.622
Data Delay : 3.559
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.557
Slack : 3.703
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.557
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.553
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.553
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.603
Data Delay : 3.552
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.559
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.559
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.559
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.559
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.559
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.616
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.712
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.615
Data Delay : 3.568
Slack : 3.727
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.591
Data Delay : 3.559
Slack : 3.727
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.591
Data Delay : 3.559
Slack : 3.736
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.596
Data Delay : 3.573
Slack : 3.741
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.585
Data Delay : 3.567
Slack : 3.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.567
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.559
Slack : 4.075
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.557
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.076
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.263
Data Delay : 3.580
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.077
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.249
Data Delay : 3.567
Slack : 4.294
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.190
Data Delay : 3.669
Slack : 4.309
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.192
Data Delay : 3.686
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.225
Data Delay : 3.926
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 3.924
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.923
Slack : 4.520
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 3.922
Slack : 4.522
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.925
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.752
Actual Width : 4.968
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.755
Actual Width : 4.971
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.836
Actual Width : 4.991
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.837
Actual Width : 4.992
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.844
Actual Width : 5.028
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.844
Actual Width : 5.028
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.844
Actual Width : 5.028
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.844
Actual Width : 5.028
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.844
Actual Width : 5.028
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.846
Actual Width : 5.030
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.847
Actual Width : 5.031
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.601
Actual Width : 19.831
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.604
Actual Width : 20.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.607
Actual Width : 20.823
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.608
Actual Width : 20.824
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.660
Actual Width : 20.876
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.686
Actual Width : 20.870
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.686
Actual Width : 20.870
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.686
Actual Width : 20.870
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.686
Actual Width : 20.870
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.689
Actual Width : 20.873
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.512
Fall : 1.781
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.245
Fall : 3.515
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.263
Fall : 1.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.820
Fall : 3.101
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.077
Fall : -1.324
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.311
Fall : -2.564
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.397
Fall : -0.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.397
Fall : -0.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.644
Fall : -0.873
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.977
Fall : -1.214
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.793
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 9.931
Fall : 9.913
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.959
Fall : 10.101
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 9.579
Fall : 9.547
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 10.004
Fall : 10.080
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.661
Fall : 10.706
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 10.516
Fall : 10.623
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 10.720
Fall : 10.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 10.793
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.560
Fall : 10.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.028
Fall : 10.042
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.968
Fall : 10.109
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.866
Fall : 9.872
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.785
Fall : 9.851
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 10.384
Fall : 10.396
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 10.128
Fall : 10.166
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 10.560
Fall : 10.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 10.152
Fall : 10.092
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.419
Fall : 3.334
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.411
Fall : 6.384
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.780
Fall : 5.845
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.176
Fall : 6.240
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.956
Fall : 5.950
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.111
Fall : 6.220
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.151
Fall : 6.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.145
Fall : 6.180
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.074
Fall : 6.119
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.150
Fall : 6.186
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 6.401
Fall : 6.369
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 6.411
Fall : 6.384
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.985
Fall : 5.938
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.985
Fall : 5.938
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 6.305
Fall : 6.309
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 6.005
Fall : 5.971
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.268
Fall : 8.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.040
Fall : 8.140
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.800
Fall : 7.856
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.312
Fall : 7.306
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.984
Fall : 8.035
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.683
Fall : 7.767
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.090
Fall : 8.178
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.141
Fall : 8.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 8.268
Fall : 8.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.137
Fall : 8.269
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.137
Fall : 8.269
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.809
Fall : 7.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.599
Fall : 7.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.765
Fall : 7.806
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.406
Fall : 7.457
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.702
Fall : 7.721
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.981
Fall : 8.036
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.627
Fall : 7.634
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.089
Fall : 7.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.089
Fall : 7.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.289
Fall : 6.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.465
Fall : 6.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.666
Fall : 6.710
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.731
Fall : 6.659
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.731
Fall : 6.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.730
Fall : 6.659
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.646
Fall : 6.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.632
Fall : 6.539
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.755
Fall : 6.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.714
Fall : 6.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.755
Fall : 6.698
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.322
Fall : 6.341
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.698
Fall : 6.778
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.068
Fall : 8.062
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.089
Fall : 8.099
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 8.228
Fall : 8.251
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.101
Fall : 8.062
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 8.451
Fall : 8.514
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 8.068
Fall : 8.141
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.897
Fall : 9.033
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.748
Fall : 8.814
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.005
Fall : 8.991
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.797
Fall : 7.838
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.183
Fall : 8.224
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.236
Fall : 8.257
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.380
Fall : 8.378
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.245
Fall : 8.300
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.797
Fall : 7.838
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.561
Fall : 8.633
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.591
Fall : 8.667
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.392
Fall : 8.326
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.900
Fall : 2.813
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.901
Fall : 2.814
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.876
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.004
Fall : 2.919
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.998
Fall : 2.913
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.874
Fall : 2.792
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.898
Fall : 2.811
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.899
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.779
Fall : 4.767
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.192
Fall : 5.251
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.572
Fall : 5.630
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.361
Fall : 5.349
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.506
Fall : 5.608
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.551
Fall : 5.625
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.543
Fall : 5.574
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.416
Fall : 5.449
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.547
Fall : 5.576
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.179
Fall : 5.181
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.188
Fall : 5.195
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.779
Fall : 4.767
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.779
Fall : 4.767
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.086
Fall : 5.123
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.786
Fall : 4.772
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.786
Fall : 4.772
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.801
Fall : 4.801
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.897
Fall : 2.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.996
Fall : 2.911
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.003
Fall : 2.918
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.164
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.093
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.901
Fall : 5.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.979
Fall : 6.964
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.644
Fall : 6.692
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 6.371
Fall : 6.434
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.901
Fall : 5.952
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.705
Fall : 6.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.846
Fall : 6.936
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.290
Fall : 6.333
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.894
Fall : 6.938
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.695
Fall : 5.738
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.073
Fall : 7.089
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.652
Fall : 6.698
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.650
Fall : 6.750
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.695
Fall : 5.738
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.434
Fall : 6.468
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.510
Fall : 6.536
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.133
Fall : 6.186
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.281
Fall : 6.273
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.926
Fall : 3.804
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.792
Fall : 5.405
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.926
Fall : 3.804
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.153
Fall : 4.026
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.346
Fall : 4.263
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 4.034
Fall : 3.919
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 4.129
Fall : 4.032
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 4.129
Fall : 4.035
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.048
Fall : 3.934
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.034
Fall : 3.919
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.461
Fall : 2.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.998
Fall : 3.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.374
Fall : 4.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.524
Fall : 4.485
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.998
Fall : 3.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 4.359
Fall : 4.312
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.457
Fall : 2.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.456
Fall : 2.369
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.479
Fall : 4.115
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.458
Fall : 2.371
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.551
Fall : 2.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.628
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.977
RF :
FR :
FF : 7.192
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.783
RF :
FR :
FF : 7.007
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.317
RF :
FR :
FF : 4.516
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.491
RF :
FR :
FF : 4.559
Input Port : SW[2]
Output Port : LED[2]
RR : 3.930
RF :
FR :
FF : 4.081
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.742
RF :
FR :
FF : 6.952
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.553
RF :
FR :
FF : 6.773
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.185
RF :
FR :
FF : 4.382
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.940
Fall : 5.807
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.085
Fall : 5.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.085
Fall : 5.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.943
Fall : 5.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.155
Fall : 6.035
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.974
Fall : 5.852
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 5.846
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 5.846
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.940
Fall : 5.807
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.744
Fall : 4.611
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.911
Fall : 4.789
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.911
Fall : 4.789
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.747
Fall : 4.614
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.974
Fall : 4.854
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.804
Fall : 4.682
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.798
Fall : 4.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.798
Fall : 4.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.744
Fall : 4.611
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 5.939
1 to Hi-Z : 6.072
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 6.066
1 to Hi-Z : 6.188
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 6.066
1 to Hi-Z : 6.188
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.942
1 to Hi-Z : 6.075
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 6.198
1 to Hi-Z : 6.318
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.966
1 to Hi-Z : 6.088
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 5.953
1 to Hi-Z : 6.075
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 5.953
1 to Hi-Z : 6.075
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.939
1 to Hi-Z : 6.072
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.708
1 to Hi-Z : 4.841
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 4.859
1 to Hi-Z : 4.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 4.859
1 to Hi-Z : 4.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.711
1 to Hi-Z : 4.844
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.981
1 to Hi-Z : 5.101
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 4.762
1 to Hi-Z : 4.884
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.750
1 to Hi-Z : 4.872
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.750
1 to Hi-Z : 4.872
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.708
1 to Hi-Z : 4.841
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 50.55 MHz
Restricted Fmax : 50.55 MHz
Clock Name : CLOCK_50
Note :
Fmax : 144.18 MHz
Restricted Fmax : 144.18 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 148.41 MHz
Restricted Fmax : 148.41 MHz
Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 219.83 MHz
Restricted Fmax : 219.83 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 1052.63 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -17.443
End Point TNS : -768.889
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.729
End Point TNS : -260.267
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.426
End Point TNS : -37.694
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.785
End Point TNS : -2.785
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 3.262
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.059
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.298
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.312
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -5.745
End Point TNS : -420.318
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.369
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.746
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.487
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.597
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.589
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.491
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -17.443
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.253
Slack : -17.356
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.166
Slack : -17.341
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.894
Slack : -17.318
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.128
Slack : -17.269
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.079
Slack : -17.266
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.824
Slack : -17.250
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.816
Slack : -17.244
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.054
Slack : -17.237
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.790
Slack : -17.231
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.041
Slack : -17.215
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 7.025
Slack : -17.214
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.764
Slack : -17.203
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.525
Data Delay : 6.752
Slack : -17.187
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.997
Slack : -17.182
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.975
Slack : -17.179
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.730
Slack : -17.166
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.722
Slack : -17.165
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.975
Slack : -17.163
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.721
Slack : -17.163
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.721
Slack : -17.151
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.944
Slack : -17.146
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.712
Slack : -17.141
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.951
Slack : -17.137
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.695
Slack : -17.131
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.681
Slack : -17.127
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.937
Slack : -17.111
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.661
Slack : -17.098
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.890
Slack : -17.059
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.617
Slack : -17.057
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.610
Slack : -17.053
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.611
Slack : -17.052
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.604
Slack : -17.033
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.591
Slack : -17.023
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.816
Slack : -17.014
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.565
Slack : -17.014
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.806
Slack : -16.988
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.538
Slack : -16.985
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.795
Slack : -16.969
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.779
Slack : -16.966
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.525
Data Delay : 6.515
Slack : -16.964
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.286
Data Delay : 6.752
Slack : -16.952
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.505
Slack : -16.950
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.760
Slack : -16.932
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.519
Data Delay : 6.487
Slack : -16.930
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.723
Slack : -16.930
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.723
Slack : -16.929
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.485
Slack : -16.916
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.709
Slack : -16.911
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.462
Slack : -16.909
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.459
Slack : -16.892
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.702
Slack : -16.887
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.447
Slack : -16.877
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.669
Slack : -16.867
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.677
Slack : -16.866
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.676
Slack : -16.855
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.647
Slack : -16.851
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.401
Slack : -16.850
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.660
Slack : -16.850
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.642
Slack : -16.849
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.642
Slack : -16.829
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.519
Data Delay : 6.384
Slack : -16.821
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.286
Data Delay : 6.609
Slack : -16.820
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.373
Slack : -16.813
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.623
Slack : -16.812
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.371
Slack : -16.809
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.286
Data Delay : 6.597
Slack : -16.808
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.361
Slack : -16.805
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.597
Slack : -16.805
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.615
Slack : -16.799
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 6.364
Slack : -16.796
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.606
Slack : -16.789
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.599
Slack : -16.781
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.281
Data Delay : 6.574
Slack : -16.780
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.572
Slack : -16.765
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.327
Slack : -16.759
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.282
Data Delay : 6.551
Slack : -16.744
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.304
Slack : -16.738
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.296
Slack : -16.726
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.536
Slack : -16.722
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.280
Slack : -16.715
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.268
Slack : -16.713
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.277
Slack : -16.700
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.252
Slack : -16.697
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.261
Slack : -16.694
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.252
Slack : -16.687
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.283
Data Delay : 6.478
Slack : -16.672
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.232
Slack : -16.671
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.229
Slack : -16.666
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.476
Slack : -16.662
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.472
Slack : -16.655
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.213
Slack : -16.645
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.203
Slack : -16.616
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 6.181
Slack : -16.598
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.286
Data Delay : 6.386
Slack : -16.598
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 6.163
Slack : -16.583
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.142
Slack : -16.576
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.386
Slack : -16.567
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.377
Slack : -16.565
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.126
Slack : -16.563
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.124
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.729
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 4.808
Slack : -6.702
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.793
Slack : -6.669
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.746
Data Delay : 5.023
Slack : -6.543
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.005
Data Delay : 4.638
Slack : -6.538
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.634
Slack : -6.520
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.611
Slack : -6.517
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.608
Slack : -6.505
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.595
Slack : -6.488
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.575
Slack : -6.487
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.571
Slack : -6.475
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.566
Slack : -6.461
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.560
Slack : -6.460
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.556
Slack : -6.441
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.015
Data Delay : 4.526
Slack : -6.428
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.738
Data Delay : 4.790
Slack : -6.427
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.741
Data Delay : 4.786
Slack : -6.414
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.511
Slack : -6.381
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.740
Data Delay : 4.741
Slack : -6.366
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.007
Data Delay : 4.459
Slack : -6.352
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.016
Data Delay : 4.436
Slack : -6.344
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 4.423
Slack : -6.322
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.010
Data Delay : 4.412
Slack : -6.291
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.002
Data Delay : 4.389
Slack : -6.284
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.384
Slack : -6.273
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.980
Data Delay : 4.393
Slack : -6.259
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.383
Slack : -6.246
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.995
Data Delay : 4.351
Slack : -6.238
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.338
Slack : -6.230
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.355
Slack : -6.230
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 4.337
Slack : -6.229
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.983
Data Delay : 4.346
Slack : -6.225
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.992
Data Delay : 4.333
Slack : -6.220
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 4.349
Slack : -6.216
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.356
Slack : -6.215
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.028
Data Delay : 4.287
Slack : -6.213
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.353
Slack : -6.201
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.961
Data Delay : 4.340
Slack : -6.186
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.996
Data Delay : 4.290
Slack : -6.171
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 4.311
Slack : -6.131
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 4.258
Slack : -6.109
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.007
Data Delay : 4.202
Slack : -6.101
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.201
Slack : -6.098
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.198
Slack : -6.093
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.189
Slack : -6.086
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 4.185
Slack : -6.072
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.197
Slack : -6.071
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 4.182
Slack : -6.070
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.200
Slack : -6.067
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 4.193
Slack : -6.064
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 4.160
Slack : -6.063
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 4.169
Slack : -6.062
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 4.168
Slack : -6.056
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.156
Slack : -6.055
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.009
Data Delay : 4.146
Slack : -6.050
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.008
Data Delay : 4.142
Slack : -6.043
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 4.174
Slack : -6.000
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 4.123
Slack : -5.999
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.127
Slack : -5.989
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 4.122
Slack : -5.988
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 4.118
Slack : -5.987
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.013
Data Delay : 4.074
Slack : -5.974
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.978
Data Delay : 4.096
Slack : -5.972
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 4.095
Slack : -5.964
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.012
Data Delay : 4.052
Slack : -5.962
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.087
Slack : -5.961
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 4.071
Slack : -5.951
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.011
Data Delay : 4.040
Slack : -5.943
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 4.081
Slack : -5.942
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 4.073
Slack : -5.938
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 4.048
Slack : -5.935
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 4.068
Slack : -5.934
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.069
Slack : -5.931
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 4.065
Slack : -5.926
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.061
Slack : -5.915
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 4.039
Slack : -5.913
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.991
Data Delay : 4.022
Slack : -5.912
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 4.019
Slack : -5.904
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.020
Slack : -5.893
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 3.972
Slack : -5.889
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 4.024
Slack : -5.881
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.983
Data Delay : 3.998
Slack : -5.867
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 3.985
Slack : -5.820
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 3.948
Slack : -5.817
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.001
Data Delay : 3.916
Slack : -5.814
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.999
Data Delay : 3.915
Slack : -5.813
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 3.943
Slack : -5.806
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 3.932
Slack : -5.805
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.932
Slack : -5.804
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.998
Data Delay : 3.906
Slack : -5.803
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.006
Data Delay : 3.897
Slack : -5.796
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.004
Data Delay : 3.892
Slack : -5.790
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.023
Data Delay : 3.867
Slack : -5.787
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 3.887
Slack : -5.786
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 3.917
Slack : -5.771
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.989
Data Delay : 3.882
Slack : -5.770
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 3.904
Slack : -5.767
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.022
Data Delay : 3.845
Slack : -5.761
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.888
Slack : -5.753
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.021
Data Delay : 3.832
Slack : -5.752
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 3.867
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.426
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 2.600
Slack : -3.973
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.211
Data Delay : 2.563
Slack : -3.973
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.211
Data Delay : 2.563
Slack : -3.794
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.402
Slack : -3.794
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.402
Slack : -3.794
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.402
Slack : -3.794
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.402
Slack : -3.794
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.402
Slack : -3.385
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.239
Data Delay : 2.003
Slack : -2.967
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.214
Data Delay : 1.560
Slack : 17.383
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.133
Slack : 17.383
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.133
Slack : 17.383
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.133
Slack : 17.383
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.133
Slack : 17.400
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.116
Slack : 17.400
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.116
Slack : 17.400
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.116
Slack : 17.457
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.059
Slack : 17.457
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 3.059
Slack : 17.491
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.986
Slack : 17.491
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.986
Slack : 17.491
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.986
Slack : 17.491
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.986
Slack : 17.522
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.955
Slack : 17.522
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.955
Slack : 17.522
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.955
Slack : 17.540
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 2.976
Slack : 17.540
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.330
Data Delay : 2.976
Slack : 17.575
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.902
Slack : 17.575
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.902
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.872
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.872
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.872
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.872
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.841
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.841
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.841
Slack : 17.640
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.837
Slack : 17.640
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.837
Slack : 17.689
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.788
Slack : 17.689
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.788
Slack : 17.702
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.775
Slack : 17.702
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.775
Slack : 17.702
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.775
Slack : 17.702
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.775
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.744
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.744
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.744
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.723
Slack : 17.754
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.723
Slack : 17.786
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.691
Slack : 17.786
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.691
Slack : 17.851
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.626
Slack : 17.851
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.626
Slack : 17.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.032
Data Delay : 2.850
Slack : 17.964
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.032
Data Delay : 2.850
Slack : 17.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.014
Data Delay : 2.845
Slack : 17.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.014
Data Delay : 2.845
Slack : 17.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.014
Data Delay : 2.845
Slack : 17.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.014
Data Delay : 2.845
Slack : 17.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.014
Data Delay : 2.845
Slack : 18.061
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.071
Data Delay : 2.714
Slack : 18.061
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.071
Data Delay : 2.714
Slack : 18.070
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.407
Slack : 18.070
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.407
Slack : 18.070
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.407
Slack : 18.070
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.407
Slack : 18.084
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.709
Slack : 18.084
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.709
Slack : 18.084
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.709
Slack : 18.084
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.709
Slack : 18.084
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.709
Slack : 18.097
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.331
Data Delay : 2.418
Slack : 18.097
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.331
Data Delay : 2.418
Slack : 18.097
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.331
Data Delay : 2.418
Slack : 18.101
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.376
Slack : 18.101
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.376
Slack : 18.101
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.376
Slack : 18.154
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.323
Slack : 18.154
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.323
Slack : 18.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.313
Slack : 18.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.313
Slack : 18.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.313
Slack : 18.164
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.313
Slack : 18.175
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.071
Data Delay : 2.600
Slack : 18.175
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.071
Data Delay : 2.600
Slack : 18.194
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.282
Slack : 18.194
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.282
Slack : 18.194
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.282
Slack : 18.195
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.282
Slack : 18.195
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.282
Slack : 18.195
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.282
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.358
Data Delay : 2.200
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.595
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.595
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.595
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.595
Slack : 18.198
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.595
Slack : 18.219
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.258
Slack : 18.219
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.258
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.785
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.254
Data Delay : 1.417
Slack : 70.539
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.876
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 3.262
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 6.269
Slack : 3.437
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 6.092
Slack : 3.567
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.964
Slack : 3.581
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.385
Data Delay : 5.939
Slack : 3.583
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.948
Slack : 3.590
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.941
Slack : 3.619
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.902
Slack : 3.656
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.371
Data Delay : 5.876
Slack : 3.677
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.851
Slack : 3.690
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.838
Slack : 3.742
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 5.787
Slack : 3.758
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 5.771
Slack : 3.765
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 5.764
Slack : 3.812
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.719
Slack : 3.836
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.692
Slack : 3.886
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.385
Data Delay : 5.634
Slack : 3.902
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.628
Slack : 3.902
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.628
Slack : 3.902
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.385
Data Delay : 5.618
Slack : 3.909
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.385
Data Delay : 5.611
Slack : 3.918
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.087
Data Delay : 5.900
Slack : 3.924
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.597
Slack : 3.938
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.881
Slack : 3.940
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.581
Slack : 3.947
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.574
Slack : 3.961
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.371
Data Delay : 5.571
Slack : 3.972
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.556
Slack : 3.977
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.371
Data Delay : 5.555
Slack : 3.984
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.371
Data Delay : 5.548
Slack : 3.985
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.543
Slack : 4.020
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.508
Slack : 4.027
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.501
Slack : 4.035
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.493
Slack : 4.042
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.486
Slack : 4.082
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.449
Slack : 4.104
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.389
Data Delay : 5.412
Slack : 4.117
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.414
Slack : 4.132
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.381
Slack : 4.133
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.398
Slack : 4.135
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.378
Slack : 4.140
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.391
Slack : 4.141
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.387
Slack : 4.157
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.371
Slack : 4.159
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 5.670
Slack : 4.164
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.364
Slack : 4.166
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.387
Data Delay : 5.352
Slack : 4.178
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.648
Slack : 4.187
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 5.640
Slack : 4.207
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.323
Slack : 4.207
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.323
Slack : 4.223
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.307
Slack : 4.223
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.307
Slack : 4.226
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.602
Slack : 4.226
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.602
Slack : 4.230
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.300
Slack : 4.230
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.373
Data Delay : 5.300
Slack : 4.248
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 5.281
Slack : 4.285
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.087
Data Delay : 5.533
Slack : 4.306
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.086
Data Delay : 5.513
Slack : 4.311
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 5.218
Slack : 4.316
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 5.215
Slack : 4.357
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 5.470
Slack : 4.387
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.385
Data Delay : 5.133
Slack : 4.392
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.440
Slack : 4.399
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.389
Data Delay : 5.117
Slack : 4.401
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.120
Slack : 4.407
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.384
Data Delay : 5.114
Slack : 4.420
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.412
Slack : 4.425
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.407
Slack : 4.427
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.086
Slack : 4.427
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.405
Slack : 4.430
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.083
Slack : 4.437
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.076
Slack : 4.440
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.084
Data Delay : 5.381
Slack : 4.452
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.076
Slack : 4.453
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.060
Slack : 4.456
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.389
Data Delay : 5.060
Slack : 4.459
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.389
Data Delay : 5.057
Slack : 4.460
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.053
Slack : 4.461
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.387
Data Delay : 5.057
Slack : 4.462
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.371
Data Delay : 5.070
Slack : 4.463
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 5.366
Slack : 4.465
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.375
Data Delay : 5.063
Slack : 4.477
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.036
Slack : 4.478
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.083
Data Delay : 5.344
Slack : 4.484
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.392
Data Delay : 5.029
Slack : 4.486
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.346
Slack : 4.516
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.074
Data Delay : 5.313
Slack : 4.518
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.387
Data Delay : 5.000
Slack : 4.519
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.353
Data Delay : 5.123
Slack : 4.521
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.387
Data Delay : 4.997
Slack : 4.540
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.077
Data Delay : 5.286
Slack : 4.560
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.272
Slack : 4.567
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.076
Data Delay : 5.260
Slack : 4.569
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.073
Data Delay : 5.261
Slack : 4.594
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.234
Slack : 4.594
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.075
Data Delay : 5.234
Slack : 4.611
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.071
Data Delay : 5.221
Slack : 4.616
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.374
Data Delay : 4.913
Slack : 4.621
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.372
Data Delay : 4.910
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.059
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.327
Data Delay : 2.659
Slack : 0.194
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.327
Data Delay : 2.794
Slack : 0.473
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.672
Slack : 0.563
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.333
Data Delay : 3.169
Slack : 0.624
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.327
Data Delay : 3.224
Slack : 0.973
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.489
Slack : 0.995
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.075
Data Delay : 3.343
Slack : 0.998
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.517
Slack : 1.008
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.521
Slack : 1.020
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.528
Slack : 1.025
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.528
Slack : 1.030
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.546
Slack : 1.040
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.553
Slack : 1.045
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.554
Slack : 1.054
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.557
Slack : 1.061
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.573
Slack : 1.064
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.567
Slack : 1.064
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.580
Slack : 1.064
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.577
Slack : 1.064
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.075
Data Delay : 3.412
Slack : 1.066
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.579
Slack : 1.068
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.576
Slack : 1.068
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.582
Slack : 1.069
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.588
Slack : 1.071
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.226
Data Delay : 3.570
Slack : 1.075
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.584
Slack : 1.084
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.594
Slack : 1.089
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.601
Slack : 1.090
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.609
Slack : 1.091
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.226
Data Delay : 3.590
Slack : 1.092
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.327
Data Delay : 3.692
Slack : 1.101
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.077
Data Delay : 3.451
Slack : 1.105
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.228
Data Delay : 3.606
Slack : 1.108
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.620
Slack : 1.111
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.624
Slack : 1.112
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.625
Slack : 1.112
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.615
Slack : 1.113
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.625
Slack : 1.115
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.069
Data Delay : 3.457
Slack : 1.115
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.226
Data Delay : 3.614
Slack : 1.116
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.618
Slack : 1.118
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.634
Slack : 1.119
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 3.623
Slack : 1.120
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.633
Slack : 1.120
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.228
Data Delay : 3.621
Slack : 1.120
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.634
Slack : 1.121
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.630
Slack : 1.122
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.635
Slack : 1.122
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.241
Data Delay : 3.636
Slack : 1.122
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.624
Slack : 1.123
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.636
Slack : 1.129
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.639
Slack : 1.129
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.640
Slack : 1.131
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.650
Slack : 1.133
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.635
Slack : 1.133
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.635
Slack : 1.135
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 3.639
Slack : 1.136
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.639
Slack : 1.138
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.075
Data Delay : 3.486
Slack : 1.139
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.652
Slack : 1.140
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.649
Slack : 1.140
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.650
Slack : 1.141
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.661
Slack : 1.144
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.653
Slack : 1.145
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.647
Slack : 1.146
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.658
Slack : 1.146
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.648
Slack : 1.148
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.656
Slack : 1.148
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.228
Data Delay : 3.649
Slack : 1.150
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.660
Slack : 1.152
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.665
Slack : 1.153
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.665
Slack : 1.154
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.227
Data Delay : 3.654
Slack : 1.154
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.657
Slack : 1.154
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.667
Slack : 1.155
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.227
Data Delay : 3.655
Slack : 1.159
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.661
Slack : 1.160
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.680
Slack : 1.162
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.228
Data Delay : 3.663
Slack : 1.162
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.664
Slack : 1.162
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.665
Slack : 1.162
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.675
Slack : 1.164
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.674
Slack : 1.165
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.231
Data Delay : 3.669
Slack : 1.166
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.669
Slack : 1.167
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.071
Data Delay : 3.511
Slack : 1.167
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.677
Slack : 1.172
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.685
Slack : 1.174
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.687
Slack : 1.177
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.229
Data Delay : 3.679
Slack : 1.177
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.690
Slack : 1.177
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.687
Slack : 1.178
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.243
Data Delay : 3.694
Slack : 1.184
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.227
Data Delay : 3.684
Slack : 1.187
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.227
Data Delay : 3.687
Slack : 1.187
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.706
Slack : 1.188
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.230
Data Delay : 3.691
Slack : 1.190
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.315
Data Delay : 3.778
Slack : 1.192
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.226
Data Delay : 3.691
Slack : 1.193
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.238
Data Delay : 3.704
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.495
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.708
Slack : 0.496
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.696
Slack : 0.498
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.698
Slack : 0.504
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 0.705
Slack : 0.604
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.803
Slack : 0.727
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 0.928
Slack : 0.741
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.941
Slack : 0.783
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.983
Slack : 0.783
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 0.988
Slack : 0.805
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 1.019
Slack : 0.889
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.095
Slack : 0.901
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.104
Slack : 0.917
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.123
Slack : 0.980
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.181
Slack : 0.989
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 0.903
Slack : 0.989
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.190
Slack : 0.999
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 0.913
Slack : 1.002
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.203
Slack : 1.013
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.213
Slack : 1.018
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 0.932
Slack : 1.048
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.253
Slack : 1.049
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 0.936
Slack : 1.062
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.259
Data Delay : 0.947
Slack : 1.069
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.259
Data Delay : 0.954
Slack : 1.096
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.296
Slack : 1.112
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 1.316
Slack : 1.113
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.318
Slack : 1.114
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.319
Slack : 1.117
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 1.031
Slack : 1.127
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.332
Slack : 1.133
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.661
Slack : 1.139
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 1.053
Slack : 1.139
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.345
Slack : 1.140
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.346
Slack : 1.140
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.668
Slack : 1.140
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.346
Slack : 1.140
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.346
Slack : 1.152
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 1.066
Slack : 1.160
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.047
Slack : 1.160
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.366
Slack : 1.162
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.049
Slack : 1.166
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.372
Slack : 1.168
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.055
Slack : 1.170
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.057
Slack : 1.185
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.072
Slack : 1.185
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.386
Slack : 1.210
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.416
Slack : 1.211
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.417
Slack : 1.214
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.230
Data Delay : 1.128
Slack : 1.221
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.424
Slack : 1.225
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.431
Slack : 1.226
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.431
Slack : 1.229
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.432
Slack : 1.236
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.442
Slack : 1.239
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.445
Slack : 1.244
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.450
Slack : 1.251
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.457
Slack : 1.261
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.467
Slack : 1.269
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.475
Slack : 1.274
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.480
Slack : 1.276
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.482
Slack : 1.287
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.815
Slack : 1.293
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.499
Slack : 1.294
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.822
Slack : 1.295
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.501
Slack : 1.309
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.514
Slack : 1.321
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.527
Slack : 1.339
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.544
Slack : 1.340
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.546
Slack : 1.360
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.888
Slack : 1.365
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.571
Slack : 1.368
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.258
Data Delay : 1.254
Slack : 1.374
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.060
Data Delay : 1.578
Slack : 1.375
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.258
Data Delay : 1.261
Slack : 1.375
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.578
Slack : 1.378
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.578
Slack : 1.382
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.059
Data Delay : 1.585
Slack : 1.400
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.257
Data Delay : 1.287
Slack : 1.412
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.618
Slack : 1.416
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.617
Slack : 1.420
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.626
Slack : 1.421
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.627
Slack : 1.423
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.623
Slack : 1.424
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.259
Data Delay : 1.309
Slack : 1.429
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.629
Slack : 1.435
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.641
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.518
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.731
Slack : 1.248
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.626
Data Delay : 1.091
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.299
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.511
Slack : 0.299
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.519
Slack : 0.308
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.067
Data Delay : 0.519
Slack : 0.311
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.319
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.323
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.536
Slack : 0.324
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.537
Slack : 0.324
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.537
Slack : 0.325
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.538
Slack : 0.325
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.538
Slack : 0.326
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.539
Slack : 0.326
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.539
Slack : 0.326
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.539
Slack : 0.327
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.540
Slack : 0.336
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.548
Slack : 0.340
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.340
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.353
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.566
Slack : 0.360
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.559
Slack : 0.432
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.631
Slack : 0.480
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.693
Slack : 0.481
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.694
Slack : 0.483
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.696
Slack : 0.483
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.696
Slack : 0.485
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.698
Slack : 0.488
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.701
Slack : 0.488
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.701
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.689
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.703
Slack : 0.498
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.711
Slack : 0.503
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.703
Slack : 0.504
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.704
Slack : 0.509
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.709
Slack : 0.510
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.694
Slack : 0.512
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.712
Slack : 0.513
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.726
Slack : 0.516
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.716
Slack : 0.516
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.729
Slack : 0.521
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.721
Slack : 0.526
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.739
Slack : 0.531
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.744
Slack : 0.532
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.745
Slack : 0.533
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.732
Slack : 0.537
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.737
Slack : 0.542
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.742
Slack : 0.546
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.057
Slack : 0.549
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.762
Slack : 0.554
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.753
Slack : 0.554
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.767
Slack : 0.556
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.755
Slack : 0.596
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.795
Slack : 0.602
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.786
Slack : 0.619
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.803
Slack : 0.630
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.829
Slack : 0.630
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.106
Data Delay : 0.880
Slack : 0.645
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.858
Slack : 0.667
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.866
Slack : 0.668
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.867
Slack : 0.698
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.396
Data Delay : 1.238
Slack : 0.700
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.899
Slack : 0.718
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.367
Data Delay : 1.229
Slack : 0.724
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.912
Slack : 0.732
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.945
Slack : 0.735
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.948
Slack : 0.737
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.950
Slack : 0.744
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.957
Slack : 0.745
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.958
Slack : 0.747
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.947
Slack : 0.748
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.948
Slack : 0.751
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.963
Slack : 0.754
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.954
Slack : 0.754
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.954
Slack : 0.757
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.969
Slack : 0.758
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.971
Slack : 0.759
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.959
Slack : 0.759
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.959
Slack : 0.759
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.959
Slack : 0.759
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.959
Slack : 0.759
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.972
Slack : 0.761
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.961
Slack : 0.763
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.963
Slack : 0.763
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.963
Slack : 0.771
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.984
Slack : 0.772
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.972
Slack : 0.780
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.980
Slack : 0.781
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.994
Slack : 0.781
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.994
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.312
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.320
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.321
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.519
Slack : 0.336
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.535
Slack : 0.374
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.573
Slack : 0.446
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.645
Slack : 0.500
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.500
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.501
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.699
Slack : 0.501
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.699
Slack : 0.502
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.502
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.503
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.702
Slack : 0.504
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.703
Slack : 0.504
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.702
Slack : 0.505
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.704
Slack : 0.505
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.703
Slack : 0.507
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.706
Slack : 0.512
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.710
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.711
Slack : 0.514
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.712
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.714
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.716
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.716
Slack : 0.519
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.718
Slack : 0.627
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.825
Slack : 0.744
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.745
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.944
Slack : 0.746
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.945
Slack : 0.747
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.945
Slack : 0.748
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.946
Slack : 0.748
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.947
Slack : 0.751
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.949
Slack : 0.751
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.950
Slack : 0.752
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.951
Slack : 0.753
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.952
Slack : 0.754
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.953
Slack : 0.756
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.955
Slack : 0.757
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.955
Slack : 0.758
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.956
Slack : 0.758
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.957
Slack : 0.759
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.957
Slack : 0.759
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.958
Slack : 0.760
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.959
Slack : 0.761
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.959
Slack : 0.761
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.959
Slack : 0.761
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.960
Slack : 0.763
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.961
Slack : 0.763
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.961
Slack : 0.764
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.963
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.767
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.965
Slack : 0.769
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.967
Slack : 0.770
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.968
Slack : 0.770
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.968
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.774
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.972
Slack : 0.805
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.003
Slack : 0.833
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.032
Slack : 0.834
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.033
Slack : 0.835
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.034
Slack : 0.837
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.035
Slack : 0.837
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.036
Slack : 0.840
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.039
Slack : 0.841
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.040
Slack : 0.842
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.041
Slack : 0.844
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.042
Slack : 0.846
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.044
Slack : 0.847
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.046
Slack : 0.848
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.047
Slack : 0.848
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.047
Slack : 0.849
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.048
Slack : 0.850
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.048
Slack : 0.850
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.048
Slack : 0.850
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.049
Slack : 0.853
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.051
Slack : 0.855
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.053
Slack : 0.855
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.054
Slack : 0.856
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.055
Slack : 0.857
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.055
Slack : 0.857
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.055
Slack : 0.857
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.056
Slack : 0.858
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.056
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.057
Slack : 0.859
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.057
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.061
Slack : 0.863
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.061
Slack : 0.865
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.063
Slack : 0.866
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.064
Slack : 0.866
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.064
Slack : 0.870
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.068
Slack : 0.870
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.068
Slack : 0.899
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.096
Slack : 0.902
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.101
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -5.745
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.941
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.943
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.941
Slack : -5.744
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.940
Slack : -5.743
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.092
Data Delay : 3.938
Slack : -5.507
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 3.681
Slack : -5.494
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.116
Data Delay : 3.667
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.070
Data Delay : 3.566
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.548
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.257
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.082
Data Delay : 3.554
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.548
Slack : -5.256
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.547
Slack : -4.996
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.176
Data Delay : 3.548
Slack : -4.971
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.204
Data Delay : 3.554
Slack : -4.967
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.214
Data Delay : 3.560
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.211
Data Delay : 3.549
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.211
Data Delay : 3.549
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.548
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.548
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.548
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.548
Slack : -4.959
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.548
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.233
Data Delay : 3.555
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.224
Data Delay : 3.546
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.224
Data Delay : 3.546
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.223
Data Delay : 3.545
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.943
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.554
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.548
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.548
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.548
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.548
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.548
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.239
Data Delay : 3.549
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.239
Data Delay : 3.549
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.239
Data Delay : 3.549
Slack : -4.931
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.239
Data Delay : 3.549
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.611
Data Delay : 3.208
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.611
Data Delay : 3.208
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.611
Data Delay : 3.208
Slack : 3.369
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.611
Data Delay : 3.208
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.601
Data Delay : 3.208
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.601
Data Delay : 3.208
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.601
Data Delay : 3.208
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.601
Data Delay : 3.208
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.601
Data Delay : 3.208
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.595
Data Delay : 3.204
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.595
Data Delay : 3.204
Slack : 3.381
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.203
Slack : 3.382
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.204
Slack : 3.382
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.204
Slack : 3.382
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.594
Data Delay : 3.204
Slack : 3.384
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.605
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.385
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.217
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.206
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.206
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.206
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.206
Slack : 3.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.206
Slack : 3.398
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.582
Data Delay : 3.208
Slack : 3.398
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.582
Data Delay : 3.208
Slack : 3.409
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.585
Data Delay : 3.222
Slack : 3.413
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.575
Data Delay : 3.216
Slack : 3.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.545
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.206
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.270
Data Delay : 3.205
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.709
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.208
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.289
Data Delay : 3.228
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.711
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.277
Data Delay : 3.216
Slack : 3.895
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.226
Data Delay : 3.294
Slack : 3.909
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.227
Data Delay : 3.309
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.254
Data Delay : 3.541
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.252
Data Delay : 3.539
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.251
Data Delay : 3.538
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.537
Slack : 4.120
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.540
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.746
Actual Width : 4.962
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.746
Actual Width : 4.962
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.746
Actual Width : 4.962
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.746
Actual Width : 4.962
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.746
Actual Width : 4.962
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.748
Actual Width : 4.964
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.749
Actual Width : 4.965
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[7]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[0]
Slack : 4.841
Actual Width : 4.996
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.dq_masks[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[2]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.842
Actual Width : 4.997
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.846
Actual Width : 5.001
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.847
Actual Width : 4.997
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.847
Actual Width : 5.002
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
Slack : 4.848
Actual Width : 4.998
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[2]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.849
Actual Width : 4.999
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.850
Actual Width : 5.034
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.851
Actual Width : 5.001
Required Width : 0.150
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.851
Actual Width : 5.035
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.487
Actual Width : 9.717
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.494
Actual Width : 9.724
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.495
Actual Width : 9.725
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.496
Actual Width : 9.726
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.597
Actual Width : 19.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[1]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[2]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[3]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[4]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[5]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[6]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[7]
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[4]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[5]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[7]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[8]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[9]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[9]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[11]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[12]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[3]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[5]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[7]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[8]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[9]
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.606
Actual Width : 19.836
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.606
Actual Width : 19.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.606
Actual Width : 19.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.606
Actual Width : 19.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.606
Actual Width : 19.822
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.589
Actual Width : 20.805
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.593
Actual Width : 20.809
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.602
Actual Width : 20.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.623
Actual Width : 20.807
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.676
Actual Width : 20.892
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.695
Actual Width : 20.845
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.696
Actual Width : 20.846
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.697
Actual Width : 20.852
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.699
Actual Width : 20.883
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.472
Fall : 1.660
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 2.972
Fall : 3.141
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.869
Fall : 1.148
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.869
Fall : 1.148
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.123
Fall : 1.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.505
Fall : 2.790
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.067
Fall : -1.233
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.115
Fall : -2.290
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.321
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.321
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.571
Fall : -0.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.856
Fall : -1.078
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 9.763
Fall : 9.640
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.930
Fall : 8.821
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.018
Fall : 8.987
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 8.648
Fall : 8.561
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 9.083
Fall : 9.048
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 9.570
Fall : 9.500
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 9.433
Fall : 9.450
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 9.653
Fall : 9.560
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 9.763
Fall : 9.640
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.550
Fall : 9.453
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.034
Fall : 8.934
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.034
Fall : 8.981
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.877
Fall : 8.809
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.846
Fall : 8.778
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.369
Fall : 9.285
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.081
Fall : 9.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.550
Fall : 9.453
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.133
Fall : 8.974
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.991
Fall : 2.916
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.992
Fall : 2.917
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.974
Fall : 2.902
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.059
Fall : 2.965
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.053
Fall : 2.959
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.972
Fall : 2.900
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.989
Fall : 2.914
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.990
Fall : 2.915
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.765
Fall : 5.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.237
Fall : 5.209
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.604
Fall : 5.575
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.442
Fall : 5.371
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.592
Fall : 5.600
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.580
Fall : 5.546
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.588
Fall : 5.509
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.504
Fall : 5.454
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.634
Fall : 5.552
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 5.765
Fall : 5.797
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 5.763
Fall : 5.810
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.382
Fall : 5.398
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.382
Fall : 5.398
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 5.685
Fall : 5.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.395
Fall : 5.405
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.395
Fall : 5.405
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 5.355
Fall : 5.389
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.987
Fall : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.050
Fall : 2.956
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.057
Fall : 2.963
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.468
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.400
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.517
Fall : 7.486
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.311
Fall : 7.273
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.043
Fall : 7.020
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 6.657
Fall : 6.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.277
Fall : 7.239
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.944
Fall : 6.961
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 7.318
Fall : 7.306
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.392
Fall : 7.362
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 7.517
Fall : 7.486
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.415
Fall : 7.386
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.415
Fall : 7.386
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.059
Fall : 7.014
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.886
Fall : 6.839
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.040
Fall : 6.969
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.743
Fall : 6.746
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.966
Fall : 6.901
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.289
Fall : 7.255
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.887
Fall : 6.820
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 7.256
Fall : 6.934
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 7.256
Fall : 6.934
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 5.723
Fall : 5.600
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 5.856
Fall : 5.845
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.038
Fall : 6.088
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.121
Fall : 6.026
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.121
Fall : 6.026
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.117
Fall : 6.009
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.037
Fall : 5.922
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.022
Fall : 5.909
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.597
Fall : 2.522
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.166
Fall : 6.135
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.092
Fall : 6.135
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.166
Fall : 6.053
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 5.733
Fall : 5.754
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.077
Fall : 6.107
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.595
Fall : 2.520
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.361
Fall : 3.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.594
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.647
Fall : 2.553
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.648
Fall : 2.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 7.264
Fall : 7.210
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 7.290
Fall : 7.210
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.408
Fall : 7.342
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.326
Fall : 7.234
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.659
Fall : 7.654
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.264
Fall : 7.229
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.016
Fall : 8.020
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 7.890
Fall : 7.849
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 8.166
Fall : 8.046
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.067
Fall : 7.021
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.391
Fall : 7.318
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.423
Fall : 7.336
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.548
Fall : 7.476
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.435
Fall : 7.397
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.067
Fall : 7.021
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.710
Fall : 7.667
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.790
Fall : 7.745
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.562
Fall : 7.409
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.621
Fall : 2.545
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 2.619
Fall : 2.543
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 2.602
Fall : 2.530
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.686
Fall : 2.592
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.681
Fall : 2.587
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 2.600
Fall : 2.528
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 2.618
Fall : 2.542
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 2.620
Fall : 2.544
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.286
Fall : 4.349
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.700
Fall : 4.672
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.053
Fall : 5.022
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.897
Fall : 4.828
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.041
Fall : 5.044
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.032
Fall : 4.997
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.038
Fall : 4.958
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.903
Fall : 4.849
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.081
Fall : 5.001
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 4.678
Fall : 4.739
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 4.677
Fall : 4.752
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 4.311
Fall : 4.357
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 4.311
Fall : 4.357
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 4.602
Fall : 4.681
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 4.323
Fall : 4.363
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 4.323
Fall : 4.363
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 4.286
Fall : 4.349
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 2.617
Fall : 2.541
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.678
Fall : 2.584
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.685
Fall : 2.591
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.091
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.022
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.403
Fall : 5.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 6.348
Fall : 6.243
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.036
Fall : 5.999
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.828
Fall : 5.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.403
Fall : 5.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.103
Fall : 6.053
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.223
Fall : 6.211
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.718
Fall : 5.699
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.300
Fall : 6.260
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.179
Fall : 5.113
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.449
Fall : 6.351
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.051
Fall : 5.993
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.050
Fall : 6.017
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.179
Fall : 5.113
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.906
Fall : 5.845
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.917
Fall : 5.858
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.618
Fall : 5.595
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.696
Fall : 5.623
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.588
Fall : 3.435
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.218
Fall : 4.734
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.588
Fall : 3.435
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.803
Fall : 3.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.978
Fall : 3.865
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.686
Fall : 3.540
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.781
Fall : 3.652
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.779
Fall : 3.634
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.700
Fall : 3.552
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.686
Fall : 3.540
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.241
Fall : 2.165
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.668
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.012
Fall : 3.895
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.141
Fall : 4.046
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.668
Fall : 3.530
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.998
Fall : 3.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.237
Fall : 2.161
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.236
Fall : 2.160
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.005
Fall : 3.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.238
Fall : 2.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.290
Fall : 2.196
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.291
Fall : 2.197
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.171
RF :
FR :
FF : 4.298
Input Port : SW[2]
Output Port : LED[2]
RR : 3.640
RF :
FR :
FF : 3.830
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.345
RF :
FR :
FF : 6.446
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.209
RF :
FR :
FF : 6.310
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.926
RF :
FR :
FF : 4.080
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.036
RF :
FR :
FF : 4.165
Input Port : SW[2]
Output Port : LED[2]
RR : 3.527
RF :
FR :
FF : 3.715
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.118
RF :
FR :
FF : 6.226
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 5.986
RF :
FR :
FF : 6.095
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.795
RF :
FR :
FF : 3.951
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 5.370
Fall : 5.228
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.483
Fall : 5.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.483
Fall : 5.341
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.382
Fall : 5.257
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.574
Fall : 5.463
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 5.374
Fall : 5.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.370
Fall : 5.228
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.370
Fall : 5.228
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.378
Fall : 5.253
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.319
Fall : 4.194
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.453
Fall : 4.311
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.453
Fall : 4.311
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.323
Fall : 4.198
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.536
Fall : 4.425
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.347
Fall : 4.205
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.343
Fall : 4.201
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.343
Fall : 4.201
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.319
Fall : 4.194
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 5.282
1 to Hi-Z : 5.424
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 5.380
1 to Hi-Z : 5.522
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 5.380
1 to Hi-Z : 5.522
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 5.325
1 to Hi-Z : 5.450
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 5.550
1 to Hi-Z : 5.661
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 5.295
1 to Hi-Z : 5.437
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 5.282
1 to Hi-Z : 5.424
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 5.282
1 to Hi-Z : 5.424
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 5.315
1 to Hi-Z : 5.440
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 4.226
1 to Hi-Z : 4.352
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 4.321
1 to Hi-Z : 4.463
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 4.321
1 to Hi-Z : 4.463
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 4.236
1 to Hi-Z : 4.361
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 4.482
1 to Hi-Z : 4.593
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 4.239
1 to Hi-Z : 4.381
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 4.226
1 to Hi-Z : 4.368
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 4.226
1 to Hi-Z : 4.368
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 4.227
1 to Hi-Z : 4.352
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -14.929
End Point TNS : -634.264
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -4.459
End Point TNS : -174.631
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -3.773
End Point TNS : -34.191
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.784
End Point TNS : -2.784
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 5.613
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -0.217
End Point TNS : -0.350
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.177
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.178
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.178
End Point TNS : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.694
End Point TNS : -356.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 2.518
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Slack : 4.784
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 9.208
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.609
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.535
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -14.929
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.977
Slack : -14.904
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.952
Slack : -14.859
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.752
Slack : -14.844
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.904
Slack : -14.835
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.881
Slack : -14.831
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.879
Slack : -14.807
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.867
Slack : -14.791
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.851
Slack : -14.781
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.827
Slack : -14.775
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.823
Slack : -14.766
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.662
Slack : -14.764
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.657
Slack : -14.755
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.658
Slack : -14.751
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.811
Slack : -14.739
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.030
Data Delay : 4.783
Slack : -14.736
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.631
Slack : -14.728
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.027
Data Delay : 4.775
Slack : -14.725
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.615
Slack : -14.717
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.777
Slack : -14.716
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.613
Slack : -14.712
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.760
Slack : -14.708
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.027
Data Delay : 4.755
Slack : -14.707
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.755
Slack : -14.706
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.596
Slack : -14.701
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.749
Slack : -14.697
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.757
Slack : -14.695
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.755
Slack : -14.689
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.585
Slack : -14.682
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.742
Slack : -14.681
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.727
Slack : -14.676
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.186
Data Delay : 4.564
Slack : -14.675
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.030
Data Delay : 4.719
Slack : -14.665
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.030
Data Delay : 4.709
Slack : -14.660
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.563
Slack : -14.658
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.704
Slack : -14.657
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.553
Slack : -14.656
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.716
Slack : -14.656
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.716
Slack : -14.641
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.687
Slack : -14.640
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.688
Slack : -14.633
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.522
Slack : -14.625
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.671
Slack : -14.621
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.518
Slack : -14.616
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.506
Slack : -14.608
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.497
Slack : -14.602
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.662
Slack : -14.594
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : DRAM_DQ[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.490
Slack : -14.593
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.029
Data Delay : 4.638
Slack : -14.592
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.487
Slack : -14.585
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.482
Slack : -14.579
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.468
Slack : -14.578
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : DRAM_DQ[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.471
Slack : -14.573
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.633
Slack : -14.557
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.030
Data Delay : 4.601
Slack : -14.557
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.448
Slack : -14.552
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.612
Slack : -14.550
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.443
Slack : -14.534
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.594
Slack : -14.533
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.593
Slack : -14.532
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.186
Data Delay : 4.420
Slack : -14.525
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : DRAM_DQ[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.416
Slack : -14.506
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.552
Slack : -14.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.388
Slack : -14.491
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : DRAM_DQ[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.381
Slack : -14.491
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.389
Slack : -14.485
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.531
Slack : -14.471
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.531
Slack : -14.470
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.360
Slack : -14.469
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.362
Slack : -14.468
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.514
Slack : -14.467
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.513
Slack : -14.459
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.519
Slack : -14.450
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.510
Slack : -14.441
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.501
Slack : -14.440
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.336
Slack : -14.434
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.170
Data Delay : 4.338
Slack : -14.432
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.492
Slack : -14.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.488
Slack : -14.428
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.488
Slack : -14.409
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.309
Slack : -14.406
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.299
Slack : -14.402
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : DRAM_DQ[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.295
Slack : -14.395
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.292
Slack : -14.394
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.454
Slack : -14.393
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.293
Slack : -14.391
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.451
Slack : -14.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.284
Slack : -14.381
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.272
Slack : -14.375
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.275
Slack : -14.373
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.268
Slack : -14.371
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.266
Slack : -14.361
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.258
Slack : -14.360
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.027
Data Delay : 4.407
Slack : -14.352
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.250
Slack : -14.348
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : DRAM_DQ[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.243
Slack : -14.345
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.405
Slack : -14.342
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : DRAM_DQ[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.173
Data Delay : 4.243
Slack : -14.333
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.224
Slack : -14.330
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.225
Slack : -14.314
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.028
Data Delay : 4.360
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -4.459
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.047
Data Delay : 2.501
Slack : -4.436
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.386
Data Delay : 3.139
Slack : -4.407
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 3.121
Slack : -4.374
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.201
Data Delay : 3.262
Slack : -4.337
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.048
Data Delay : 2.378
Slack : -4.336
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 3.050
Slack : -4.334
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.376
Data Delay : 3.047
Slack : -4.332
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 3.046
Slack : -4.324
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 3.041
Slack : -4.319
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 3.039
Slack : -4.300
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 3.014
Slack : -4.282
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.054
Data Delay : 2.317
Slack : -4.275
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.992
Slack : -4.271
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.051
Data Delay : 2.309
Slack : -4.264
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.380
Data Delay : 2.973
Slack : -4.263
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.969
Slack : -4.259
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.974
Slack : -4.235
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.955
Slack : -4.234
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.372
Data Delay : 2.951
Slack : -4.231
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.381
Data Delay : 2.939
Slack : -4.211
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.944
Slack : -4.208
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.382
Data Delay : 2.915
Slack : -4.202
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.370
Data Delay : 2.921
Slack : -4.202
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.385
Data Delay : 2.906
Slack : -4.202
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.195
Data Delay : 3.096
Slack : -4.201
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.198
Data Delay : 3.092
Slack : -4.195
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.926
Slack : -4.169
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.196
Data Delay : 3.062
Slack : -4.142
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.863
Slack : -4.141
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.868
Slack : -4.137
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.366
Data Delay : 2.860
Slack : -4.127
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.360
Data Delay : 2.856
Slack : -4.126
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.865
Slack : -4.125
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.364
Data Delay : 2.850
Slack : -4.123
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.391
Data Delay : 2.821
Slack : -4.111
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.365
Data Delay : 2.835
Slack : -4.105
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.826
Slack : -4.100
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.841
Slack : -4.095
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.815
Slack : -4.081
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.337
Data Delay : 2.833
Slack : -4.079
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.830
Slack : -4.077
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.337
Data Delay : 2.829
Slack : -4.069
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.790
Slack : -4.066
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.806
Slack : -4.058
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.785
Slack : -4.049
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.775
Slack : -4.045
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.337
Data Delay : 2.797
Slack : -4.043
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.765
Slack : -4.041
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.368
Data Delay : 2.762
Slack : -4.039
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.761
Slack : -4.031
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.353
Data Delay : 2.767
Slack : -4.026
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.741
Slack : -4.014
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.359
Data Delay : 2.744
Slack : -4.013
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.753
Slack : -4.007
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.367
Data Delay : 2.729
Slack : -4.005
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.717
Slack : -4.005
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.742
Slack : -4.000
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.715
Slack : -3.997
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.741
Slack : -3.985
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.725
Slack : -3.983
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.377
Data Delay : 2.695
Slack : -3.981
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.723
Slack : -3.980
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.346
Data Delay : 2.723
Slack : -3.978
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.718
Slack : -3.966
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.375
Data Delay : 2.680
Slack : -3.961
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.359
Data Delay : 2.691
Slack : -3.955
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.374
Data Delay : 2.670
Slack : -3.945
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.677
Slack : -3.942
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.690
Slack : -3.940
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.687
Slack : -3.938
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.686
Slack : -3.936
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.363
Data Delay : 2.662
Slack : -3.936
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.362
Data Delay : 2.663
Slack : -3.935
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.666
Slack : -3.929
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.666
Slack : -3.928
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.662
Slack : -3.923
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.355
Data Delay : 2.657
Slack : -3.917
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.354
Data Delay : 2.652
Slack : -3.912
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.649
Slack : -3.906
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.654
Slack : -3.895
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.600
Slack : -3.894
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.640
Slack : -3.893
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.346
Data Delay : 2.636
Slack : -3.881
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.369
Data Delay : 2.601
Slack : -3.879
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.627
Slack : -3.873
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.618
Slack : -3.870
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.366
Data Delay : 2.593
Slack : -3.861
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.606
Slack : -3.854
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.386
Data Delay : 2.557
Slack : -3.837
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.384
Data Delay : 2.542
Slack : -3.826
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.383
Data Delay : 2.532
Slack : -3.823
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.373
Data Delay : 2.539
Slack : -3.818
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.371
Data Delay : 2.536
Slack : -3.817
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.564
Slack : -3.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.554
Slack : -3.816
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.364
Data Delay : 2.541
Slack : -3.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.554
Slack : -3.812
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.357
Data Delay : 2.544
Slack : -3.811
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.553
Slack : -3.803
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.547
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -3.773
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 1.849
Slack : -3.543
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.047
Data Delay : 1.867
Slack : -3.543
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.047
Data Delay : 1.867
Slack : -3.443
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.775
Slack : -3.443
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.775
Slack : -3.443
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.775
Slack : -3.443
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.775
Slack : -3.443
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.775
Slack : -3.164
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 1.504
Slack : -2.953
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 1.285
Slack : 18.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.915
Slack : 18.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.915
Slack : 18.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.915
Slack : 18.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.915
Slack : 18.681
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.249
Data Delay : 1.908
Slack : 18.681
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.249
Data Delay : 1.908
Slack : 18.681
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.249
Data Delay : 1.908
Slack : 18.720
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.868
Slack : 18.720
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.250
Data Delay : 1.868
Slack : 18.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.828
Slack : 18.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.828
Slack : 18.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.828
Slack : 18.734
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.828
Slack : 18.753
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.810
Slack : 18.753
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.810
Slack : 18.753
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.810
Slack : 18.757
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.249
Data Delay : 1.832
Slack : 18.757
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.249
Data Delay : 1.832
Slack : 18.781
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.781
Slack : 18.781
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.781
Slack : 18.797
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.765
Slack : 18.797
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.765
Slack : 18.797
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.765
Slack : 18.797
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.765
Slack : 18.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.745
Slack : 18.818
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.745
Slack : 18.830
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.733
Slack : 18.830
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.733
Slack : 18.830
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.733
Slack : 18.844
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.718
Slack : 18.844
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.718
Slack : 18.861
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.701
Slack : 18.861
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.701
Slack : 18.861
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.701
Slack : 18.861
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.701
Slack : 18.881
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.682
Slack : 18.881
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.682
Slack : 18.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.669
Slack : 18.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.669
Slack : 18.894
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.669
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.654
Slack : 18.908
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.654
Slack : 18.945
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.618
Slack : 18.945
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.618
Slack : 19.041
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.070
Data Delay : 1.727
Slack : 19.041
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.070
Data Delay : 1.727
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.062
Data Delay : 1.724
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.062
Data Delay : 1.724
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.062
Data Delay : 1.724
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.062
Data Delay : 1.724
Slack : 19.052
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.062
Data Delay : 1.724
Slack : 19.112
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 1.630
Slack : 19.112
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 1.630
Slack : 19.113
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.449
Slack : 19.113
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.449
Slack : 19.113
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.449
Slack : 19.113
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.449
Slack : 19.117
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.446
Slack : 19.117
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.446
Slack : 19.117
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.446
Slack : 19.118
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.468
Slack : 19.118
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.468
Slack : 19.118
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.468
Slack : 19.124
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.626
Slack : 19.124
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.626
Slack : 19.124
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.626
Slack : 19.124
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.626
Slack : 19.124
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.626
Slack : 19.160
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.402
Slack : 19.160
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.402
Slack : 19.165
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.271
Data Delay : 1.355
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.394
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.394
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.394
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.393
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.393
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.393
Slack : 19.169
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.393
Slack : 19.172
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.414
Slack : 19.175
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 1.567
Slack : 19.175
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.096
Data Delay : 1.567
Slack : 19.178
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.408
Slack : 19.180
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.380
Slack : 19.180
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.380
Slack : 19.180
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.380
Slack : 19.186
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.252
Data Delay : 1.400
Slack : 19.187
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.563
Slack : 19.187
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.563
Slack : 19.187
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.563
Slack : 19.187
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.088
Data Delay : 1.563
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.784
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : -0.021
Data Delay : 1.133
Slack : 70.890
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.540
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 5.613
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 4.094
Slack : 5.705
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 4.001
Slack : 5.819
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.888
Slack : 5.826
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.242
Data Delay : 3.872
Slack : 5.827
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.880
Slack : 5.831
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.876
Slack : 5.851
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.848
Slack : 5.911
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.795
Slack : 5.919
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.787
Slack : 5.923
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.783
Slack : 5.928
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.231
Data Delay : 3.780
Slack : 5.987
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.720
Slack : 6.003
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.701
Slack : 6.027
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.677
Slack : 6.032
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.242
Data Delay : 3.666
Slack : 6.034
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.670
Slack : 6.040
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.242
Data Delay : 3.658
Slack : 6.044
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.242
Data Delay : 3.654
Slack : 6.048
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.658
Slack : 6.048
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.658
Slack : 6.057
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.642
Slack : 6.065
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.634
Slack : 6.069
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.630
Slack : 6.072
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.813
Slack : 6.105
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.062
Data Delay : 3.773
Slack : 6.123
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.756
Slack : 6.134
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.231
Data Delay : 3.574
Slack : 6.142
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.231
Data Delay : 3.566
Slack : 6.146
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.231
Data Delay : 3.562
Slack : 6.152
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.555
Slack : 6.178
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.514
Slack : 6.193
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.514
Slack : 6.195
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.690
Slack : 6.201
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.506
Slack : 6.205
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.502
Slack : 6.209
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.495
Slack : 6.217
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.487
Slack : 6.221
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.483
Slack : 6.233
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.471
Slack : 6.240
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.464
Slack : 6.240
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.647
Slack : 6.241
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.463
Slack : 6.244
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.462
Slack : 6.245
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.459
Slack : 6.248
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.456
Slack : 6.252
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.452
Slack : 6.254
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.452
Slack : 6.254
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.452
Slack : 6.254
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.630
Slack : 6.262
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.444
Slack : 6.262
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.444
Slack : 6.265
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.246
Data Delay : 3.429
Slack : 6.266
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.440
Slack : 6.266
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.440
Slack : 6.291
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.595
Slack : 6.291
From Node : sdram_controller:sdram_|r.state[4]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.595
Slack : 6.317
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.375
Slack : 6.319
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.244
Data Delay : 3.377
Slack : 6.346
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.062
Data Delay : 3.532
Slack : 6.355
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.054
Data Delay : 3.530
Slack : 6.364
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.061
Data Delay : 3.515
Slack : 6.365
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.242
Data Delay : 3.333
Slack : 6.366
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.233
Data Delay : 3.340
Slack : 6.371
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.bank[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.234
Data Delay : 3.334
Slack : 6.384
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.308
Slack : 6.390
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.309
Slack : 6.392
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.300
Slack : 6.396
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.state[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.296
Slack : 6.420
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.address[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.241
Data Delay : 3.279
Slack : 6.428
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.462
Slack : 6.428
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.462
Slack : 6.433
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.454
Slack : 6.437
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.453
Slack : 6.447
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.059
Data Delay : 3.434
Slack : 6.461
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.429
Slack : 6.467
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.231
Data Delay : 3.241
Slack : 6.471
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.246
Data Delay : 3.223
Slack : 6.472
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.058
Data Delay : 3.410
Slack : 6.479
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.246
Data Delay : 3.215
Slack : 6.481
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.052
Data Delay : 3.406
Slack : 6.481
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.409
Slack : 6.483
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.246
Data Delay : 3.211
Slack : 6.495
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.055
Data Delay : 3.389
Slack : 6.505
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 3.384
Slack : 6.507
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.185
Slack : 6.515
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.049
Data Delay : 3.375
Slack : 6.520
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.172
Slack : 6.523
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.181
Slack : 6.525
From Node : sdram_controller:sdram_|r.act_row[0]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.244
Data Delay : 3.171
Slack : 6.526
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.232
Data Delay : 3.181
Slack : 6.531
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.dq_masks[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.173
Slack : 6.532
From Node : sdram_controller:sdram_|r.act_row[2]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.217
Data Delay : 3.238
Slack : 6.532
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.354
Slack : 6.532
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.address[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.354
Slack : 6.533
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.244
Data Delay : 3.163
Slack : 6.537
From Node : sdram_controller:sdram_|r.act_row[1]
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.244
Data Delay : 3.159
Slack : 6.539
From Node : sdram_controller:sdram_|r.state[6]
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.053
Data Delay : 3.347
Slack : 6.542
From Node : sdram_controller:sdram_|r.act_row[4]
To Node : sdram_controller:sdram_|r.address[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.235
Data Delay : 3.162
Slack : 6.543
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.address[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.050
Data Delay : 3.346
Slack : 6.548
From Node : sdram_controller:sdram_|r.act_row[3]
To Node : sdram_controller:sdram_|r.address[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 10.000
Clock Skew : -0.248
Data Delay : 3.144
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -0.217
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.574
Data Delay : 1.565
Slack : -0.133
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.576
Data Delay : 1.651
Slack : 0.086
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.580
Data Delay : 1.874
Slack : 0.119
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.577
Data Delay : 1.904
Slack : 0.268
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.388
Slack : 0.376
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.412
Data Delay : 1.996
Slack : 0.395
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.574
Data Delay : 2.177
Slack : 0.410
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.134
Slack : 0.421
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.148
Slack : 0.430
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.414
Data Delay : 2.052
Slack : 0.435
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.156
Slack : 0.443
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.156
Slack : 0.444
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.161
Slack : 0.444
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.171
Slack : 0.445
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.169
Slack : 0.448
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.414
Data Delay : 2.070
Slack : 0.452
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.165
Slack : 0.453
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.177
Slack : 0.455
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.178
Slack : 0.456
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.174
Slack : 0.460
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.184
Slack : 0.460
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.183
Slack : 0.460
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.414
Data Delay : 2.082
Slack : 0.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.408
Data Delay : 2.078
Slack : 0.463
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.184
Slack : 0.465
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.182
Slack : 0.465
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.176
Slack : 0.466
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.193
Slack : 0.466
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.572
Data Delay : 2.246
Slack : 0.477
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.199
Slack : 0.478
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.196
Slack : 0.479
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.202
Slack : 0.479
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.202
Slack : 0.479
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.576
Data Delay : 2.263
Slack : 0.480
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 2.254
Slack : 0.482
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.206
Slack : 0.483
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.410
Data Delay : 2.101
Slack : 0.483
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.206
Slack : 0.483
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.196
Slack : 0.484
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.502
Data Delay : 2.194
Slack : 0.484
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.202
Slack : 0.485
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.502
Data Delay : 2.195
Slack : 0.485
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.210
Slack : 0.486
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.209
Slack : 0.486
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.210
Slack : 0.487
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.565
Data Delay : 2.260
Slack : 0.488
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.572
Data Delay : 2.268
Slack : 0.489
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.200
Slack : 0.490
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.214
Slack : 0.493
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.205
Slack : 0.494
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.217
Slack : 0.494
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.502
Data Delay : 2.204
Slack : 0.495
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.222
Slack : 0.497
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.269
Slack : 0.497
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.211
Slack : 0.497
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.221
Slack : 0.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.411
Data Delay : 2.118
Slack : 0.499
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.218
Slack : 0.500
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.224
Slack : 0.500
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.223
Slack : 0.500
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.221
Slack : 0.500
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.408
Data Delay : 2.116
Slack : 0.502
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.220
Slack : 0.502
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.227
Slack : 0.502
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 2.276
Slack : 0.505
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.217
Slack : 0.505
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.218
Slack : 0.505
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.218
Slack : 0.505
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.218
Slack : 0.505
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.564
Data Delay : 2.277
Slack : 0.506
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.217
Slack : 0.506
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.520
Data Delay : 2.234
Slack : 0.507
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.219
Slack : 0.507
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.410
Data Delay : 2.125
Slack : 0.508
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.220
Slack : 0.508
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.504
Data Delay : 2.220
Slack : 0.508
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.227
Slack : 0.511
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.411
Data Delay : 2.130
Slack : 0.512
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.235
Slack : 0.513
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.224
Slack : 0.514
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.416
Data Delay : 2.138
Slack : 0.515
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.233
Slack : 0.516
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.234
Slack : 0.517
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.240
Slack : 0.518
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.231
Slack : 0.518
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.232
Slack : 0.519
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.520
Data Delay : 2.247
Slack : 0.519
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.420
Data Delay : 2.147
Slack : 0.520
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.422
Data Delay : 2.150
Slack : 0.520
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.233
Slack : 0.521
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.242
Slack : 0.522
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.249
Slack : 0.523
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.236
Slack : 0.525
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.515
Data Delay : 2.248
Slack : 0.526
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.237
Slack : 0.526
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.240
Slack : 0.527
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.503
Data Delay : 2.238
Slack : 0.528
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.411
Data Delay : 2.147
Slack : 0.529
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.242
Slack : 0.530
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.244
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.177
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.436
Slack : 1.186
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.233
Data Delay : 0.576
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.178
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vga_vc[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vga_vc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.282
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.404
Slack : 0.292
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.421
Slack : 0.294
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.295
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.336
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.457
Slack : 0.408
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.530
Slack : 0.443
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.564
Slack : 0.460
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.581
Slack : 0.460
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.585
Slack : 0.461
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.591
Slack : 0.514
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.641
Slack : 0.527
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.653
Slack : 0.531
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.655
Slack : 0.566
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.688
Slack : 0.577
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.526
Slack : 0.580
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.702
Slack : 0.583
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.705
Slack : 0.584
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.533
Slack : 0.591
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.540
Slack : 0.606
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.731
Slack : 0.606
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.727
Slack : 0.616
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.150
Data Delay : 0.550
Slack : 0.642
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.574
Slack : 0.645
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.769
Slack : 0.645
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.577
Slack : 0.648
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.773
Slack : 0.649
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.774
Slack : 0.649
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.968
Slack : 0.654
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.779
Slack : 0.659
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.608
Slack : 0.659
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.780
Slack : 0.663
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.790
Slack : 0.665
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.614
Slack : 0.665
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.792
Slack : 0.669
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.618
Slack : 0.673
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.150
Data Delay : 0.607
Slack : 0.673
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.800
Slack : 0.673
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.800
Slack : 0.676
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.803
Slack : 0.677
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.151
Data Delay : 0.610
Slack : 0.678
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.150
Data Delay : 0.612
Slack : 0.679
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.806
Slack : 0.683
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.150
Data Delay : 0.617
Slack : 0.684
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.806
Slack : 0.687
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.151
Data Delay : 0.620
Slack : 0.701
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.828
Slack : 0.701
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.828
Slack : 0.704
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.236
Data Delay : 1.024
Slack : 0.707
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.830
Slack : 0.711
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.135
Data Delay : 0.660
Slack : 0.727
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.853
Slack : 0.729
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.853
Slack : 0.738
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.865
Slack : 0.739
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.866
Slack : 0.740
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.865
Slack : 0.741
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.868
Slack : 0.742
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.868
Slack : 0.745
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.872
Slack : 0.750
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.236
Data Delay : 1.070
Slack : 0.751
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.878
Slack : 0.755
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.236
Data Delay : 1.075
Slack : 0.755
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.882
Slack : 0.756
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.883
Slack : 0.759
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.886
Slack : 0.761
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.888
Slack : 0.764
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.891
Slack : 0.790
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.914
Slack : 0.791
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.236
Data Delay : 1.111
Slack : 0.802
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.151
Data Delay : 0.735
Slack : 0.804
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.931
Slack : 0.808
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.929
Slack : 0.808
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.932
Slack : 0.809
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.041
Data Delay : 0.934
Slack : 0.810
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.151
Data Delay : 0.743
Slack : 0.813
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.151
Data Delay : 0.746
Slack : 0.813
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.040
Data Delay : 0.937
Slack : 0.816
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.937
Slack : 0.821
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.942
Slack : 0.822
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.949
Slack : 0.827
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.954
Slack : 0.832
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.958
Slack : 0.832
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.042
Data Delay : 0.958
Slack : 0.832
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.959
Slack : 0.832
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.959
Slack : 0.835
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.957
Slack : 0.842
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.043
Data Delay : 0.969
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.178
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.178
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.179
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.313
Slack : 0.184
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.313
Slack : 0.184
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.315
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.317
Slack : 0.187
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.316
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.199
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.327
Slack : 0.204
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.333
Slack : 0.217
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.337
Slack : 0.254
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.375
Slack : 0.277
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.397
Slack : 0.281
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.394
Slack : 0.284
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.413
Slack : 0.285
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.414
Slack : 0.287
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.416
Slack : 0.288
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.417
Slack : 0.288
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.417
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.419
Slack : 0.288
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.419
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.420
Slack : 0.296
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.425
Slack : 0.298
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.300
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.305
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.306
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.435
Slack : 0.307
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.428
Slack : 0.308
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.437
Slack : 0.310
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.431
Slack : 0.310
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.226
Data Delay : 0.620
Slack : 0.316
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.444
Slack : 0.317
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.437
Slack : 0.319
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.447
Slack : 0.321
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.441
Slack : 0.323
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.451
Slack : 0.325
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.446
Slack : 0.327
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.448
Slack : 0.332
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.452
Slack : 0.333
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.461
Slack : 0.334
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.455
Slack : 0.340
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.469
Slack : 0.354
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.072
Data Delay : 0.510
Slack : 0.362
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.482
Slack : 0.367
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.498
Slack : 0.368
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.028
Data Delay : 0.480
Slack : 0.379
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.500
Slack : 0.382
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.028
Data Delay : 0.494
Slack : 0.391
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.511
Slack : 0.396
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.243
Data Delay : 0.723
Slack : 0.408
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.528
Slack : 0.410
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.226
Data Delay : 0.720
Slack : 0.429
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.029
Data Delay : 0.542
Slack : 0.437
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.568
Slack : 0.438
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.569
Slack : 0.440
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.563
Slack : 0.442
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.563
Slack : 0.444
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.573
Slack : 0.444
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.567
Slack : 0.444
From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.573
Slack : 0.446
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.577
Slack : 0.447
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.571
Slack : 0.448
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.569
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.577
Slack : 0.449
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.580
Slack : 0.450
From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.579
Slack : 0.450
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.573
Slack : 0.450
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.573
Slack : 0.454
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.039
Data Delay : 0.577
Slack : 0.454
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.575
Slack : 0.454
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.575
Slack : 0.456
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.584
Slack : 0.457
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.460
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.589
Slack : 0.460
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.581
Slack : 0.465
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.044
Data Delay : 0.593
Slack : 0.466
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.398
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.rf_pending
To Node : sdram_controller:sdram_|r.rf_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : sdram_controller:sdram_|r.wr_pending
To Node : sdram_controller:sdram_|r.wr_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.193
From Node : sdram_controller:sdram_|r.rd_pending
To Node : sdram_controller:sdram_|r.rd_pending
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.197
From Node : sdram_controller:sdram_|r.rf_counter[9]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.318
Slack : 0.227
From Node : sdram_controller:sdram_|r.state[5]
To Node : sdram_controller:sdram_|r.state[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.348
Slack : 0.270
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.391
Slack : 0.295
From Node : sdram_controller:sdram_|r.init_counter[14]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.297
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.297
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.297
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.418
Slack : 0.298
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.299
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.300
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.304
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.425
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.305
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.426
Slack : 0.306
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.306
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.307
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.428
Slack : 0.308
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[0]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.429
Slack : 0.357
From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.478
Slack : 0.445
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.state[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.566
Slack : 0.446
From Node : sdram_controller:sdram_|r.init_counter[13]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.446
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.567
Slack : 0.447
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.447
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.568
Slack : 0.448
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.569
Slack : 0.453
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.574
Slack : 0.454
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.575
Slack : 0.454
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.575
Slack : 0.455
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.455
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.456
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.456
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.577
Slack : 0.457
From Node : sdram_controller:sdram_|r.rf_counter[8]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.457
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.578
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.579
Slack : 0.458
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[2]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.579
Slack : 0.459
From Node : sdram_controller:sdram_|r.init_counter[12]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.580
Slack : 0.459
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.580
Slack : 0.460
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.581
Slack : 0.461
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.582
Slack : 0.463
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.584
Slack : 0.463
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.584
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.585
Slack : 0.464
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.585
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.466
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.587
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.588
Slack : 0.467
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.588
Slack : 0.475
From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.596
Slack : 0.508
From Node : sdram_controller:sdram_|r.state[8]
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.629
Slack : 0.509
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.630
Slack : 0.509
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.630
Slack : 0.510
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.631
Slack : 0.510
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.631
Slack : 0.511
From Node : sdram_controller:sdram_|r.rf_counter[7]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.632
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[1]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.633
Slack : 0.512
From Node : sdram_controller:sdram_|r.rf_counter[3]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.633
Slack : 0.513
From Node : sdram_controller:sdram_|r.init_counter[11]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.634
Slack : 0.513
From Node : sdram_controller:sdram_|r.rf_counter[5]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.634
Slack : 0.516
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.637
Slack : 0.516
From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.637
Slack : 0.517
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.638
Slack : 0.518
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.639
Slack : 0.519
From Node : sdram_controller:sdram_|r.init_counter[5]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.640
Slack : 0.520
From Node : sdram_controller:sdram_|r.init_counter[1]
To Node : sdram_controller:sdram_|r.init_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.641
Slack : 0.520
From Node : sdram_controller:sdram_|r.init_counter[7]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.641
Slack : 0.521
From Node : sdram_controller:sdram_|r.init_counter[9]
To Node : sdram_controller:sdram_|r.init_counter[12]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.642
Slack : 0.521
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[3]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.642
Slack : 0.522
From Node : sdram_controller:sdram_|r.rf_counter[6]
To Node : sdram_controller:sdram_|r.rf_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.643
Slack : 0.523
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.644
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.645
Slack : 0.524
From Node : sdram_controller:sdram_|r.rf_counter[0]
To Node : sdram_controller:sdram_|r.rf_counter[4]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.645
Slack : 0.526
From Node : sdram_controller:sdram_|r.rf_counter[2]
To Node : sdram_controller:sdram_|r.rf_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.647
Slack : 0.527
From Node : sdram_controller:sdram_|r.rf_counter[4]
To Node : sdram_controller:sdram_|r.rf_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.648
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[5]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[13]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.529
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[7]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.650
Slack : 0.530
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[9]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.651
Slack : 0.530
From Node : sdram_controller:sdram_|r.init_counter[8]
To Node : sdram_controller:sdram_|r.init_counter[11]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.651
Slack : 0.531
From Node : sdram_controller:sdram_|r.state[7]
To Node : sdram_controller:sdram_|r.state[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.652
Slack : 0.531
From Node : sdram_controller:sdram_|r.init_counter[0]
To Node : sdram_controller:sdram_|r.init_counter[1]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.652
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[2]
To Node : sdram_controller:sdram_|r.init_counter[6]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[10]
To Node : sdram_controller:sdram_|r.init_counter[14]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
Slack : 0.532
From Node : sdram_controller:sdram_|r.init_counter[4]
To Node : sdram_controller:sdram_|r.init_counter[8]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.653
Slack : 0.533
From Node : sdram_controller:sdram_|r.init_counter[6]
To Node : sdram_controller:sdram_|r.init_counter[10]
Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.654
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.694
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.789
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.791
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.789
Slack : -4.693
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.230
Data Delay : 2.786
Slack : -4.692
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.789
Slack : -4.583
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 2.659
Slack : -4.575
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.251
Data Delay : 2.648
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.213
Data Delay : 2.588
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.572
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.574
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.430
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.580
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.574
Slack : -4.429
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.571
Slack : -4.256
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.047
Data Delay : 2.580
Slack : -4.254
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.586
Slack : -4.250
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.047
Data Delay : 2.574
Slack : -4.250
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.047
Data Delay : 2.574
Slack : -4.242
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.574
Slack : -4.242
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.574
Slack : -4.242
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.574
Slack : -4.242
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.574
Slack : -4.242
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.574
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 2.581
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.038
Data Delay : 2.574
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.573
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.038
Data Delay : 2.574
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.038
Data Delay : 2.574
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.573
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.573
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.039
Data Delay : 2.573
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.241
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.032
Data Delay : 2.580
Slack : -4.240
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.037
Data Delay : 2.574
Slack : -4.240
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.037
Data Delay : 2.574
Slack : -4.234
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 2.574
Slack : -4.234
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 2.574
Slack : -4.234
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 2.574
Slack : -4.234
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.031
Data Delay : 2.574
Slack : -4.227
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : -0.023
Data Delay : 2.572
Slack : -4.202
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.572
Slack : -4.202
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.572
Slack : -4.202
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.572
Slack : -4.202
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.572
Slack : -4.202
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.572
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.946
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.946
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.946
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.946
Slack : 2.518
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.946
Slack : 2.544
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.231
Data Delay : 1.946
Slack : 2.557
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 1.947
Slack : 2.557
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 1.947
Slack : 2.557
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 1.947
Slack : 2.557
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 1.947
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.214
Data Delay : 1.945
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.214
Data Delay : 1.945
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.214
Data Delay : 1.945
Slack : 2.563
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.214
Data Delay : 1.945
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.947
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.947
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.947
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.947
Slack : 2.564
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.947
Slack : 2.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.947
Slack : 2.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.947
Slack : 2.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.947
Slack : 2.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.947
Slack : 2.566
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.947
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 1.957
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.567
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 1.956
Slack : 2.574
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.205
Data Delay : 1.947
Slack : 2.574
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.205
Data Delay : 1.947
Slack : 2.579
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.214
Data Delay : 1.961
Slack : 2.582
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.205
Data Delay : 1.955
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.761
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.947
Slack : 2.762
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.032
Data Delay : 1.963
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.015
Data Delay : 1.946
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.763
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.024
Data Delay : 1.955
Slack : 2.897
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.019
Data Delay : 2.020
Slack : 2.902
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.016
Data Delay : 2.028
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.009
Data Delay : 2.157
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.155
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.155
Slack : 3.008
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.004
Data Delay : 2.152
Slack : 3.011
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.005
Data Delay : 2.156
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.784
Actual Width : 5.000
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.785
Actual Width : 5.001
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.796
Actual Width : 4.980
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.796
Actual Width : 4.980
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.796
Actual Width : 4.980
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.796
Actual Width : 4.980
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.796
Actual Width : 4.980
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.801
Actual Width : 5.017
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[0]
Slack : 4.801
Actual Width : 5.017
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[1]
Slack : 4.801
Actual Width : 5.017
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[2]
Slack : 4.801
Actual Width : 5.017
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[3]
Slack : 4.801
Actual Width : 5.017
Required Width : 0.216
Type : High Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.act_row[4]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[0]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[3]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[0]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[1]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[2]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[3]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[4]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[5]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[6]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[7]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[8]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_counter[9]
Slack : 4.813
Actual Width : 4.997
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rf_pending
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[10]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[11]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[12]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[13]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[14]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[1]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[2]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[4]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[5]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[6]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[7]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[8]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.init_counter[9]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.rd_pending
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[4]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[5]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[6]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[7]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[8]
Slack : 4.814
Actual Width : 4.998
Required Width : 0.184
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.wr_pending
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[0]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[10]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[9]
Slack : 4.817
Actual Width : 4.972
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[0]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[11]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[3]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[6]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.address[8]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[0]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.bank[1]
Slack : 4.818
Actual Width : 4.973
Required Width : 0.155
Type : Low Pulse Width
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : sdram_controller:sdram_|r.state[1]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.610
Actual Width : 20.826
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.636
Actual Width : 20.852
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.642
Actual Width : 20.826
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.643
Actual Width : 20.827
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.644
Actual Width : 20.828
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.644
Actual Width : 20.828
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.644
Actual Width : 20.828
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.644
Actual Width : 20.828
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.647
Actual Width : 20.831
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.649
Actual Width : 20.865
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.649
Actual Width : 20.865
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.650
Actual Width : 20.866
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.650
Actual Width : 20.834
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.652
Actual Width : 20.868
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.656
Actual Width : 20.872
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.657
Actual Width : 20.873
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 0.740
Fall : 1.482
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.804
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.623
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.623
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 0.719
Fall : 1.317
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.573
Fall : 2.137
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.493
Fall : -1.222
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.255
Fall : -1.937
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.358
Fall : -0.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.536
Fall : -1.090
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.313
Fall : 6.460
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.793
Fall : 5.876
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 5.759
Fall : 6.041
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.594
Fall : 5.678
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 5.806
Fall : 5.971
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.201
Fall : 6.318
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.089
Fall : 6.240
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.227
Fall : 6.385
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.313
Fall : 6.460
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 6.125
Fall : 6.276
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.865
Fall : 5.971
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.734
Fall : 6.023
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.802
Fall : 5.888
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.700
Fall : 5.827
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.047
Fall : 6.179
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.913
Fall : 6.016
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.125
Fall : 6.276
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.968
Fall : 6.044
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 2.000
Fall : 1.945
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 2.001
Fall : 1.946
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.979
Fall : 1.928
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 2.060
Fall : 1.988
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 2.052
Fall : 1.980
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 2.055
Fall : 1.983
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.977
Fall : 1.926
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.998
Fall : 1.943
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.999
Fall : 1.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 2.053
Fall : 1.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.820
Fall : 3.760
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.349
Fall : 3.460
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.570
Fall : 3.712
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.422
Fall : 3.554
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.576
Fall : 3.760
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.576
Fall : 3.720
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.545
Fall : 3.681
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.508
Fall : 3.637
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.734
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 3.818
Fall : 3.711
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 3.820
Fall : 3.713
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 3.557
Fall : 3.474
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 3.557
Fall : 3.474
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 3.745
Fall : 3.658
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 3.565
Fall : 3.478
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 3.565
Fall : 3.478
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 3.554
Fall : 3.493
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.997
Fall : 1.942
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 2.053
Fall : 1.981
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 2.057
Fall : 1.985
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.958
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.905
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.782
Fall : 4.918
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.665
Fall : 4.838
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.507
Fall : 4.626
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.218
Fall : 4.314
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.638
Fall : 4.810
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.496
Fall : 4.607
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 4.646
Fall : 4.769
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 4.693
Fall : 4.865
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 4.782
Fall : 4.918
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.737
Fall : 4.933
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.737
Fall : 4.933
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.482
Fall : 4.608
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.426
Fall : 4.524
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.532
Fall : 4.666
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.342
Fall : 4.468
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.470
Fall : 4.545
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.591
Fall : 4.756
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.437
Fall : 4.502
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 5.003
Fall : 4.766
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.003
Fall : 4.766
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.568
Fall : 3.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.684
Fall : 3.701
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.827
Fall : 3.886
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.834
Fall : 3.845
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.832
Fall : 3.845
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.834
Fall : 3.845
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.780
Fall : 3.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.773
Fall : 3.767
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.857
Fall : 3.939
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 3.857
Fall : 3.939
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.847
Fall : 3.908
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.617
Fall : 3.642
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.834
Fall : 3.914
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.712
Fall : 1.657
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.709
Fall : 1.654
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.708
Fall : 1.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.245
Fall : 2.951
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.711
Fall : 1.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.755
Fall : 1.683
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.758
Fall : 1.686
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.726
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.640
Fall : 4.735
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.729
Fall : 4.863
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.651
Fall : 4.726
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.847
Fall : 5.000
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.761
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.103
Fall : 5.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.028
Fall : 5.231
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.163
Fall : 5.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.485
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.709
Fall : 4.827
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.704
Fall : 4.844
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.854
Fall : 4.932
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.750
Fall : 4.865
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.485
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.955
Fall : 5.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.927
Fall : 5.124
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.836
Fall : 4.901
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.802
Fall : 1.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.001
Fall : 3.106
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.348
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.066
Fall : 3.192
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.216
Fall : 3.391
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.218
Fall : 3.357
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.190
Fall : 3.318
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.119
Fall : 3.241
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.217
Fall : 3.365
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 3.104
Fall : 3.018
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 3.106
Fall : 3.020
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 3.034
Fall : 2.967
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.854
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.332
Fall : 3.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.950
Fall : 4.038
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.771
Fall : 3.883
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.594
Fall : 3.709
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.332
Fall : 3.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.790
Fall : 3.904
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.836
Fall : 3.962
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.571
Fall : 3.727
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.884
Fall : 4.010
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.235
Fall : 3.366
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.019
Fall : 4.130
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.746
Fall : 3.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.797
Fall : 3.915
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.235
Fall : 3.366
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.639
Fall : 3.768
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.688
Fall : 3.766
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.470
Fall : 3.620
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.557
Fall : 3.613
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.226
Fall : 2.220
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.678
Fall : 3.431
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.226
Fall : 2.220
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.350
Fall : 2.357
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.488
Fall : 2.534
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.288
Fall : 2.300
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.344
Fall : 2.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.347
Fall : 2.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.295
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.288
Fall : 2.300
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.270
Fall : 2.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.500
Fall : 2.572
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.589
Fall : 2.650
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.270
Fall : 2.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.479
Fall : 2.548
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.818
RF :
FR :
FF : 3.181
Input Port : SW[2]
Output Port : LED[2]
RR : 2.437
RF :
FR :
FF : 2.866
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 4.009
RF :
FR :
FF : 4.744
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.890
RF :
FR :
FF : 4.614
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.537
RF :
FR :
FF : 3.122
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.732
RF :
FR :
FF : 3.100
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 3.874
RF :
FR :
FF : 4.602
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.757
RF :
FR :
FF : 4.474
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.458
RF :
FR :
FF : 3.039
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.442
Fall : 3.368
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.544
Fall : 3.451
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.544
Fall : 3.451
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.443
Fall : 3.369
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.578
Fall : 3.513
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.486
Fall : 3.393
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.475
Fall : 3.382
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.475
Fall : 3.382
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.442
Fall : 3.368
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.757
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 2.865
Fall : 2.772
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 2.865
Fall : 2.772
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 2.759
Fall : 2.685
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 2.895
Fall : 2.830
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 2.809
Fall : 2.716
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 2.799
Fall : 2.706
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 2.799
Fall : 2.706
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 2.757
Fall : 2.683
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 3.504
1 to Hi-Z : 3.578
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 3.584
1 to Hi-Z : 3.677
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 3.584
1 to Hi-Z : 3.677
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 3.508
1 to Hi-Z : 3.582
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 3.677
1 to Hi-Z : 3.742
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 3.520
1 to Hi-Z : 3.613
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 3.515
1 to Hi-Z : 3.608
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 3.515
1 to Hi-Z : 3.608
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 3.504
1 to Hi-Z : 3.578
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
0 to Hi-Z : 2.800
1 to Hi-Z : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
0 to Hi-Z : 2.885
1 to Hi-Z : 2.978
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
0 to Hi-Z : 2.885
1 to Hi-Z : 2.978
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
0 to Hi-Z : 2.804
1 to Hi-Z : 2.878
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
0 to Hi-Z : 2.973
1 to Hi-Z : 3.038
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
0 to Hi-Z : 2.824
1 to Hi-Z : 2.917
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
0 to Hi-Z : 2.819
1 to Hi-Z : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
0 to Hi-Z : 2.819
1 to Hi-Z : 2.912
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
0 to Hi-Z : 2.800
1 to Hi-Z : 2.874
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -18.257
Hold : -0.217
Recovery : -6.225
Removal : 2.518
Minimum Pulse Width : 4.746
Clock : CLOCK_50
Setup : -18.257
Hold : -0.217
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 9.208
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 2.500
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 4.746
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -7.550
Hold : 0.178
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 19.597
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.914
Hold : 0.177
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 35.491
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -4.737
Hold : 0.178
Recovery : -6.225
Removal : 2.518
Minimum Pulse Width : 20.589
Clock : Design-wide TNS
Setup : -1145.21
Hold : -0.35
Recovery : -455.695
Removal : 0.0
Minimum Pulse Width : 0.0
Clock : CLOCK_50
Setup : -809.639
Hold : -0.350
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Setup : 0.000
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -292.429
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.914
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -40.228
Hold : 0.000
Recovery : -455.695
Removal : 0.000
Minimum Pulse Width : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.512
Fall : 1.781
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.245
Fall : 3.515
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.011
Fall : 1.277
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.263
Fall : 1.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.820
Fall : 3.101
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.493
Fall : -1.222
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.255
Fall : -1.937
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.592
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.358
Fall : -0.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.536
Fall : -1.078
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 10.793
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 9.931
Fall : 9.913
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 9.959
Fall : 10.101
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 9.579
Fall : 9.547
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 10.004
Fall : 10.080
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 10.661
Fall : 10.706
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 10.516
Fall : 10.623
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 10.720
Fall : 10.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 10.793
Fall : 10.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 10.560
Fall : 10.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 10.028
Fall : 10.042
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.968
Fall : 10.109
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.866
Fall : 9.872
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.785
Fall : 9.851
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 10.384
Fall : 10.396
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 10.128
Fall : 10.166
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 10.560
Fall : 10.568
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 10.152
Fall : 10.092
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 3.321
Fall : 3.234
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 3.319
Fall : 3.232
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.214
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 3.425
Fall : 3.340
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 3.416
Fall : 3.331
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 3.419
Fall : 3.334
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 3.294
Fall : 3.212
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 3.318
Fall : 3.231
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 3.320
Fall : 3.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 6.411
Fall : 6.384
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 5.780
Fall : 5.845
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 6.176
Fall : 6.240
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 5.956
Fall : 5.950
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 6.111
Fall : 6.220
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 6.151
Fall : 6.233
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 6.145
Fall : 6.180
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 6.074
Fall : 6.119
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 6.150
Fall : 6.186
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 6.401
Fall : 6.369
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 6.411
Fall : 6.384
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 5.985
Fall : 5.938
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 5.985
Fall : 5.938
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 6.305
Fall : 6.309
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 5.992
Fall : 5.944
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 6.005
Fall : 5.971
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 3.317
Fall : 3.230
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 3.417
Fall : 3.332
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 3.423
Fall : 3.338
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 4.576
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 4.505
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 8.268
Fall : 8.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 8.040
Fall : 8.140
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 7.800
Fall : 7.856
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 7.312
Fall : 7.306
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 7.984
Fall : 8.035
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 7.683
Fall : 7.767
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 8.090
Fall : 8.178
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 8.141
Fall : 8.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 8.268
Fall : 8.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.137
Fall : 8.269
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.137
Fall : 8.269
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.809
Fall : 7.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.599
Fall : 7.631
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.765
Fall : 7.806
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.406
Fall : 7.457
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.702
Fall : 7.721
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.981
Fall : 8.036
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.627
Fall : 7.634
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.089
Fall : 7.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.089
Fall : 7.827
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.289
Fall : 6.217
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.465
Fall : 6.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.666
Fall : 6.710
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.731
Fall : 6.659
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.731
Fall : 6.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.730
Fall : 6.659
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.646
Fall : 6.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.632
Fall : 6.539
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.755
Fall : 6.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.714
Fall : 6.797
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.755
Fall : 6.698
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.322
Fall : 6.341
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.698
Fall : 6.778
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.726
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 4.640
Fall : 4.735
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 4.729
Fall : 4.863
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 4.651
Fall : 4.726
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 4.847
Fall : 5.000
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 4.636
Fall : 4.761
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 5.103
Fall : 5.241
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 5.028
Fall : 5.231
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 5.163
Fall : 5.298
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.485
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.709
Fall : 4.827
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.704
Fall : 4.844
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.854
Fall : 4.932
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.750
Fall : 4.865
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.485
Fall : 4.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.955
Fall : 5.045
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.927
Fall : 5.124
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.836
Fall : 4.901
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : DRAM_ADDR[*]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[0]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[1]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[2]
Clock Port : CLOCK_50
Rise : 1.747
Fall : 1.692
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[3]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[4]
Clock Port : CLOCK_50
Rise : 1.748
Fall : 1.693
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[5]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[6]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[7]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[8]
Clock Port : CLOCK_50
Rise : 1.726
Fall : 1.676
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[9]
Clock Port : CLOCK_50
Rise : 1.807
Fall : 1.736
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[10]
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[11]
Clock Port : CLOCK_50
Rise : 1.802
Fall : 1.731
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_ADDR[12]
Clock Port : CLOCK_50
Rise : 1.724
Fall : 1.674
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[*]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[0]
Clock Port : CLOCK_50
Rise : 1.745
Fall : 1.690
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_BA[1]
Clock Port : CLOCK_50
Rise : 1.746
Fall : 1.691
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.001
Fall : 3.106
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.348
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.066
Fall : 3.192
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.216
Fall : 3.391
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.218
Fall : 3.357
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.190
Fall : 3.318
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.119
Fall : 3.241
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.217
Fall : 3.365
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[8]
Clock Port : CLOCK_50
Rise : 3.104
Fall : 3.018
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[9]
Clock Port : CLOCK_50
Rise : 3.106
Fall : 3.020
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[10]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[11]
Clock Port : CLOCK_50
Rise : 2.853
Fall : 2.790
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[12]
Clock Port : CLOCK_50
Rise : 3.034
Fall : 2.967
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[13]
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[14]
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.794
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[15]
Clock Port : CLOCK_50
Rise : 2.854
Fall : 2.812
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[*]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[0]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQM[1]
Clock Port : CLOCK_50
Rise : 1.744
Fall : 1.689
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_RAS_N
Clock Port : CLOCK_50
Rise : 1.800
Fall : 1.729
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_WE_N
Clock Port : CLOCK_50
Rise : 1.804
Fall : 1.733
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise : 3.708
Fall :
Clock Edge : Rise
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_CLK
Clock Port : CLOCK_50
Rise :
Fall : 3.654
Clock Edge : Fall
Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
Data Port : DRAM_DQ[*]
Clock Port : CLOCK_50
Rise : 3.332
Fall : 3.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[0]
Clock Port : CLOCK_50
Rise : 3.950
Fall : 4.038
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[1]
Clock Port : CLOCK_50
Rise : 3.771
Fall : 3.883
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[2]
Clock Port : CLOCK_50
Rise : 3.594
Fall : 3.709
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[3]
Clock Port : CLOCK_50
Rise : 3.332
Fall : 3.501
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[4]
Clock Port : CLOCK_50
Rise : 3.790
Fall : 3.904
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[5]
Clock Port : CLOCK_50
Rise : 3.836
Fall : 3.962
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[6]
Clock Port : CLOCK_50
Rise : 3.571
Fall : 3.727
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : DRAM_DQ[7]
Clock Port : CLOCK_50
Rise : 3.884
Fall : 4.010
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.235
Fall : 3.366
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.019
Fall : 4.130
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.746
Fall : 3.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.797
Fall : 3.915
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.235
Fall : 3.366
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.639
Fall : 3.768
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.688
Fall : 3.766
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.470
Fall : 3.620
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.557
Fall : 3.613
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.226
Fall : 2.220
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.678
Fall : 3.431
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.226
Fall : 2.220
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.350
Fall : 2.357
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.488
Fall : 2.534
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.288
Fall : 2.300
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.344
Fall : 2.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.347
Fall : 2.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.295
Fall : 2.308
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.288
Fall : 2.300
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.270
Fall : 2.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.500
Fall : 2.572
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.589
Fall : 2.650
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.270
Fall : 2.287
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.479
Fall : 2.548
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.628
RF :
FR :
FF : 4.693
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 6.977
RF :
FR :
FF : 7.192
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.783
RF :
FR :
FF : 7.007
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.317
RF :
FR :
FF : 4.516
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.732
RF :
FR :
FF : 3.100
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : DRAM_DQ[6]
RR : 3.874
RF :
FR :
FF : 4.602
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.757
RF :
FR :
FF : 4.474
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.458
RF :
FR :
FF : 3.039
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : SW[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : raw_loader_in
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_DAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_CLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : AUD_ADCDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_BA[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQM[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_RAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CAS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CKE
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_WE_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_CS_N
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_ADDR[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : DRAM_DQ[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 276
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1181
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1940
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 248
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1050
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1437
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 276
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 108
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]
To Clock : CLOCK_50
RR Paths : 1
FR Paths : 1
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1181
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1940
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 248
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1050
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1437
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Recovery Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Removal Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 2
Hold : 2
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 0
Hold : 0
Property : Unconstrained Output Port Paths
Setup : 0
Hold : 0
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sat Apr 2 16:35:55 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'spectrum.sdc'
Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port
Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection
Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]}
Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin
Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock
Warning (332125): Found combinational loop of 509 nodes
Warning (332126): Node "z80_|bus_control_|db[5]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~8|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~8|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~9|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~9|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|dataa"
Warning (332126): Node "z80_|alu_|db[7]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~7|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~8|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~10|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~10|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~11|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~14|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~27|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~27|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datab"
Warning (332126): Node "z80_|alu_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~21|datab"
Warning (332126): Node "z80_|alu_control_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_control_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datac"
Warning (332126): Node "z80_|alu_control_|db[6]~23|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa"
Warning (332126): Node "z80_|alu_|db[6]~21|datac"
Warning (332126): Node "z80_|alu_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|dataa"
Warning (332126): Node "z80_|bus_control_|db[6]~8|datad"
Warning (332126): Node "z80_|bus_control_|db[6]~8|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~9|datad"
Warning (332126): Node "z80_|bus_control_|db[6]~9|combout"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datac"
Warning (332126): Node "z80_|alu_|db_high[3]~6|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout"
Warning (332126): Node "z80_|alu_|db[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~19|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~20|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~20|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|datab"
Warning (332126): Node "z80_|alu_|db[5]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~10|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~25|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~26|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~26|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|dataa"
Warning (332126): Node "z80_|alu_|db[4]~10|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa"
Warning (332126): Node "z80_|alu_control_|db[4]~31|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~32|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~32|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~33|datac"
Warning (332126): Node "z80_|alu_control_|db[4]~33|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datad"
Warning (332126): Node "z80_|alu_|db[4]~8|datab"
Warning (332126): Node "z80_|alu_|db[4]~8|combout"
Warning (332126): Node "z80_|alu_|db[4]~10|datab"
Warning (332126): Node "z80_|bus_control_|db[4]~19|datac"
Warning (332126): Node "z80_|bus_control_|db[4]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~12|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~14|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~17|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datac"
Warning (332126): Node "z80_|alu_|db[1]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|datac"
Warning (332126): Node "z80_|alu_control_|db[1]~25|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~27|dataa"
Warning (332126): Node "z80_|alu_control_|db[1]~27|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|datad"
Warning (332126): Node "z80_|alu_control_|db[1]~26|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~27|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa"
Warning (332126): Node "z80_|alu_|db[1]~15|datab"
Warning (332126): Node "z80_|alu_|db[1]~15|combout"
Warning (332126): Node "z80_|alu_|db[1]~16|datab"
Warning (332126): Node "z80_|bus_control_|db[1]~10|datab"
Warning (332126): Node "z80_|bus_control_|db[1]~10|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~11|datad"
Warning (332126): Node "z80_|bus_control_|db[1]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~16|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~6|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~6|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~7|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~7|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~11|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~11|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|datac"
Warning (332126): Node "z80_|alu_|db[2]~12|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|datac"
Warning (332126): Node "z80_|alu_control_|db[2]~28|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datad"
Warning (332126): Node "z80_|alu_control_|db[2]~29|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa"
Warning (332126): Node "z80_|alu_control_|db[2]~30|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~37|datab"
Warning (332126): Node "z80_|alu_control_|db[2]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datac"
Warning (332126): Node "z80_|alu_|db[2]~11|datab"
Warning (332126): Node "z80_|alu_|db[2]~11|combout"
Warning (332126): Node "z80_|alu_|db[2]~12|datab"
Warning (332126): Node "z80_|bus_control_|db[2]~12|datad"
Warning (332126): Node "z80_|bus_control_|db[2]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~13|datad"
Warning (332126): Node "z80_|bus_control_|db[2]~13|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~30|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~15|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~16|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab"
Warning (332126): Node "z80_|alu_|db[2]~11|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~7|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~0|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~0|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~1|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~1|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~5|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~5|combout"
Warning (332126): Node "z80_|alu_|db[3]~13|datac"
Warning (332126): Node "z80_|alu_|db[3]~13|combout"
Warning (332126): Node "z80_|alu_|db[3]~14|datab"
Warning (332126): Node "z80_|alu_|db[3]~14|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa"
Warning (332126): Node "z80_|alu_control_|db[3]~36|combout"
Warning (332126): Node "z80_|bus_control_|db[3]~21|dataa"
Warning (332126): Node "z80_|bus_control_|db[3]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~4|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~4|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~13|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~14|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~10|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~11|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~18|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~23|combout"
Warning (332126): Node "z80_|alu_|db[0]~17|datac"
Warning (332126): Node "z80_|alu_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_|db[0]~18|datac"
Warning (332126): Node "z80_|alu_|db[0]~18|combout"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|datac"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|datab"
Warning (332126): Node "z80_|alu_control_|db[0]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~14|datab"
Warning (332126): Node "z80_|alu_control_|db[0]~14|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~17|dataa"
Warning (332126): Node "z80_|bus_control_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~10|dataa"
Warning (332126): Node "z80_|alu_control_|db[0]~10|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|datac"
Warning (332126): Node "z80_|alu_|db[0]~18|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~23|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab"
Warning (332126): Node "z80_|alu_|db[0]~17|datab"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datad"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~22|datad"
Warning (332126): Node "z80_|sw1_|db_down[3]~2|datac"
Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datad"
Warning (332126): Node "z80_|alu_control_|db[3]~35|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~36|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datac"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datac"
Warning (332126): Node "z80_|alu_|db[3]~14|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~6|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~1|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout"
Warning (332126): Node "z80_|alu_|db[3]~13|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~21|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout"
Warning (332126): Node "z80_|alu_|db[1]~15|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datab"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datac"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~33|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac"
Warning (332126): Node "z80_|alu_|db[4]~8|datac"
Warning (332126): Node "z80_|alu_|db_low[3]~0|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout"
Warning (332126): Node "z80_|alu_|db[5]~23|datac"
Warning (332126): Node "z80_|alu_|db[5]~23|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datad"
Warning (332126): Node "z80_|alu_control_|db[5]~17|datad"
Warning (332126): Node "z80_|alu_control_|db[5]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab"
Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~17|datac"
Warning (332126): Node "z80_|alu_|db[5]~23|datab"
Warning (332126): Node "z80_|bus_control_|db[5]~15|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac"
Warning (332126): Node "z80_|alu_|db[7]~19|datac"
Warning (332126): Node "z80_|alu_|db[7]~19|combout"
Warning (332126): Node "z80_|alu_|db[7]~20|datad"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa"
Warning (332126): Node "z80_|alu_control_|db[7]~18|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~20|datac"
Warning (332126): Node "z80_|alu_control_|db[7]~20|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~5|datad"
Warning (332126): Node "z80_|bus_control_|db[7]~5|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~7|datac"
Warning (332126): Node "z80_|bus_control_|db[7]~7|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa"
Warning (332126): Node "z80_|alu_control_|db[7]~19|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~20|datab"
Warning (332126): Node "z80_|alu_|db[7]~19|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~19|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~16|datac"
Warning (332126): Node "z80_|alu_|db_high[1]~15|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~13|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~4|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~10|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~18|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datac"
Critical Warning (332081): Design contains combinational loop of 509 nodes. Estimating the delays through the loop.
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -18.257
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -18.257 -809.639 CLOCK_50
Info (332119): -7.550 -292.429 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.737 -40.228 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 2.500 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is -0.026
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.026 -0.026 CLOCK_50
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.343 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.358 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -6.225
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.225 -455.695 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.696
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.696 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.752
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.489 0.000 CLOCK_50
Info (332119): 19.601 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.596 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -17.443
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -17.443 -768.889 CLOCK_50
Info (332119): -6.729 -260.267 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.426 -37.694 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 3.262 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is 0.059
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.059 0.000 CLOCK_50
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -5.745
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -5.745 -420.318 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.369
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.369 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.746
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.746 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.487 0.000 CLOCK_50
Info (332119): 19.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.589 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -14.929
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.929 -634.264 CLOCK_50
Info (332119): -4.459 -174.631 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -3.773 -34.191 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 5.613 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case hold slack is -0.217
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.217 -0.350 CLOCK_50
Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -4.694
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.694 -356.359 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 2.518
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 4.784
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 4.784 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 9.208 0.000 CLOCK_50
Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 530 warnings
Info: Peak virtual memory: 445 megabytes
Info: Processing ended: Sat Apr 2 16:35:59 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
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