44 lines
1.2 KiB
Systemverilog
44 lines
1.2 KiB
Systemverilog
//============================================================================
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// Z80 Top level interface
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//============================================================================
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`ifndef Z80_IFC
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`define Z80_IFC
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`timescale 100 ns/ 100 ns
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// Define set and clear for the negative logic pins
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`define CLR 1
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`define SET 0
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interface z80_if (input logic CLK);
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logic nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK;
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logic nWAIT, nINT, nNMI, nRESET, nBUSRQ;
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logic [15:0] A;
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wire [7:0] D;
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//=================================================
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// Modport for the CPU module (internal) interface
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// Also considered "design under test" port
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//=================================================
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modport dut (
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output nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,
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input nWAIT, nINT, nNMI, nRESET, nBUSRQ,
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input CLK,
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output A,
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inout D);
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//=================================================
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// Modport for the user (external) pin interface
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// Also considered a "test bench" port
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//=================================================
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modport tb (
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input nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,
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output nWAIT, nINT, nNMI, nRESET, nBUSRQ,
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input CLK,
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input A,
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inout D);
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endinterface : z80_if
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`endif
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