159 lines
7.3 KiB
Verilog
159 lines
7.3 KiB
Verilog
//=============================================================================
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// This module implements the instruction execute state logic.
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//
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// Copyright (C) 2014-2016 Goran Devic
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//=============================================================================
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// Using a compiled format will include files generated by "gencompile.py" script
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// These files are a processed version of "exec_matrix_compiled.vh"
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// You would define this on Xilinx and undefine (comment out) on Altera
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`define USE_COMPILED_FORMAT
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module execute
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(
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//----------------------------------------------------------
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// Control signals generated by the instruction execution
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//----------------------------------------------------------
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`include "exec_module.vh"
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output reg nextM, // Last M cycle of any instruction
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output reg setM1, // Last T clock of any instruction
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output reg fFetch, // Function: opcode fetch cycle ("M1")
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output reg fMRead, // Function: memory read cycle
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output reg fMWrite, // Function: memory write cycle
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output reg fIORead, // Function: IO Read cycle
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output reg fIOWrite, // Function: IO Write cycle
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//----------------------------------------------------------
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// Inputs from the instruction decode PLA
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//----------------------------------------------------------
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input wire [104:0] pla, // Statically decoded instructions
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//----------------------------------------------------------
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// Inputs from various blocks
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//----------------------------------------------------------
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input wire in_intr, // Servicing maskable interrupt
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input wire in_nmi, // Servicing non-maskable interrupt
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input wire in_halt, // Currently in HALT mode
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input wire im1, // Interrupt Mode 1
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input wire im2, // Interrupt Mode 2
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input wire use_ixiy, // Special decode signal
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input wire flags_cond_true, // Flags condition is true
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input wire repeat_en, // Enable repeat of a block instruction
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input wire flags_zf, // ZF to test a condition
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input wire flags_nf, // NF to test for subtraction
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input wire flags_sf, // SF to test for 8-bit sign of a value
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input wire flags_cf, // CF to set HF for CCF
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//----------------------------------------------------------
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// Machine and clock cycles
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//----------------------------------------------------------
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input wire M1, // Machine cycle #1
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input wire M2, // Machine cycle #2
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input wire M3, // Machine cycle #3
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input wire M4, // Machine cycle #4
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input wire M5, // Machine cycle #5
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input wire T1, // T-cycle #1
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input wire T2, // T-cycle #2
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input wire T3, // T-cycle #3
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input wire T4, // T-cycle #4
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input wire T5, // T-cycle #5
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input wire T6 // T-cycle #6
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);
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// Detects unknown instructions by signalling the known ones
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reg validPLA; // Valid PLA asserts this reg
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// Activates a state machine to compute WZ=IX+d; takes 5T cycles
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reg ixy_d; // Compute WX=IX+d
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// Signals the setting of IX/IY prefix flags; inhibits clearing them
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reg setIXIY; // Set IX/IY flag at the next T cycle
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// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
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reg nonRep; // Non-repeating block instruction
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// Suspends incrementing PC through address latch unless in HALT or interrupt mode
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reg pc_inc_hold; // Normally 0 unless in one of those modes
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//--------------------------------------------------------------
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// Define various shortcuts to field naming
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//--------------------------------------------------------------
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`define GP_REG_BC 2'h0
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`define GP_REG_DE 2'h1
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`define GP_REG_HL 2'h2
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`define GP_REG_AF 2'h3
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`define PFSEL_P 2'h0
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`define PFSEL_V 2'h1
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`define PFSEL_IFF2 2'h2
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`define PFSEL_REP 2'h3
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//--------------------------------------------------------------
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// Make available different bits and sections of the opcode byte
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//--------------------------------------------------------------
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wire op0 = pla[99];
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wire op1 = pla[100];
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wire op2 = pla[101];
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wire op3 = pla[102];
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wire op4 = pla[103];
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wire op5 = pla[104];
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wire [1:0] op21 = { pla[101], pla[100] };
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wire [1:0] op54 = { pla[104], pla[103] };
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//--------------------------------------------------------------
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// 8-bit register selections needs to swizzle mux for A and F
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//--------------------------------------------------------------
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wire rsel0 = op0 ^ (op1 & op2);
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wire rsel3 = op3 ^ (op4 & op5);
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`ifdef USE_COMPILED_FORMAT
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`include "temp_wires.vh" // Define all temp wires used with compiled equations
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`endif
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always @(*) // always_comb
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begin
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//-----------------------------------------------------------------------------
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// Default assignment of all control outputs to 0 to prevent generating latches
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//-----------------------------------------------------------------------------
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`include "exec_zero.vh" // Initial assignment to all ctl wires to zero
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// Reset internal control regs
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validPLA = 0; // Will be set by every *valid* PLA entry
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nextM = 0; // Will be set to advance to the next M cycle
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setM1 = 0; // Will be set on a last M/T cycle of an instruction
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// Reset global machine cycle functions
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fFetch = M1; // Fetch is aliased to M1
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fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
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ixy_d = 0;
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setIXIY = 0;
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nonRep = 0;
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pc_inc_hold = 0;
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//-------------------------------------------------------------------------
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// State-based signal assignment; code generated from Timings spreadsheet
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//-------------------------------------------------------------------------
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`ifdef USE_COMPILED_FORMAT
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`include "exec_matrix_compiled.vh" // Compiled execution equations
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`else
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`include "exec_matrix.vh" // Execution statements in the original nested-if format
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`endif
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// Needed by data bus 0 override logic, make only one bus writer active at any time
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ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);
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end
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endmodule
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