129 lines
3.8 KiB
Verilog
129 lines
3.8 KiB
Verilog
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sat Feb 27 08:13:14 2016"
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module address_latch(
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ctl_inc_cy,
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ctl_inc_dec,
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ctl_al_we,
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ctl_inc_limit6,
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ctl_bus_inc_oe,
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clk,
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ctl_apin_mux,
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ctl_apin_mux2,
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clrpc,
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nreset,
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address_is_1,
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abus,
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address
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);
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input wire ctl_inc_cy;
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input wire ctl_inc_dec;
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input wire ctl_al_we;
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input wire ctl_inc_limit6;
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input wire ctl_bus_inc_oe;
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input wire clk;
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input wire ctl_apin_mux;
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input wire ctl_apin_mux2;
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input wire clrpc;
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input wire nreset;
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output wire address_is_1;
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inout wire [15:0] abus;
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output wire [15:0] address;
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wire [15:0] abusz;
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reg [15:0] Q;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire [15:0] SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_4;
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wire [15:0] SYNTHESIZED_WIRE_5;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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Q[15:0] <= 16'b0000000000000000;
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end
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else
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if (ctl_al_we)
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begin
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Q[15:0] <= abusz[15:0];
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end
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end
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assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1);
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assign abusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus;
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assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz;
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assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz;
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assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz;
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assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz;
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assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz;
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assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz;
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assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz;
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assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz;
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assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz;
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assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz;
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assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz;
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assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz;
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assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz;
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assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz;
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assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz;
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assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz;
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assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8];
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address_mux b2v_inst7(
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.select(ctl_apin_mux2),
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.in0(SYNTHESIZED_WIRE_5),
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.in1(Q),
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.out(address));
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assign SYNTHESIZED_WIRE_2 = ~clrpc;
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inc_dec b2v_inst_inc_dec(
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.limit6(ctl_inc_limit6),
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.decrement(ctl_inc_dec),
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.carry_in(ctl_inc_cy),
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.d(Q),
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.address(SYNTHESIZED_WIRE_7));
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address_mux b2v_mux(
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.select(ctl_apin_mux),
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.in0(abusz),
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.in1(SYNTHESIZED_WIRE_7),
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.out(SYNTHESIZED_WIRE_5));
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assign SYNTHESIZED_WIRE_4 = ~Q[0];
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endmodule
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