Merge branch 'sdram'

PLLJ_PLLSPE_INFO.txt

@@ -1,3 +1,8 @@
+PLL_Name	sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1
+PLLJITTER	35
+PLLSPEmax	84
+PLLSPEmin	-53
+
 PLL_Name	ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1
 PLLJITTER	NA
 PLLSPEmax	84

db/altsyncram_6u14.tdf

@@ -0,0 +1,439 @@
+--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=0 NUMWORDS_B=0 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=12 WIDTH_B=12 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_6u14
+( 
+	address_a[6..0]	:	input;
+	address_b[6..0]	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	clocken1	:	input;
+	data_a[11..0]	:	input;
+	q_b[11..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a10 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a11 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 7,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 127,
+			PORT_A_LOGICAL_RAM_DEPTH = 128,
+			PORT_A_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 7,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 127,
+			PORT_B_LOGICAL_RAM_DEPTH = 128,
+			PORT_B_LOGICAL_RAM_WIDTH = 12,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[6..0]	: WIRE;
+	address_b_wire[6..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[11..0].clk0 = clock0;
+	ram_block1a[11..0].clk1 = clock1;
+	ram_block1a[11..0].ena0 = wren_a;
+	ram_block1a[11..0].ena1 = clocken1;
+	ram_block1a[11..0].portaaddr[] = ( address_a_wire[6..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[9].portadatain[] = ( data_a[9..9]);
+	ram_block1a[10].portadatain[] = ( data_a[10..10]);
+	ram_block1a[11].portadatain[] = ( data_a[11..11]);
+	ram_block1a[11..0].portawe = wren_a;
+	ram_block1a[11..0].portbaddr[] = ( address_b_wire[6..0]);
+	ram_block1a[11..0].portbre = B"111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[11..0].portbdataout[0..0]);
+END;
+--VALID FILE

db/altsyncram_eh91.tdf

@@ -0,0 +1,417 @@
+--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom/hc91.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION decode_c8a (data[0..0])
+RETURNS ( eq[1..0]);
+FUNCTION mux_3nb (data[15..0], sel[0..0])
+RETURNS ( result[7..0]);
+FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 16 reg 2 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_eh91
+( 
+	address_a[13..0]	:	input;
+	clock0	:	input;
+	q_a[7..0]	:	output;
+) 
+VARIABLE 
+	address_reg_a[0..0] : dffe;
+	out_address_reg_a[0..0] : dffe;
+	rden_decode : decode_c8a;
+	mux2 : mux_3nb;
+	ram_block1a0 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a10 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a11 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a12 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a13 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a14 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a15 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom/hc91.hex",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_sel[0..0]	: WIRE;
+	address_a_wire[13..0]	: WIRE;
+	rden_decode_addr_sel_a[0..0]	: WIRE;
+	w_addr_val_a3w[0..0]	: WIRE;
+
+BEGIN 
+	address_reg_a[].clk = clock0;
+	address_reg_a[].d = address_a_sel[];
+	out_address_reg_a[].clk = clock0;
+	out_address_reg_a[].d = address_reg_a[].q;
+	rden_decode.data[] = w_addr_val_a3w[];
+	mux2.data[] = ( ram_block1a[15..0].portadataout[0..0]);
+	mux2.sel[] = out_address_reg_a[].q;
+	ram_block1a[15..0].clk0 = clock0;
+	ram_block1a[15..0].ena0 = ( rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);
+	ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[15..0].portare = B"1111111111111111";
+	address_a_sel[0..0] = address_a[13..13];
+	address_a_wire[] = address_a[];
+	q_a[] = mux2.result[];
+	rden_decode_addr_sel_a[0..0] = address_a_wire[13..13];
+	w_addr_val_a3w[] = rden_decode_addr_sel_a[];
+END;
+--VALID FILE

db/cmpr_ngc.tdf

@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=1 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_ngc
+( 
+	aeb	:	output;
+	dataa[0..0]	:	input;
+	datab[0..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[1..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] $ data_wire[1..1]);
+	data_wire[] = ( datab[0..0], dataa[0..0]);
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

db/cmpr_qgc.tdf

@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=4 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_qgc
+( 
+	aeb	:	output;
+	dataa[3..0]	:	input;
+	datab[3..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[9..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[6..6] $ data_wire[7..7]) # (data_wire[8..8] $ data_wire[9..9])), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

db/cmpr_qkk.tdf

@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="NO" aeb dataa datab CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_qkk
+( 
+	aeb	:	output;
+	dataa[4..0]	:	input;
+	datab[4..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[12..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]);
+	data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6])));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

db/cntr_23j.tdf

@@ -0,0 +1,86 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=1 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=1 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_ngc (dataa[0..0], datab[0..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 1 reg 1 
+SUBDESIGN cntr_23j
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[0..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[0..0] : dffeas;
+	cmpr1 : cmpr_ngc;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[0..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[0..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[0..0]	: WIRE;
+	safe_q[0..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[0..0].cin = ( external_cin);
+	counter_comb_bita[0..0].dataa = ( counter_reg_bit[0..0].q);
+	counter_comb_bita[0..0].datab = ( updown_dir);
+	counter_comb_bita[0..0].datad = ( B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr1.dataa[] = safe_q[];
+	cmpr1.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	compare_result = cmpr1.aeb;
+	cout_actual = (counter_comb_bita[0].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"0";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"1";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE

db/cntr_bgi.tdf

@@ -0,0 +1,102 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=12 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=4 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_qgc (dataa[3..0], datab[3..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 4 reg 4 
+SUBDESIGN cntr_bgi
+( 
+	clock	:	input;
+	q[3..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[3..0] : dffeas;
+	cmpr1 : cmpr_qgc;
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[3..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[3..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[3..0]	: WIRE;
+	safe_q[3..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin);
+	counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q);
+	counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[3..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr1.dataa[] = safe_q[];
+	cmpr1.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	clk_en = VCC;
+	cnt_en = VCC;
+	compare_result = cmpr1.aeb;
+	cout_actual = (counter_comb_bita[3].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"1011";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"1111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE

db/cntr_egi.tdf

@@ -0,0 +1,102 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=15 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=4 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_qgc (dataa[3..0], datab[3..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 4 reg 4 
+SUBDESIGN cntr_egi
+( 
+	clock	:	input;
+	q[3..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[3..0] : dffeas;
+	cmpr1 : cmpr_qgc;
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[3..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[3..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[3..0]	: WIRE;
+	safe_q[3..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin);
+	counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q);
+	counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[3..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr1.dataa[] = safe_q[];
+	cmpr1.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	clk_en = VCC;
+	cnt_en = VCC;
+	compare_result = cmpr1.aeb;
+	cout_actual = (counter_comb_bita[3].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"1110";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"1111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE

db/cntr_i6j.tdf

@@ -0,0 +1,101 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_modulus=128 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=7 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+
+--synthesis_resources = lut 7 reg 7 
+SUBDESIGN cntr_i6j
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[6..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneive_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[6..0] : dffeas;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	data[6..0]	: NODE;
+	external_cin	: WIRE;
+	s_val[6..0]	: WIRE;
+	safe_q[6..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, external_cin);
+	counter_comb_bita[6..0].dataa = ( counter_reg_bit[6..0].q);
+	counter_comb_bita[6..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[6..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[6..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = ((sclr # sset) # sload);
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	q[] = safe_q[];
+	s_val[] = B"1111111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	updown_dir = B"1";
+END;
+--VALID FILE

db/decode_dvf.tdf

@@ -0,0 +1,35 @@
+--lpm_decode CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_DECODES=2 LPM_WIDTH=1 data enable eq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 1 
+SUBDESIGN decode_dvf
+( 
+	data[0..0]	:	input;
+	enable	:	input;
+	eq[1..0]	:	output;
+) 
+VARIABLE 
+	eq_node[1..0]	: WIRE;
+
+BEGIN 
+	eq[] = eq_node[];
+	eq_node[] = ( (data[] & enable), ((! data[]) & enable));
+END;
+--VALID FILE

db/mux_ssc.tdf

@@ -0,0 +1,67 @@
+--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=15 LPM_WIDTHS=1 data result sel
+--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 15 
+SUBDESIGN mux_ssc
+( 
+	data[29..0]	:	input;
+	result[14..0]	:	output;
+	sel[0..0]	:	input;
+) 
+VARIABLE 
+	result_node[14..0]	: WIRE;
+	sel_node[0..0]	: WIRE;
+	w_data102w[1..0]	: WIRE;
+	w_data114w[1..0]	: WIRE;
+	w_data126w[1..0]	: WIRE;
+	w_data138w[1..0]	: WIRE;
+	w_data150w[1..0]	: WIRE;
+	w_data162w[1..0]	: WIRE;
+	w_data174w[1..0]	: WIRE;
+	w_data18w[1..0]	: WIRE;
+	w_data30w[1..0]	: WIRE;
+	w_data42w[1..0]	: WIRE;
+	w_data4w[1..0]	: WIRE;
+	w_data54w[1..0]	: WIRE;
+	w_data66w[1..0]	: WIRE;
+	w_data78w[1..0]	: WIRE;
+	w_data90w[1..0]	: WIRE;
+
+BEGIN 
+	result[] = result_node[];
+	result_node[] = ( ((sel_node[] & w_data174w[1..1]) # ((! sel_node[]) & w_data174w[0..0])), ((sel_node[] & w_data162w[1..1]) # ((! sel_node[]) & w_data162w[0..0])), ((sel_node[] & w_data150w[1..1]) # ((! sel_node[]) & w_data150w[0..0])), ((sel_node[] & w_data138w[1..1]) # ((! sel_node[]) & w_data138w[0..0])), ((sel_node[] & w_data126w[1..1]) # ((! sel_node[]) & w_data126w[0..0])), ((sel_node[] & w_data114w[1..1]) # ((! sel_node[]) & w_data114w[0..0])), ((sel_node[] & w_data102w[1..1]) # ((! sel_node[]) & w_data102w[0..0])), ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0])));
+	sel_node[] = ( sel[0..0]);
+	w_data102w[] = ( data[23..23], data[8..8]);
+	w_data114w[] = ( data[24..24], data[9..9]);
+	w_data126w[] = ( data[25..25], data[10..10]);
+	w_data138w[] = ( data[26..26], data[11..11]);
+	w_data150w[] = ( data[27..27], data[12..12]);
+	w_data162w[] = ( data[28..28], data[13..13]);
+	w_data174w[] = ( data[29..29], data[14..14]);
+	w_data18w[] = ( data[16..16], data[1..1]);
+	w_data30w[] = ( data[17..17], data[2..2]);
+	w_data42w[] = ( data[18..18], data[3..3]);
+	w_data4w[] = ( data[15..15], data[0..0]);
+	w_data54w[] = ( data[19..19], data[4..4]);
+	w_data66w[] = ( data[20..20], data[5..5]);
+	w_data78w[] = ( data[21..21], data[6..6]);
+	w_data90w[] = ( data[22..22], data[7..7]);
+END;
+--VALID FILE

db/pll_sdram_altpll.v

@@ -0,0 +1,92 @@
+//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=50 clk0_duty_cycle=50 clk0_multiply_by=133 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll_sdram" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+//CBXI_INSTANCE_NAME="spectrum_pll_sdram_sdram_clocks_altpll_altpll_component"
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+
+
+
+//synthesis_resources = cycloneive_pll 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  pll_sdram_altpll
+	( 
+	clk,
+	inclk) /* synthesis synthesis_clearbox=1 */;
+	output   [4:0]  clk;
+	input   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [4:0]   wire_pll1_clk;
+	wire  wire_pll1_fbout;
+
+	cycloneive_pll   pll1
+	( 
+	.activeclock(),
+	.clk(wire_pll1_clk),
+	.clkbad(),
+	.fbin(wire_pll1_fbout),
+	.fbout(wire_pll1_fbout),
+	.inclk(inclk),
+	.locked(),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.vcooverrange(),
+	.vcounderrange()
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.areset(1'b0),
+	.clkswitch(1'b0),
+	.configupdate(1'b0),
+	.pfdena(1'b1),
+	.phasecounterselect({3{1'b0}}),
+	.phasestep(1'b0),
+	.phaseupdown(1'b0),
+	.scanclk(1'b0),
+	.scanclkena(1'b1),
+	.scandata(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pll1.bandwidth_type = "auto",
+		pll1.clk0_divide_by = 50,
+		pll1.clk0_duty_cycle = 50,
+		pll1.clk0_multiply_by = 133,
+		pll1.clk0_phase_shift = "0",
+		pll1.compensate_clock = "clk0",
+		pll1.inclk0_input_frequency = 20000,
+		pll1.operation_mode = "normal",
+		pll1.pll_type = "auto",
+		pll1.lpm_type = "cycloneive_pll";
+	assign
+		clk = {wire_pll1_clk[4:0]};
+endmodule //pll_sdram_altpll
+//VALID FILE

db/sdram_clk_gen_altpll.v

@@ -0,0 +1,96 @@
+//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="3000" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sdram_clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+//CBXI_INSTANCE_NAME="spectrum_sdram_controller_sdram_sdram_clk_gen_sdram_clk_pll_altpll_altpll_component"
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+
+
+
+//synthesis_resources = cycloneive_pll 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  sdram_clk_gen_altpll
+	( 
+	clk,
+	inclk) /* synthesis synthesis_clearbox=1 */;
+	output   [4:0]  clk;
+	input   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [4:0]   wire_pll1_clk;
+	wire  wire_pll1_fbout;
+
+	cycloneive_pll   pll1
+	( 
+	.activeclock(),
+	.clk(wire_pll1_clk),
+	.clkbad(),
+	.fbin(wire_pll1_fbout),
+	.fbout(wire_pll1_fbout),
+	.inclk(inclk),
+	.locked(),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.vcooverrange(),
+	.vcounderrange()
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.areset(1'b0),
+	.clkswitch(1'b0),
+	.configupdate(1'b0),
+	.pfdena(1'b1),
+	.phasecounterselect({3{1'b0}}),
+	.phasestep(1'b0),
+	.phaseupdown(1'b0),
+	.scanclk(1'b0),
+	.scanclkena(1'b1),
+	.scandata(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pll1.bandwidth_type = "auto",
+		pll1.clk0_divide_by = 1,
+		pll1.clk0_duty_cycle = 50,
+		pll1.clk0_multiply_by = 2,
+		pll1.clk0_phase_shift = "0",
+		pll1.clk1_divide_by = 1,
+		pll1.clk1_duty_cycle = 50,
+		pll1.clk1_multiply_by = 2,
+		pll1.clk1_phase_shift = "3000",
+		pll1.compensate_clock = "clk0",
+		pll1.inclk0_input_frequency = 20000,
+		pll1.operation_mode = "normal",
+		pll1.pll_type = "auto",
+		pll1.lpm_type = "cycloneive_pll";
+	assign
+		clk = {wire_pll1_clk[4:0]};
+endmodule //sdram_clk_gen_altpll
+//VALID FILE

db/sld_ela_trigger_cso.tdf

@@ -0,0 +1,55 @@
+--sld_ela_trigger DATA_BITS=12 INVERSION_MASK=00000000 INVERSION_MASK_LENGTH=1 LEVEL_NAMES="sld_reserved_spectrum_auto_signaltap_0_1_eb98," POWER_UP_TRIGGER=0 TRIGGER_LEVEL=1 acq_clk data_in reset_all setup_bit_in setup_bit_out setup_ena tck trigger_level_match_out
+--VERSION_BEGIN 13.1 cbx_mgl 2013:10:17:09:48:49:SJ cbx_sld_ela_trigger 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION sld_reserved_spectrum_auto_signaltap_0_1_eb98 (acq_clk, data_in[11..0], reset_all, setup_bit_in, setup_ena, tck)
+WITH ( ASYNC_ENABLED, DATA_BITS, SYNC_ENABLED, TRIGGER_LEVEL)
+RETURNS ( setup_bit_out, trigger);
+
+--synthesis_resources = sld_reserved_spectrum_auto_signaltap_0_1_eb98 1 
+SUBDESIGN sld_ela_trigger_cso
+( 
+	acq_clk	:	input;
+	data_in[11..0]	:	input;
+	reset_all	:	input;
+	setup_bit_in	:	input;
+	setup_bit_out	:	output;
+	setup_ena	:	input;
+	tck	:	input;
+	trigger_level_match_out[0..0]	:	output;
+) 
+VARIABLE 
+	mgl_prim1 : sld_reserved_spectrum_auto_signaltap_0_1_eb98
+		WITH (
+			ASYNC_ENABLED = 0,
+			DATA_BITS = 12,
+			SYNC_ENABLED = 0,
+			TRIGGER_LEVEL = 1
+		);
+
+BEGIN 
+	mgl_prim1.acq_clk = acq_clk;
+	mgl_prim1.data_in[] = data_in[];
+	mgl_prim1.reset_all = reset_all;
+	mgl_prim1.setup_bit_in = setup_bit_in;
+	mgl_prim1.setup_ena = setup_ena;
+	mgl_prim1.tck = tck;
+	setup_bit_out = mgl_prim1.setup_bit_out;
+	trigger_level_match_out[] = ( mgl_prim1.trigger);
+END;
+--VALID FILE