56 lines
2.1 KiB
Plaintext
56 lines
2.1 KiB
Plaintext
--sld_ela_trigger DATA_BITS=12 INVERSION_MASK=00000000 INVERSION_MASK_LENGTH=1 LEVEL_NAMES="sld_reserved_spectrum_auto_signaltap_0_1_eb98," POWER_UP_TRIGGER=0 TRIGGER_LEVEL=1 acq_clk data_in reset_all setup_bit_in setup_bit_out setup_ena tck trigger_level_match_out
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--VERSION_BEGIN 13.1 cbx_mgl 2013:10:17:09:48:49:SJ cbx_sld_ela_trigger 2013:10:17:09:48:19:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION sld_reserved_spectrum_auto_signaltap_0_1_eb98 (acq_clk, data_in[11..0], reset_all, setup_bit_in, setup_ena, tck)
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WITH ( ASYNC_ENABLED, DATA_BITS, SYNC_ENABLED, TRIGGER_LEVEL)
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RETURNS ( setup_bit_out, trigger);
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--synthesis_resources = sld_reserved_spectrum_auto_signaltap_0_1_eb98 1
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SUBDESIGN sld_ela_trigger_cso
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(
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acq_clk : input;
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data_in[11..0] : input;
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reset_all : input;
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setup_bit_in : input;
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setup_bit_out : output;
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setup_ena : input;
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tck : input;
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trigger_level_match_out[0..0] : output;
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)
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VARIABLE
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mgl_prim1 : sld_reserved_spectrum_auto_signaltap_0_1_eb98
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WITH (
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ASYNC_ENABLED = 0,
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DATA_BITS = 12,
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SYNC_ENABLED = 0,
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TRIGGER_LEVEL = 1
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);
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BEGIN
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mgl_prim1.acq_clk = acq_clk;
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mgl_prim1.data_in[] = data_in[];
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mgl_prim1.reset_all = reset_all;
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mgl_prim1.setup_bit_in = setup_bit_in;
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mgl_prim1.setup_ena = setup_ena;
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mgl_prim1.tck = tck;
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setup_bit_out = mgl_prim1.setup_bit_out;
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trigger_level_match_out[] = ( mgl_prim1.trigger);
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END;
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--VALID FILE
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