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Fixed clocks

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This commit is contained in:
Adrian Scripca
2022-04-02 15:57:16 +03:00
parent d20be0fefc
commit f114ff0549
75 changed files with 407468 additions and 409289 deletions
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db/.cmp.kpt
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db/logic_util_heursitic.dat
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db/prev_cmp_spectrum.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828489178 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing started: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828489379 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\".\"; expecting a direction spectrum.sv(6) " "Verilog HDL syntax error at spectrum.sv(6) near text \".\"; expecting a direction" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648828489447 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648828489448 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489449 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828489902 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing ended: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828490035 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648903952061 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:52:31 2022 " "Processing started: Sat Apr 2 15:52:31 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648903952246 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"/\"; expecting \"end\" spectrum.sv(112) " "Verilog HDL syntax error at spectrum.sv(112) near text \"/\"; expecting \"end\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 112 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648903952313 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648903952313 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952314 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952316 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952316 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952317 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952317 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952318 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952319 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952321 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952323 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952323 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952324 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952324 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952325 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952327 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952328 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952328 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952330 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952331 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952331 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952332 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952332 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952333 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952333 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952357 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952357 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952358 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952359 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952359 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952360 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952361 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952361 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952364 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952365 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952365 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952366 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952368 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952369 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952369 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952370 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952370 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952372 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952372 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952373 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952373 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903952375 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903952375 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952375 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952375 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952376 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952376 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952378 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952378 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952380 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952380 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952383 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952680 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952681 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952682 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648903952751 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Apr 2 15:52:32 2022 " "Processing ended: Sat Apr 2 15:52:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648903952889 ""}
db/spectrum.(0).cnf.cdb
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:41 2022 " "Processing started: Fri Apr 1 18:55:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:43 2022 " "Processing ended: Fri Apr 1 18:55:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648904015094 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648904015094 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:53:34 2022 " "Processing started: Sat Apr 2 15:53:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648904015094 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648904015094 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648904015095 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648904016287 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648904016316 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:36 2022 " "Processing ended: Sat Apr 2 15:53:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648904016628 ""}
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db/spectrum.cmp.hdb
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db/spectrum.cmp.idb
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db/spectrum.cmp.rdb
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db/spectrum.eda.qmsg
+12 -12
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@@ -1,12 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:50 2022 " "Processing started: Fri Apr 1 18:55:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:53 2022 " "Processing ended: Fri Apr 1 18:55:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648904023213 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:53:43 2022 " "Processing started: Sat Apr 2 15:53:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648904023215 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024089 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024403 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024715 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025028 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025280 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025528 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025776 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904026024 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:46 2022 " "Processing ended: Sat Apr 2 15:53:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""}
db/spectrum.fit.qmsg
+72 -72
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db/spectrum.hier_info
+63 -63
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@@ -1,79 +1,79 @@
|spectrum
LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
LED[1] << <GND>
LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
LED[4] << <GND>
LED[5] << <GND>
LED[6] << <GND>
LED[7] << <GND>
CLOCK_50 => CLOCK_50.IN3
LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= <GND>
LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= <GND>
LED[5] <= <GND>
LED[6] <= <GND>
LED[7] <= <GND>
CLOCK_50 => CLOCK_50.IN2
KEY[0] => reset.IN1
KEY[1] => nNMI.IN1
PS2_CLK => PS2_CLK.IN1
PS2_DAT => PS2_DAT.IN1
I2C_SCLK <> ula:ula_.I2C_SCLK
I2C_SDAT <> ula:ula_.I2C_SDAT
AUD_XCK << ula:ula_.AUD_XCK
AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK
AUD_DACLRCK << ula:ula_.AUD_DACLRCK
AUD_BCLK << ula:ula_.AUD_BCLK
AUD_DACDAT << ula:ula_.AUD_DACDAT
AUD_XCK <= ula:ula_.AUD_XCK
AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK
AUD_DACLRCK <= ula:ula_.AUD_DACLRCK
AUD_BCLK <= ula:ula_.AUD_BCLK
AUD_DACDAT <= ula:ula_.AUD_DACDAT
AUD_ADCDAT => AUD_ADCDAT.IN1
VGA_R[0] << ula:ula_.VGA_R
VGA_R[1] << ula:ula_.VGA_R
VGA_R[2] << ula:ula_.VGA_R
VGA_R[3] << ula:ula_.VGA_R
VGA_G[0] << ula:ula_.VGA_G
VGA_G[1] << ula:ula_.VGA_G
VGA_G[2] << ula:ula_.VGA_G
VGA_G[3] << ula:ula_.VGA_G
VGA_B[0] << ula:ula_.VGA_B
VGA_B[1] << ula:ula_.VGA_B
VGA_B[2] << ula:ula_.VGA_B
VGA_B[3] << ula:ula_.VGA_B
VGA_HS << ula:ula_.VGA_HS
VGA_VS << ula:ula_.VGA_VS
VGA_R[0] <= ula:ula_.VGA_R
VGA_R[1] <= ula:ula_.VGA_R
VGA_R[2] <= ula:ula_.VGA_R
VGA_R[3] <= ula:ula_.VGA_R
VGA_G[0] <= ula:ula_.VGA_G
VGA_G[1] <= ula:ula_.VGA_G
VGA_G[2] <= ula:ula_.VGA_G
VGA_G[3] <= ula:ula_.VGA_G
VGA_B[0] <= ula:ula_.VGA_B
VGA_B[1] <= ula:ula_.VGA_B
VGA_B[2] <= ula:ula_.VGA_B
VGA_B[3] <= ula:ula_.VGA_B
VGA_HS <= ula:ula_.VGA_HS
VGA_VS <= ula:ula_.VGA_VS
SW[0] => ~NO_FANOUT~
SW[1] => LED[0].DATAIN
SW[1] => comb.OUTPUTSELECT
SW[2] => SW[2].IN1
SW[3] => ~NO_FANOUT~
GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
GPIO_1[25] << z80_top_direct_n:z80_.nHALT
GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
GPIO_1[27] << z80_top_direct_n:z80_.nWR
GPIO_1[28] << z80_top_direct_n:z80_.nRD
GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
GPIO_1[31] << z80_top_direct_n:z80_.nM1
GPIO_1[32] << <GND>
GPIO_1[33] << <GND>
buzzer_out << ula:ula_.beep
GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK
GPIO_1[25] <= z80_top_direct_n:z80_.nHALT
GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH
GPIO_1[27] <= z80_top_direct_n:z80_.nWR
GPIO_1[28] <= z80_top_direct_n:z80_.nRD
GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ
GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ
GPIO_1[31] <= z80_top_direct_n:z80_.nM1
GPIO_1[32] <= <GND>
GPIO_1[33] <= <GND>
buzzer_out <= ula:ula_.beep
raw_loader_in => raw_loader_in.IN1
db/spectrum.hif
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db/spectrum.ipinfo
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db/spectrum.map.bpm
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db/spectrum.map.hdb
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db/spectrum.map.kpt
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db/spectrum.map.qmsg
+159 -159
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db/spectrum.pplq.rdb
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db/spectrum.pre_map.hdb
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db/spectrum.root_partition.map.reg_db.cdb
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db/spectrum.routing.rdb
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db/spectrum.rtlv.hdb
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db/spectrum.sgdiff.cdb
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db/spectrum.sta.qmsg
+58 -58
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db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
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output_files/spectrum.asm.rpt
+6 -6
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@@ -1,5 +1,5 @@
Assembler report for spectrum
Fri Apr 1 18:55:43 2022
Sat Apr 2 15:53:36 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Apr 1 18:55:43 2022 ;
; Assembler Status ; Successful - Sat Apr 2 15:53:36 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ;
+----------------+-----------------------+
; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x0056423F ;
; Checksum ; 0x0056423F ;
; JTAG usercode ; 0x0056105B ;
; Checksum ; 0x0056105B ;
+----------------+-----------------------+
@@ -173,13 +173,13 @@ Default Value : On
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Fri Apr 1 18:55:41 2022
Info: Processing started: Sat Apr 2 15:53:34 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 385 megabytes
Info: Processing ended: Fri Apr 1 18:55:43 2022
Info: Processing ended: Sat Apr 2 15:53:36 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.done
+1 -1
View File
@@ -1 +1 @@
Fri Apr 1 18:55:53 2022
Sat Apr 2 15:53:46 2022
output_files/spectrum.eda.rpt
+4 -4
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum
Fri Apr 1 18:55:53 2022
Sat Apr 2 15:53:46 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Apr 1 18:55:53 2022 ;
; EDA Netlist Writer Status ; Successful - Sat Apr 2 15:53:46 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Fri Apr 1 18:55:50 2022
Info: Processing started: Sat Apr 2 15:53:43 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
@@ -100,7 +100,7 @@ Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 380 megabytes
Info: Processing ended: Fri Apr 1 18:55:53 2022
Info: Processing ended: Sat Apr 2 15:53:46 2022
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
output_files/spectrum.fit.rpt
+1521 -1515
View File
File diff suppressed because it is too large Load Diff
output_files/spectrum.fit.summary
+3 -3
View File
@@ -1,12 +1,12 @@
Fitter Status : Successful - Fri Apr 1 18:55:39 2022
Fitter Status : Successful - Sat Apr 2 15:53:32 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Device : EP4CE22F17C6
Timing Models : Final
Total logic elements : 2,396 / 22,320 ( 11 % )
Total combinational functions : 2,272 / 22,320 ( 10 % )
Total logic elements : 2,376 / 22,320 ( 11 % )
Total combinational functions : 2,258 / 22,320 ( 10 % )
Dedicated logic registers : 591 / 22,320 ( 3 % )
Total registers : 600
Total pins : 75 / 154 ( 49 % )
output_files/spectrum.flow.rpt
+13 -13
View File
@@ -1,5 +1,5 @@
Flow report for spectrum
Fri Apr 1 18:55:53 2022
Sat Apr 2 15:53:46 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,15 +40,15 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Fri Apr 1 18:55:53 2022 ;
; Flow Status ; Successful - Sat Apr 2 15:53:46 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Total logic elements ; 2,396 / 22,320 ( 11 % ) ;
; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ;
; Total logic elements ; 2,376 / 22,320 ( 11 % ) ;
; Total combinational functions ; 2,258 / 22,320 ( 10 % ) ;
; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ;
; Total registers ; 600 ;
; Total pins ; 75 / 154 ( 49 % ) ;
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/01/2022 18:55:04 ;
; Start date & time ; 04/02/2022 15:52:58 ;
; Main task ; Compilation ;
; Revision Name ; spectrum ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164882850457192
Value : 0.164890397819294
Default Value : --
Entity Name : --
Section Id : --
@@ -278,15 +278,15 @@ Section Id : --
; Flow Elapsed Time ;
+--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis
Elapsed Time : 00:00:13
Elapsed Time : 00:00:12
Average Processors Used : 1.0
Peak Virtual Memory : 441 MB
Total CPU Time (on all processors) : 00:00:13
Total CPU Time (on all processors) : 00:00:12
Module Name : Fitter
Elapsed Time : 00:00:21
Average Processors Used : 1.0
Peak Virtual Memory : 639 MB
Peak Virtual Memory : 634 MB
Total CPU Time (on all processors) : 00:00:21
Module Name : Assembler
@@ -298,8 +298,8 @@ Total CPU Time (on all processors) : 00:00:02
Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:04
Average Processors Used : 1.0
Peak Virtual Memory : 437 MB
Total CPU Time (on all processors) : 00:00:04
Peak Virtual Memory : 440 MB
Total CPU Time (on all processors) : 00:00:03
Module Name : EDA Netlist Writer
Elapsed Time : 00:00:03
@@ -308,10 +308,10 @@ Peak Virtual Memory : 372 MB
Total CPU Time (on all processors) : 00:00:03
Module Name : Total
Elapsed Time : 00:00:43
Elapsed Time : 00:00:42
Average Processors Used : --
Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:43
Total CPU Time (on all processors) : 00:00:41
+--------------------------------------------------------------------------------+
output_files/spectrum.jdi
+1 -1
View File
@@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="8380d13cf466db2d8054"/>
<hash md5_digest_80b="4f424ba9a0f5c16836a4"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+49 -49
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum
Fri Apr 1 18:55:17 2022
Sat Apr 2 15:53:10 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -70,13 +70,13 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Apr 1 18:55:17 2022 ;
; Analysis & Synthesis Status ; Successful - Sat Apr 2 15:53:10 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 2,537 ;
; Total combinational functions ; 2,269 ;
; Total logic elements ; 2,523 ;
; Total combinational functions ; 2,255 ;
; Dedicated logic registers ; 592 ;
; Total registers ; 592 ;
; Total pins ; 75 ;
@@ -935,16 +935,16 @@ Library :
+---------------------------------------------+---------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------+
; Estimated Total logic elements ; 2,537 ;
; Estimated Total logic elements ; 2,523 ;
; ; ;
; Total combinational functions ; 2269 ;
; Total combinational functions ; 2255 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 1640 ;
; -- 3 input functions ; 385 ;
; -- <=2 input functions ; 244 ;
; -- 4 input functions ; 1637 ;
; -- 3 input functions ; 372 ;
; -- <=2 input functions ; 246 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2216 ;
; -- normal mode ; 2202 ;
; -- arithmetic mode ; 53 ;
; ; ;
; Total registers ; 592 ;
@@ -959,8 +959,8 @@ Library :
; ; ;
; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ;
; Maximum fan-out ; 436 ;
; Total fan-out ; 11524 ;
; Average fan-out ; 3.74 ;
; Total fan-out ; 11477 ;
; Average fan-out ; 3.75 ;
+---------------------------------------------+---------------------------------+
@@ -968,7 +968,7 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 2269 (98)
LC Combinationals : 2255 (86)
LC Registers : 592 (0)
Memory Bits : 524288
DSP Elements : 0
@@ -1028,7 +1028,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
Library Name : work
Compilation Hierarchy Node : |ram32:ram1|
LC Combinationals : 16 (0)
LC Combinationals : 24 (0)
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
@@ -1040,7 +1040,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 16 (0)
LC Combinationals : 24 (0)
LC Registers : 4 (0)
Memory Bits : 262144
DSP Elements : 0
@@ -1052,7 +1052,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
Library Name : work
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
LC Combinationals : 16 (0)
LC Combinationals : 24 (0)
LC Registers : 4 (4)
Memory Bits : 262144
DSP Elements : 0
@@ -1088,7 +1088,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
Library Name : work
Compilation Hierarchy Node : |mux_6nb:mux2|
LC Combinationals : 8 (8)
LC Combinationals : 16 (16)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1160,7 +1160,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|clocks:clocks_
Library Name : work
Compilation Hierarchy Node : |i2c_loader:i2c_loader_|
LC Combinationals : 81 (81)
LC Combinationals : 80 (80)
LC Registers : 34 (34)
Memory Bits : 0
DSP Elements : 0
@@ -1244,7 +1244,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_
Library Name : work
Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_|
LC Combinationals : 150 (150)
LC Combinationals : 151 (151)
LC Registers : 43 (43)
Memory Bits : 0
DSP Elements : 0
@@ -1256,7 +1256,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_
Library Name : work
Compilation Hierarchy Node : |z80_top_direct_n:z80_|
LC Combinationals : 1733 (2)
LC Combinationals : 1723 (2)
LC Registers : 362 (1)
Memory Bits : 0
DSP Elements : 0
@@ -1268,7 +1268,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_
Library Name : work
Compilation Hierarchy Node : |address_latch:address_latch_|
LC Combinationals : 48 (16)
LC Combinationals : 46 (16)
LC Registers : 16 (16)
Memory Bits : 0
DSP Elements : 0
@@ -1280,7 +1280,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre
Library Name : work
Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec|
LC Combinationals : 32 (14)
LC Combinationals : 30 (13)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1292,7 +1292,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre
Library Name : work
Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0|
LC Combinationals : 4 (4)
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1376,7 +1376,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres
Library Name : work
Compilation Hierarchy Node : |alu:alu_|
LC Combinationals : 130 (77)
LC Combinationals : 130 (76)
LC Registers : 20 (20)
Memory Bits : 0
DSP Elements : 0
@@ -1400,7 +1400,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se
Library Name : work
Compilation Hierarchy Node : |alu_core:b2v_core|
LC Combinationals : 20 (0)
LC Combinationals : 21 (0)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1424,7 +1424,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
Library Name : work
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1|
LC Combinationals : 4 (4)
LC Combinationals : 5 (5)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1544,7 +1544,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con
Library Name : work
Compilation Hierarchy Node : |alu_flags:alu_flags_|
LC Combinationals : 63 (63)
LC Combinationals : 60 (60)
LC Registers : 10 (10)
Memory Bits : 0
DSP Elements : 0
@@ -1604,7 +1604,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_
Library Name : work
Compilation Hierarchy Node : |data_switch_mask:sw1_|
LC Combinationals : 2 (2)
LC Combinationals : 3 (3)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1628,7 +1628,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode
Library Name : work
Compilation Hierarchy Node : |execute:execute_|
LC Combinationals : 933 (933)
LC Combinationals : 926 (926)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1712,7 +1712,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con
Library Name : work
Compilation Hierarchy Node : |reg_file:reg_file_|
LC Combinationals : 282 (273)
LC Combinationals : 283 (273)
LC Registers : 224 (0)
Memory Bits : 0
DSP Elements : 0
@@ -1748,7 +1748,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi|
LC Combinationals : 8 (8)
LC Combinationals : 6 (6)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
@@ -1868,7 +1868,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_hi|
LC Combinationals : 0 (0)
LC Combinationals : 2 (2)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
@@ -2048,7 +2048,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
Library Name : work
Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo|
LC Combinationals : 0 (0)
LC Combinationals : 1 (1)
LC Registers : 8 (8)
Memory Bits : 0
DSP Elements : 0
@@ -2241,9 +2241,9 @@ state.Idle : 1
; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_busrq_ALTERA_SYNTHESIZED ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_b[0] ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_b[0] ; Stuck at GND due to stuck port data_in ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ;
; ula:ula_|pcm_outr[14] ; Merged with ula:ula_|pcm_outl[14] ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ;
; ula:ula_|pcm_outr[13] ; Merged with ula:ula_|pcm_outl[13] ;
; ula:ula_|pcm_outr[12] ; Merged with ula:ula_|pcm_outl[12] ;
; ula:ula_|i2c_loader:i2c_loader_|retries ; Stuck at GND due to stuck port data_in ;
@@ -2290,7 +2290,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
+----------------------------------------------------------+---------+
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ;
; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ;
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 138 ;
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 139 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ;
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ;
@@ -2308,40 +2308,40 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ;
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][0] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ;
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ;
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 61 ;
; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ;
; z80_top_direct_n:z80_|fpga_reset ; 2 ;
; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ;
@@ -4948,7 +4948,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Fri Apr 1 18:55:04 2022
Info: Processing started: Sat Apr 2 15:52:58 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
@@ -5389,17 +5389,17 @@ Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Warning (21074): Design contains 2 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "SW[0]"
Warning (15610): No output dependent on input pin "SW[3]"
Info (21057): Implemented 2747 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 2734 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 11 input pins
Info (21059): Implemented 62 output pins
Info (21060): Implemented 2 bidirectional pins
Info (21061): Implemented 2607 logic cells
Info (21061): Implemented 2594 logic cells
Info (21064): Implemented 64 RAM segments
Info (21065): Implemented 1 PLLs
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings
Info: Peak virtual memory: 441 megabytes
Info: Processing ended: Fri Apr 1 18:55:17 2022
Info: Elapsed time: 00:00:13
Info: Processing ended: Sat Apr 2 15:53:10 2022
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:13
output_files/spectrum.map.summary
+3 -3
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@@ -1,10 +1,10 @@
Analysis & Synthesis Status : Successful - Fri Apr 1 18:55:17 2022
Analysis & Synthesis Status : Successful - Sat Apr 2 15:53:10 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Total logic elements : 2,537
Total combinational functions : 2,269
Total logic elements : 2,523
Total combinational functions : 2,255
Dedicated logic registers : 592
Total registers : 592
Total pins : 75
output_files/spectrum.sof
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output_files/spectrum.sta.rpt
+20262 -20256
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output_files/spectrum.sta.summary
+49 -49
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@@ -3,43 +3,43 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -18.123
TNS : -549.338
Slack : -18.425
TNS : -546.891
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -7.533
TNS : -284.813
Slack : -6.923
TNS : -271.506
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.740
TNS : -42.810
Slack : -4.745
TNS : -42.191
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.914
TNS : -2.914
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.210
TNS : 0.000
Slack : -2.915
TNS : -2.915
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.342
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.344
Slack : 0.342
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.357
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.517
TNS : 0.000
Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -6.223
TNS : -459.348
Slack : -6.263
TNS : -464.840
Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.698
Slack : 3.657
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -51,7 +51,7 @@ Slack : 19.602
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 20.595
Slack : 20.597
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
@@ -59,43 +59,43 @@ Slack : 35.503
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -17.311
TNS : -526.609
Slack : -17.572
TNS : -524.603
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -6.686
TNS : -253.661
Slack : -6.192
TNS : -241.805
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.428
TNS : -40.009
Slack : -4.414
TNS : -39.436
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.785
TNS : -2.785
Slack : -2.786
TNS : -2.786
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.297
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.298
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.300
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.304
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.311
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.467
TNS : 0.000
Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -5.744
TNS : -423.582
Slack : -5.773
TNS : -427.930
Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.374
Slack : 3.347
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
@@ -103,11 +103,11 @@ Slack : 9.489
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : 19.600
Slack : 19.601
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 20.591
Slack : 20.590
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
@@ -115,24 +115,24 @@ Slack : 35.491
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -14.971
TNS : -442.545
Slack : -15.171
TNS : -440.252
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
Slack : -4.979
TNS : -171.124
Slack : -4.743
TNS : -163.399
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -3.775
TNS : -35.541
Slack : -3.815
TNS : -35.260
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.784
TNS : -2.784
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : -0.053
TNS : -0.089
Slack : 0.112
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.177
@@ -147,11 +147,11 @@ Slack : 0.186
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.693
TNS : -358.284
Slack : -4.728
TNS : -362.420
Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
Slack : 2.518
Slack : 2.503
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
simulation/modelsim/spectrum.vo
+51409 -51659
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simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
+51409 -51659
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simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
+43482 -43687
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simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
+51409 -51659
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simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
+44747 -44952
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simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
+51409 -51659
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simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
+44105 -44310
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simulation/modelsim/spectrum_modelsim.xrf
+2402 -2415
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simulation/modelsim/spectrum_v.sdo
+44747 -44952
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spectrum.qsf
+1
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@@ -462,4 +462,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to buzzer_out
set_location_assignment PIN_B6 -to raw_loader_in
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to raw_loader_in
set_global_assignment -name QIP_FILE ram_video.qip
set_global_assignment -name CDF_FILE output_files/spectrum.cdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
spectrum.sv
+1 -2
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@@ -109,7 +109,6 @@ begin
3'b001: begin
// Normally data supplied by the ULA
D[7:0] = ula_data;
/*
// Kempston joystick at the IO address 0x1F; active bits are high:
// FIRE UP DOWN LEFT RIGHT
@@ -129,7 +128,7 @@ end
// ----------------------------------------------------
wire[7:0] rom_data;
rom0 rom(
.clock(CLOCK_50),
.clock(clk_vram),
.address(A),
.q(rom_data)
);