Working version with loader from schmidt trigger

db/altsyncram_q7c2.tdf

@@ -0,0 +1,766 @@
+--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK1" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION decode_jsa (data[0..0], enable)
+RETURNS ( eq[1..0]);
+FUNCTION decode_c8a (data[0..0])
+RETURNS ( eq[1..0]);
+FUNCTION mux_3nb (data[15..0], sel[0..0])
+RETURNS ( result[7..0]);
+FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 16 reg 4 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_q7c2
+( 
+	address_a[13..0]	:	input;
+	address_b[13..0]	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	data_a[7..0]	:	input;
+	data_b[7..0]	:	input;
+	q_a[7..0]	:	output;
+	q_b[7..0]	:	output;
+	wren_a	:	input;
+	wren_b	:	input;
+) 
+VARIABLE 
+	address_reg_a[0..0] : dffe;
+	address_reg_b[0..0] : dffe;
+	out_address_reg_a[0..0] : dffe;
+	out_address_reg_b[0..0] : dffe;
+	decode2 : decode_jsa;
+	decode3 : decode_jsa;
+	rden_decode_a : decode_c8a;
+	rden_decode_b : decode_c8a;
+	mux4 : mux_3nb;
+	mux5 : mux_3nb;
+	ram_block1a0 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a10 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a11 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a12 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a13 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a14 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a15 : cycloneive_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "bidir_dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 8192,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 16383,
+			PORT_A_LOGICAL_RAM_DEPTH = 16384,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_IN_CLOCK = "clock1",
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 8192,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 16383,
+			PORT_B_LOGICAL_RAM_DEPTH = 16384,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_sel[0..0]	: WIRE;
+	address_a_wire[13..0]	: WIRE;
+	address_b_sel[0..0]	: WIRE;
+	address_b_wire[13..0]	: WIRE;
+	w_addr_val_a2w[0..0]	: WIRE;
+	w_addr_val_a7w[0..0]	: WIRE;
+	w_addr_val_b4w[0..0]	: WIRE;
+	w_addr_val_b8w[0..0]	: WIRE;
+	wren_decode_addr_sel_a[0..0]	: WIRE;
+	wren_decode_addr_sel_b[0..0]	: WIRE;
+
+BEGIN 
+	address_reg_a[].clk = clock0;
+	address_reg_a[].d = address_a_sel[];
+	address_reg_b[].clk = clock1;
+	address_reg_b[].d = address_b_sel[];
+	out_address_reg_a[].clk = clock0;
+	out_address_reg_a[].d = address_reg_a[].q;
+	out_address_reg_b[].clk = clock1;
+	out_address_reg_b[].d = address_reg_b[].q;
+	decode2.data[] = w_addr_val_a2w[];
+	decode2.enable = wren_a;
+	decode3.data[] = w_addr_val_b4w[];
+	decode3.enable = wren_b;
+	rden_decode_a.data[] = w_addr_val_a7w[];
+	rden_decode_b.data[] = w_addr_val_b8w[];
+	mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]);
+	mux4.sel[] = out_address_reg_a[].q;
+	mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]);
+	mux5.sel[] = out_address_reg_b[].q;
+	ram_block1a[15..0].clk0 = clock0;
+	ram_block1a[15..0].clk1 = clock1;
+	ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]);
+	ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]);
+	ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[0..0]);
+	ram_block1a[9].portadatain[] = ( data_a[1..1]);
+	ram_block1a[10].portadatain[] = ( data_a[2..2]);
+	ram_block1a[11].portadatain[] = ( data_a[3..3]);
+	ram_block1a[12].portadatain[] = ( data_a[4..4]);
+	ram_block1a[13].portadatain[] = ( data_a[5..5]);
+	ram_block1a[14].portadatain[] = ( data_a[6..6]);
+	ram_block1a[15].portadatain[] = ( data_a[7..7]);
+	ram_block1a[15..0].portare = B"1111111111111111";
+	ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
+	ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[0].portbdatain[] = ( data_b[0..0]);
+	ram_block1a[1].portbdatain[] = ( data_b[1..1]);
+	ram_block1a[2].portbdatain[] = ( data_b[2..2]);
+	ram_block1a[3].portbdatain[] = ( data_b[3..3]);
+	ram_block1a[4].portbdatain[] = ( data_b[4..4]);
+	ram_block1a[5].portbdatain[] = ( data_b[5..5]);
+	ram_block1a[6].portbdatain[] = ( data_b[6..6]);
+	ram_block1a[7].portbdatain[] = ( data_b[7..7]);
+	ram_block1a[8].portbdatain[] = ( data_b[0..0]);
+	ram_block1a[9].portbdatain[] = ( data_b[1..1]);
+	ram_block1a[10].portbdatain[] = ( data_b[2..2]);
+	ram_block1a[11].portbdatain[] = ( data_b[3..3]);
+	ram_block1a[12].portbdatain[] = ( data_b[4..4]);
+	ram_block1a[13].portbdatain[] = ( data_b[5..5]);
+	ram_block1a[14].portbdatain[] = ( data_b[6..6]);
+	ram_block1a[15].portbdatain[] = ( data_b[7..7]);
+	ram_block1a[15..0].portbre = B"1111111111111111";
+	ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
+	address_a_sel[0..0] = address_a[13..13];
+	address_a_wire[] = address_a[];
+	address_b_sel[0..0] = address_b[13..13];
+	address_b_wire[] = address_b[];
+	q_a[] = mux4.result[];
+	q_b[] = mux5.result[];
+	w_addr_val_a2w[0..0] = address_a_wire[13..13];
+	w_addr_val_a7w[] = wren_decode_addr_sel_a[];
+	w_addr_val_b4w[0..0] = address_b_wire[13..13];
+	w_addr_val_b8w[] = wren_decode_addr_sel_b[];
+	wren_decode_addr_sel_a[0..0] = address_a_wire[13..13];
+	wren_decode_addr_sel_b[0..0] = address_b_wire[13..13];
+END;
+--VALID FILE

db/pll_altpll.v

@@ -1,4 +1,4 @@
-//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=143 clk0_duty_cycle=50 clk0_multiply_by=72 clk0_phase_shift="0" clk1_divide_by=25 clk1_duty_cycle=50 clk1_multiply_by=7 clk1_phase_shift="0" clk2_divide_by=25 clk2_duty_cycle=50 clk2_multiply_by=12 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2000 clk0_duty_cycle=50 clk0_multiply_by=1007 clk0_phase_shift="0" clk1_divide_by=25 clk1_duty_cycle=50 clk1_multiply_by=7 clk1_phase_shift="0" clk2_divide_by=25 clk2_duty_cycle=50 clk2_multiply_by=12 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
 //VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ  VERSION_END
 //CBXI_INSTANCE_NAME="spectrum_ula_ula_pll_pll_altpll_altpll_component"
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
@@ -80,9 +80,9 @@ module  pll_altpll
 	);
 	defparam
 		pll1.bandwidth_type = "auto",
-		pll1.clk0_divide_by = 143,
+		pll1.clk0_divide_by = 2000,
 		pll1.clk0_duty_cycle = 50,
-		pll1.clk0_multiply_by = 72,
+		pll1.clk0_multiply_by = 1007,
 		pll1.clk0_phase_shift = "0",
 		pll1.clk1_divide_by = 25,
 		pll1.clk1_duty_cycle = 50,

db/spectrum.asm.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724654189 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724654190 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:04:14 2022 " "Processing started: Thu Mar 31 14:04:14 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724654190 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648724654190 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr  1 18:55:41 2022 " "Processing started: Fri Apr  1 18:55:41 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648724654190 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648724655397 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648724655426 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:15 2022 " "Processing ended: Thu Mar 31 14:04:15 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724655745 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648724655745 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr  1 18:55:43 2022 " "Processing ended: Fri Apr  1 18:55:43 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""}

db/spectrum.cmp.logdb

@@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000
 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
 IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
 IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,74;9;74;0;0;74;74;0;74;74;0;0;0;0;40;0;0;40;0;0;2;0;0;0;0;0;0;74;0;0,
+IO_RULES_MATRIX,Total Pass,75;9;75;0;0;75;75;0;75;75;0;0;0;0;41;0;0;41;0;0;2;0;0;0;0;0;0;75;0;0,
 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;65;0;74;74;0;0;74;0;0;74;74;74;74;34;74;74;34;74;74;72;74;74;74;74;74;74;0;74;74,
+IO_RULES_MATRIX,Total Inapplicable,0;66;0;75;75;0;0;75;0;0;75;75;75;75;34;75;75;34;75;75;73;75;75;75;75;75;75;0;75;75,
 IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
 IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
@@ -102,10 +102,11 @@ IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inap
 IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,PS2_DAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,PS2_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,AUD_ADCDAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
 IO_RULES_SUMMARY,Total I/O Rules,30,

db/spectrum.eda.qmsg

@@ -1,12 +1,12 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648724662545 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 31 14:04:22 2022 " "Processing started: Thu Mar 31 14:04:22 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648724662545 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr  1 18:55:50 2022 " "Processing started: Fri Apr  1 18:55:50 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648724662546 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724663449 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724663768 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664086 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664404 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664660 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724664912 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724665163 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648724665416 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 31 14:04:25 2022 " "Processing ended: Thu Mar 31 14:04:25 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648724665513 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr  1 18:55:53 2022 " "Processing ended: Fri Apr  1 18:55:53 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""}

db/spectrum.hier_info

@@ -1,12 +1,12 @@
 |spectrum
-LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
+LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
-LED[1] <= <GND>
+LED[1] << <GND>
-LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
+LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE
-LED[3] <= <GND>
+LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
-LED[4] <= <GND>
+LED[4] << <GND>
-LED[5] <= <GND>
+LED[5] << <GND>
-LED[6] <= <GND>
+LED[6] << <GND>
-LED[7] <= <GND>
+LED[7] << <GND>
 CLOCK_50 => CLOCK_50.IN3
 KEY[0] => reset.IN1
 KEY[1] => nNMI.IN1
@@ -14,66 +14,67 @@ PS2_CLK => PS2_CLK.IN1
 PS2_DAT => PS2_DAT.IN1
 I2C_SCLK <> ula:ula_.I2C_SCLK
 I2C_SDAT <> ula:ula_.I2C_SDAT
-AUD_XCK <= ula:ula_.AUD_XCK
+AUD_XCK << ula:ula_.AUD_XCK
-AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK
+AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK
-AUD_DACLRCK <= ula:ula_.AUD_DACLRCK
+AUD_DACLRCK << ula:ula_.AUD_DACLRCK
-AUD_BCLK <= ula:ula_.AUD_BCLK
+AUD_BCLK << ula:ula_.AUD_BCLK
-AUD_DACDAT <= ula:ula_.AUD_DACDAT
+AUD_DACDAT << ula:ula_.AUD_DACDAT
 AUD_ADCDAT => AUD_ADCDAT.IN1
-VGA_R[0] <= ula:ula_.VGA_R
+VGA_R[0] << ula:ula_.VGA_R
-VGA_R[1] <= ula:ula_.VGA_R
+VGA_R[1] << ula:ula_.VGA_R
-VGA_R[2] <= ula:ula_.VGA_R
+VGA_R[2] << ula:ula_.VGA_R
-VGA_R[3] <= ula:ula_.VGA_R
+VGA_R[3] << ula:ula_.VGA_R
-VGA_G[0] <= ula:ula_.VGA_G
+VGA_G[0] << ula:ula_.VGA_G
-VGA_G[1] <= ula:ula_.VGA_G
+VGA_G[1] << ula:ula_.VGA_G
-VGA_G[2] <= ula:ula_.VGA_G
+VGA_G[2] << ula:ula_.VGA_G
-VGA_G[3] <= ula:ula_.VGA_G
+VGA_G[3] << ula:ula_.VGA_G
-VGA_B[0] <= ula:ula_.VGA_B
+VGA_B[0] << ula:ula_.VGA_B
-VGA_B[1] <= ula:ula_.VGA_B
+VGA_B[1] << ula:ula_.VGA_B
-VGA_B[2] <= ula:ula_.VGA_B
+VGA_B[2] << ula:ula_.VGA_B
-VGA_B[3] <= ula:ula_.VGA_B
+VGA_B[3] << ula:ula_.VGA_B
-VGA_HS <= ula:ula_.VGA_HS
+VGA_HS << ula:ula_.VGA_HS
-VGA_VS <= ula:ula_.VGA_VS
+VGA_VS << ula:ula_.VGA_VS
 SW[0] => ~NO_FANOUT~
 SW[1] => LED[0].DATAIN
 SW[1] => comb.OUTPUTSELECT
 SW[2] => SW[2].IN1
 SW[3] => ~NO_FANOUT~
-GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK
+GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
-GPIO_1[25] <= z80_top_direct_n:z80_.nHALT
+GPIO_1[25] << z80_top_direct_n:z80_.nHALT
-GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH
+GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
-GPIO_1[27] <= z80_top_direct_n:z80_.nWR
+GPIO_1[27] << z80_top_direct_n:z80_.nWR
-GPIO_1[28] <= z80_top_direct_n:z80_.nRD
+GPIO_1[28] << z80_top_direct_n:z80_.nRD
-GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ
+GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
-GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ
+GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
-GPIO_1[31] <= z80_top_direct_n:z80_.nM1
+GPIO_1[31] << z80_top_direct_n:z80_.nM1
-GPIO_1[32] <= <GND>
+GPIO_1[32] << <GND>
-GPIO_1[33] <= <GND>
+GPIO_1[33] << <GND>
-buzzer_out <= ula:ula_.beep
+buzzer_out << ula:ula_.beep
+raw_loader_in => raw_loader_in.IN1
 
 
 |spectrum|rom0:rom
@@ -2027,7 +2028,7 @@ D[2] => border[2].DATAIN
 D[3] => beep.IN1
 D[3] => pcm_outl.DATAB
 D[3] => pcm_outr.DATAB
-D[4] => beep.IN1
+D[4] => beep.IN0
 D[4] => pcm_outl.DATAB
 D[4] => pcm_outr.DATAB
 D[5] => ~NO_FANOUT~
@@ -2076,6 +2077,8 @@ AUD_DACDAT <= i2s_intf:i2s_intf_.I2S_DOUT
 AUD_ADCDAT => AUD_ADCDAT.IN1
 beeper <= beeper~reg0.DB_MAX_OUTPUT_PORT_TYPE
 beep <= beep~reg0.DB_MAX_OUTPUT_PORT_TYPE
+raw_loader_in => beep.IN1
+raw_loader_in => ula_data.DATAB
 VGA_R[0] <= video:video_.VGA_R[0]
 VGA_R[1] <= video:video_.VGA_R[1]
 VGA_R[2] <= video:video_.VGA_R[2]

db/spectrum.lpc.html

@@ -1409,7 +1409,7 @@
 </TR>
 <TR >
 <TD >ula_</TD>
-<TD >39</TD>
+<TD >40</TD>
 <TD >2</TD>
 <TD >3</TD>
 <TD >2</TD>

db/spectrum.lpc.txt

@@ -1307,7 +1307,7 @@ Input only Bidir  : 0
 Output only Bidir : 0
 
 Hierarchy         : ula_
-Input             : 39
+Input             : 40
 Constant Input    : 2
 Unused Input      : 3
 Floating Input    : 2

greybox_tmp/cbx_args.txt

@@ -1,16 +1,70 @@
-ADDRESS_ACLR_A=NONE
+BANDWIDTH_TYPE=AUTO
-CLOCK_ENABLE_INPUT_A=BYPASS
+CLK0_DIVIDE_BY=143
-CLOCK_ENABLE_OUTPUT_A=BYPASS
+CLK0_DUTY_CYCLE=50
-INIT_FILE=./rom/gw03.hex
+CLK0_MULTIPLY_BY=72
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=25
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=7
+CLK1_PHASE_SHIFT=0
+CLK2_DIVIDE_BY=25
+CLK2_DUTY_CYCLE=50
+CLK2_MULTIPLY_BY=12
+CLK2_PHASE_SHIFT=0
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
 INTENDED_DEVICE_FAMILY="Cyclone IV E"
-NUMWORDS_A=16384
+LPM_TYPE=altpll
-OPERATION_MODE=ROM
+OPERATION_MODE=NORMAL
-OUTDATA_ACLR_A=NONE
+PLL_TYPE=AUTO
-OUTDATA_REG_A=CLOCK0
+PORT_ACTIVECLOCK=PORT_UNUSED
-WIDTHAD_A=14
+PORT_ARESET=PORT_UNUSED
-WIDTH_A=8
+PORT_CLKBAD0=PORT_UNUSED
-WIDTH_BYTEENA_A=1
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_USED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_USED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+SELF_RESET_ON_LOSS_LOCK=OFF
+WIDTH_CLOCK=5
 DEVICE_FAMILY="Cyclone IV E"
-address_a
+CBX_AUTO_BLACKBOX=ALL
-clock0
+inclk
-q_a
+inclk
+clk
+clk
+clk
+locked

output_files/greybox_tmp/cbx_args.txt

@@ -1,60 +1,36 @@
-BANDWIDTH_TYPE=AUTO
+ADDRESS_REG_B=CLOCK1
-CLK0_DIVIDE_BY=2000
+CLOCK_ENABLE_INPUT_A=BYPASS
-CLK0_DUTY_CYCLE=50
+CLOCK_ENABLE_INPUT_B=BYPASS
-CLK0_MULTIPLY_BY=1007
+CLOCK_ENABLE_OUTPUT_A=BYPASS
-CLK0_PHASE_SHIFT=0
+CLOCK_ENABLE_OUTPUT_B=BYPASS
-COMPENSATE_CLOCK=CLK0
+INDATA_REG_B=CLOCK1
-INCLK0_INPUT_FREQUENCY=20000
 INTENDED_DEVICE_FAMILY="Cyclone IV E"
-LPM_TYPE=altpll
+LPM_TYPE=altsyncram
-OPERATION_MODE=NORMAL
+NUMWORDS_A=16384
-PLL_TYPE=AUTO
+NUMWORDS_B=16384
-PORT_ACTIVECLOCK=PORT_UNUSED
+OPERATION_MODE=BIDIR_DUAL_PORT
-PORT_ARESET=PORT_UNUSED
+OUTDATA_ACLR_A=NONE
-PORT_CLKBAD0=PORT_UNUSED
+OUTDATA_ACLR_B=NONE
-PORT_CLKBAD1=PORT_UNUSED
+OUTDATA_REG_A=CLOCK0
-PORT_CLKLOSS=PORT_UNUSED
+OUTDATA_REG_B=CLOCK1
-PORT_CLKSWITCH=PORT_UNUSED
+POWER_UP_UNINITIALIZED=FALSE
-PORT_CONFIGUPDATE=PORT_UNUSED
+READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
-PORT_FBIN=PORT_UNUSED
+READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
-PORT_INCLK0=PORT_USED
+WIDTHAD_A=14
-PORT_INCLK1=PORT_UNUSED
+WIDTHAD_B=14
-PORT_LOCKED=PORT_USED
+WIDTH_A=8
-PORT_PFDENA=PORT_UNUSED
+WIDTH_B=8
-PORT_PHASECOUNTERSELECT=PORT_UNUSED
+WIDTH_BYTEENA_A=1
-PORT_PHASEDONE=PORT_UNUSED
+WIDTH_BYTEENA_B=1
-PORT_PHASESTEP=PORT_UNUSED
+WRCONTROL_WRADDRESS_REG_B=CLOCK1
-PORT_PHASEUPDOWN=PORT_UNUSED
-PORT_PLLENA=PORT_UNUSED
-PORT_SCANACLR=PORT_UNUSED
-PORT_SCANCLK=PORT_UNUSED
-PORT_SCANCLKENA=PORT_UNUSED
-PORT_SCANDATA=PORT_UNUSED
-PORT_SCANDATAOUT=PORT_UNUSED
-PORT_SCANDONE=PORT_UNUSED
-PORT_SCANREAD=PORT_UNUSED
-PORT_SCANWRITE=PORT_UNUSED
-PORT_clk0=PORT_USED
-PORT_clk1=PORT_UNUSED
-PORT_clk2=PORT_UNUSED
-PORT_clk3=PORT_UNUSED
-PORT_clk4=PORT_UNUSED
-PORT_clk5=PORT_UNUSED
-PORT_clkena0=PORT_UNUSED
-PORT_clkena1=PORT_UNUSED
-PORT_clkena2=PORT_UNUSED
-PORT_clkena3=PORT_UNUSED
-PORT_clkena4=PORT_UNUSED
-PORT_clkena5=PORT_UNUSED
-PORT_extclk0=PORT_UNUSED
-PORT_extclk1=PORT_UNUSED
-PORT_extclk2=PORT_UNUSED
-PORT_extclk3=PORT_UNUSED
-SELF_RESET_ON_LOSS_LOCK=OFF
-WIDTH_CLOCK=5
 DEVICE_FAMILY="Cyclone IV E"
-CBX_AUTO_BLACKBOX=ALL
+address_a
-inclk
+address_b
-inclk
+clock0
-clk
+clock1
-locked
+data_a
+data_b
+wren_a
+wren_b
+q_a
+q_b

output_files/spectrum.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for spectrum
-Thu Mar 31 14:04:15 2022
+Fri Apr  1 18:55:43 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -37,7 +37,7 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Mar 31 14:04:15 2022 ;
+; Assembler Status      ; Successful - Fri Apr  1 18:55:43 2022 ;
 ; Revision Name         ; spectrum                              ;
 ; Top-level Entity Name ; spectrum                              ;
 ; Family                ; Cyclone IV E                          ;
@@ -162,8 +162,8 @@ Default Value : On
 ; Option         ; Setting               ;
 +----------------+-----------------------+
 ; Device         ; EP4CE22F17C6          ;
-; JTAG usercode  ; 0x00559289            ;
+; JTAG usercode  ; 0x0056423F            ;
-; Checksum       ; 0x00559289            ;
+; Checksum       ; 0x0056423F            ;
 +----------------+-----------------------+
 
 
@@ -173,14 +173,14 @@ Default Value : On
 Info: *******************************************************************
 Info: Running Quartus II 32-bit Assembler
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Mar 31 14:04:14 2022
+    Info: Processing started: Fri Apr  1 18:55:41 2022
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 375 megabytes
+    Info: Peak virtual memory: 385 megabytes
-    Info: Processing ended: Thu Mar 31 14:04:15 2022
+    Info: Processing ended: Fri Apr  1 18:55:43 2022
-    Info: Elapsed time: 00:00:01
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 
 

output_files/spectrum.done

@@ -1 +1 @@
-Thu Mar 31 14:04:25 2022
+Fri Apr  1 18:55:53 2022

output_files/spectrum.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for spectrum
-Thu Mar 31 14:04:25 2022
+Fri Apr  1 18:55:53 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -36,7 +36,7 @@ applicable agreement for further details.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Mar 31 14:04:25 2022 ;
+; EDA Netlist Writer Status ; Successful - Fri Apr  1 18:55:53 2022 ;
 ; Revision Name             ; spectrum                              ;
 ; Top-level Entity Name     ; spectrum                              ;
 ; Family                    ; Cyclone IV E                          ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
 Info: *******************************************************************
 Info: Running Quartus II 32-bit EDA Netlist Writer
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Mar 31 14:04:22 2022
+    Info: Processing started: Fri Apr  1 18:55:50 2022
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
 Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
@@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
 Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
 Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 383 megabytes
+    Info: Peak virtual memory: 380 megabytes
-    Info: Processing ended: Thu Mar 31 14:04:25 2022
+    Info: Processing ended: Fri Apr  1 18:55:53 2022
     Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:03
 

output_files/spectrum.fit.summary

@@ -1,15 +1,15 @@
-Fitter Status : Successful - Thu Mar 31 14:04:11 2022
+Fitter Status : Successful - Fri Apr  1 18:55:39 2022
 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
 Revision Name : spectrum
 Top-level Entity Name : spectrum
 Family : Cyclone IV E
 Device : EP4CE22F17C6
 Timing Models : Final
-Total logic elements : 2,383 / 22,320 ( 11 % )
+Total logic elements : 2,396 / 22,320 ( 11 % )
-    Total combinational functions : 2,265 / 22,320 ( 10 % )
+    Total combinational functions : 2,272 / 22,320 ( 10 % )
     Dedicated logic registers : 591 / 22,320 ( 3 % )
 Total registers : 600
-Total pins : 74 / 154 ( 48 % )
+Total pins : 75 / 154 ( 49 % )
 Total virtual pins : 0
 Total memory bits : 524,288 / 608,256 ( 86 % )
 Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )

output_files/spectrum.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for spectrum
-Thu Mar 31 14:04:25 2022
+Fri Apr  1 18:55:53 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -40,18 +40,18 @@ applicable agreement for further details.
 +---------------------------------------------------------------------------------+
 ; Flow Summary                                                                    ;
 +------------------------------------+--------------------------------------------+
-; Flow Status                        ; Successful - Thu Mar 31 14:04:25 2022      ;
+; Flow Status                        ; Successful - Fri Apr  1 18:55:53 2022      ;
 ; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
 ; Revision Name                      ; spectrum                                   ;
 ; Top-level Entity Name              ; spectrum                                   ;
 ; Family                             ; Cyclone IV E                               ;
 ; Device                             ; EP4CE22F17C6                               ;
 ; Timing Models                      ; Final                                      ;
-; Total logic elements               ; 2,383 / 22,320 ( 11 % )                    ;
+; Total logic elements               ; 2,396 / 22,320 ( 11 % )                    ;
-;     Total combinational functions  ; 2,265 / 22,320 ( 10 % )                    ;
+;     Total combinational functions  ; 2,272 / 22,320 ( 10 % )                    ;
 ;     Dedicated logic registers      ; 591 / 22,320 ( 3 % )                       ;
 ; Total registers                    ; 600                                        ;
-; Total pins                         ; 74 / 154 ( 48 % )                          ;
+; Total pins                         ; 75 / 154 ( 49 % )                          ;
 ; Total virtual pins                 ; 0                                          ;
 ; Total memory bits                  ; 524,288 / 608,256 ( 86 % )                 ;
 ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                            ;
@@ -64,7 +64,7 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 03/31/2022 14:03:37 ;
+; Start date & time ; 04/01/2022 18:55:04 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; spectrum            ;
 +-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
 ; Flow Non-Default Global Settings                                               ;
 +--------------------------------------------------------------------------------+
 Assignment Name : COMPILER_SIGNATURE_ID
-Value           : 0.164872461727117
+Value           : 0.164882850457192
 Default Value   : --
 Entity Name     : --
 Section Id      : --
@@ -127,6 +127,12 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : IP_TOOL_NAME
+Value           : RAM: 2-PORT
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : IP_TOOL_VERSION
 Value           : 13.1
 Default Value   : --
@@ -163,6 +169,12 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : IP_TOOL_VERSION
+Value           : 13.1
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : MAX_CORE_JUNCTION_TEMP
 Value           : 85
 Default Value   : --
@@ -223,6 +235,12 @@ Default Value   : --
 Entity Name     : --
 Section Id      : --
 
+Assignment Name : MISC_FILE
+Value           : ram_video_bb.v
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
 Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
 Value           : 1.2V
 Default Value   : --
@@ -262,38 +280,38 @@ Section Id      : --
 Module Name                        : Analysis & Synthesis
 Elapsed Time                       : 00:00:13
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 442 MB
+Peak Virtual Memory                : 441 MB
 Total CPU Time (on all processors) : 00:00:13
 
 Module Name                        : Fitter
-Elapsed Time                       : 00:00:20
+Elapsed Time                       : 00:00:21
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 633 MB
+Peak Virtual Memory                : 639 MB
-Total CPU Time (on all processors) : 00:00:20
+Total CPU Time (on all processors) : 00:00:21
 
 Module Name                        : Assembler
-Elapsed Time                       : 00:00:01
+Elapsed Time                       : 00:00:02
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 375 MB
+Peak Virtual Memory                : 385 MB
 Total CPU Time (on all processors) : 00:00:02
 
 Module Name                        : TimeQuest Timing Analyzer
 Elapsed Time                       : 00:00:04
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 451 MB
+Peak Virtual Memory                : 437 MB
-Total CPU Time (on all processors) : 00:00:03
+Total CPU Time (on all processors) : 00:00:04
 
 Module Name                        : EDA Netlist Writer
 Elapsed Time                       : 00:00:03
 Average Processors Used            : 1.0
-Peak Virtual Memory                : 371 MB
+Peak Virtual Memory                : 372 MB
 Total CPU Time (on all processors) : 00:00:03
 
 Module Name                        : Total
-Elapsed Time                       : 00:00:41
+Elapsed Time                       : 00:00:43
 Average Processors Used            : --
 Peak Virtual Memory                : --
-Total CPU Time (on all processors) : 00:00:41
+Total CPU Time (on all processors) : 00:00:43
 +--------------------------------------------------------------------------------+
 
 

output_files/spectrum.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="848845bd7b18df14562b"/>
+    <hash md5_digest_80b="8380d13cf466db2d8054"/>
   </project>
   <file_info>
     <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>

output_files/spectrum.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for spectrum
-Thu Mar 31 14:03:50 2022
+Fri Apr  1 18:55:17 2022
 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
 
 
@@ -70,16 +70,16 @@ applicable agreement for further details.
 +---------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                    ;
 +------------------------------------+--------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Mar 31 14:03:50 2022      ;
+; Analysis & Synthesis Status        ; Successful - Fri Apr  1 18:55:17 2022      ;
 ; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
 ; Revision Name                      ; spectrum                                   ;
 ; Top-level Entity Name              ; spectrum                                   ;
 ; Family                             ; Cyclone IV E                               ;
-; Total logic elements               ; 2,530                                      ;
+; Total logic elements               ; 2,537                                      ;
-;     Total combinational functions  ; 2,262                                      ;
+;     Total combinational functions  ; 2,269                                      ;
 ;     Dedicated logic registers      ; 592                                        ;
 ; Total registers                    ; 592                                        ;
-; Total pins                         ; 74                                         ;
+; Total pins                         ; 75                                         ;
 ; Total virtual pins                 ; 0                                          ;
 ; Total memory bits                  ; 524,288                                    ;
 ; Embedded Multiplier 9-bit elements ; 0                                          ;
@@ -935,32 +935,32 @@ Library                          :
 +---------------------------------------------+---------------------------------+
 ; Resource                                    ; Usage                           ;
 +---------------------------------------------+---------------------------------+
-; Estimated Total logic elements              ; 2,530                           ;
+; Estimated Total logic elements              ; 2,537                           ;
 ;                                             ;                                 ;
-; Total combinational functions               ; 2262                            ;
+; Total combinational functions               ; 2269                            ;
 ; Logic element usage by number of LUT inputs ;                                 ;
-;     -- 4 input functions                    ; 1645                            ;
+;     -- 4 input functions                    ; 1640                            ;
-;     -- 3 input functions                    ; 364                             ;
+;     -- 3 input functions                    ; 385                             ;
-;     -- <=2 input functions                  ; 253                             ;
+;     -- <=2 input functions                  ; 244                             ;
 ;                                             ;                                 ;
 ; Logic elements by mode                      ;                                 ;
-;     -- normal mode                          ; 2209                            ;
+;     -- normal mode                          ; 2216                            ;
 ;     -- arithmetic mode                      ; 53                              ;
 ;                                             ;                                 ;
 ; Total registers                             ; 592                             ;
 ;     -- Dedicated logic registers            ; 592                             ;
 ;     -- I/O registers                        ; 0                               ;
 ;                                             ;                                 ;
-; I/O pins                                    ; 74                              ;
+; I/O pins                                    ; 75                              ;
 ; Total memory bits                           ; 524288                          ;
 ; Embedded Multiplier 9-bit elements          ; 0                               ;
 ; Total PLLs                                  ; 1                               ;
 ;     -- PLLs                                 ; 1                               ;
 ;                                             ;                                 ;
 ; Maximum fan-out node                        ; ula:ula_|clocks:clocks_|clk_cpu ;
-; Maximum fan-out                             ; 472                             ;
+; Maximum fan-out                             ; 436                             ;
-; Total fan-out                               ; 11497                           ;
+; Total fan-out                               ; 11524                           ;
-; Average fan-out                             ; 3.75                            ;
+; Average fan-out                             ; 3.74                            ;
 +---------------------------------------------+---------------------------------+
 
 
@@ -968,13 +968,13 @@ Library                          :
 ; Analysis & Synthesis Resource Utilization by Entity                            ;
 +--------------------------------------------------------------------------------+
 Compilation Hierarchy Node : |spectrum
-LC Combinationals          : 2262 (87)
+LC Combinationals          : 2269 (98)
 LC Registers               : 592 (0)
 Memory Bits                : 524288
 DSP Elements               : 0
 DSP 9x9                    : 0
 DSP 18x18                  : 0
-Pins                       : 74
+Pins                       : 75
 Virtual Pins               : 0
 Full Hierarchy Name        : |spectrum
 Library Name               : work
@@ -1028,7 +1028,7 @@ Full Hierarchy Name        : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
 Library Name               : work
 
 Compilation Hierarchy Node :    |ram32:ram1|
-LC Combinationals          : 24 (0)
+LC Combinationals          : 16 (0)
 LC Registers               : 4 (0)
 Memory Bits                : 262144
 DSP Elements               : 0
@@ -1040,7 +1040,7 @@ Full Hierarchy Name        : |spectrum|ram32:ram1
 Library Name               : work
 
 Compilation Hierarchy Node :       |altsyncram:altsyncram_component|
-LC Combinationals          : 24 (0)
+LC Combinationals          : 16 (0)
 LC Registers               : 4 (0)
 Memory Bits                : 262144
 DSP Elements               : 0
@@ -1052,7 +1052,7 @@ Full Hierarchy Name        : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
 Library Name               : work
 
 Compilation Hierarchy Node :          |altsyncram_g9i1:auto_generated|
-LC Combinationals          : 24 (0)
+LC Combinationals          : 16 (0)
 LC Registers               : 4 (4)
 Memory Bits                : 262144
 DSP Elements               : 0
@@ -1088,7 +1088,7 @@ Full Hierarchy Name        : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
 Library Name               : work
 
 Compilation Hierarchy Node :             |mux_6nb:mux2|
-LC Combinationals          : 16 (16)
+LC Combinationals          : 8 (8)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1136,7 +1136,7 @@ Full Hierarchy Name        : |spectrum|rom0:rom|altsyncram:altsyncram_component|
 Library Name               : work
 
 Compilation Hierarchy Node :    |ula:ula_|
-LC Combinationals          : 418 (4)
+LC Combinationals          : 420 (4)
 LC Registers               : 224 (7)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1244,7 +1244,7 @@ Full Hierarchy Name        : |spectrum|ula:ula_|video:video_
 Library Name               : work
 
 Compilation Hierarchy Node :       |zx_keyboard:zx_keyboard_|
-LC Combinationals          : 148 (148)
+LC Combinationals          : 150 (150)
 LC Registers               : 43 (43)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1256,7 +1256,7 @@ Full Hierarchy Name        : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_
 Library Name               : work
 
 Compilation Hierarchy Node :    |z80_top_direct_n:z80_|
-LC Combinationals          : 1731 (2)
+LC Combinationals          : 1733 (2)
 LC Registers               : 362 (1)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1268,7 +1268,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_
 Library Name               : work
 
 Compilation Hierarchy Node :       |address_latch:address_latch_|
-LC Combinationals          : 47 (16)
+LC Combinationals          : 48 (16)
 LC Registers               : 16 (16)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1280,7 +1280,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|address_latch:addre
 Library Name               : work
 
 Compilation Hierarchy Node :          |inc_dec:b2v_inst_inc_dec|
-LC Combinationals          : 31 (14)
+LC Combinationals          : 32 (14)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1292,7 +1292,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|address_latch:addre
 Library Name               : work
 
 Compilation Hierarchy Node :             |inc_dec_2bit:b2v_dual_adder_0|
-LC Combinationals          : 3 (3)
+LC Combinationals          : 4 (4)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1376,7 +1376,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|address_pins:addres
 Library Name               : work
 
 Compilation Hierarchy Node :       |alu:alu_|
-LC Combinationals          : 130 (76)
+LC Combinationals          : 130 (77)
 LC Registers               : 20 (20)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1400,7 +1400,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se
 Library Name               : work
 
 Compilation Hierarchy Node :          |alu_core:b2v_core|
-LC Combinationals          : 21 (0)
+LC Combinationals          : 20 (0)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1448,7 +1448,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
 Library Name               : work
 
 Compilation Hierarchy Node :             |alu_slice:b2v_alu_slice_bit_3|
-LC Combinationals          : 6 (6)
+LC Combinationals          : 5 (5)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1544,7 +1544,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con
 Library Name               : work
 
 Compilation Hierarchy Node :       |alu_flags:alu_flags_|
-LC Combinationals          : 62 (62)
+LC Combinationals          : 63 (63)
 LC Registers               : 10 (10)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1604,7 +1604,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_
 Library Name               : work
 
 Compilation Hierarchy Node :       |data_switch_mask:sw1_|
-LC Combinationals          : 3 (3)
+LC Combinationals          : 2 (2)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1628,7 +1628,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|decode_state:decode
 Library Name               : work
 
 Compilation Hierarchy Node :       |execute:execute_|
-LC Combinationals          : 931 (931)
+LC Combinationals          : 933 (933)
 LC Registers               : 0 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1712,7 +1712,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con
 Library Name               : work
 
 Compilation Hierarchy Node :       |reg_file:reg_file_|
-LC Combinationals          : 283 (274)
+LC Combinationals          : 282 (273)
 LC Registers               : 224 (0)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1748,7 +1748,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
 Library Name               : work
 
 Compilation Hierarchy Node :          |reg_latch:b2v_latch_af_hi|
-LC Combinationals          : 6 (6)
+LC Combinationals          : 8 (8)
 LC Registers               : 8 (8)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1832,7 +1832,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
 Library Name               : work
 
 Compilation Hierarchy Node :          |reg_latch:b2v_latch_de2_lo|
-LC Combinationals          : 1 (1)
+LC Combinationals          : 0 (0)
 LC Registers               : 8 (8)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1868,7 +1868,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
 Library Name               : work
 
 Compilation Hierarchy Node :          |reg_latch:b2v_latch_hl2_hi|
-LC Combinationals          : 2 (2)
+LC Combinationals          : 0 (0)
 LC Registers               : 8 (8)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -1880,7 +1880,7 @@ Full Hierarchy Name        : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
 Library Name               : work
 
 Compilation Hierarchy Node :          |reg_latch:b2v_latch_hl2_lo|
-LC Combinationals          : 0 (0)
+LC Combinationals          : 1 (1)
 LC Registers               : 8 (8)
 Memory Bits                : 0
 DSP Elements               : 0
@@ -2290,7 +2290,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
 +----------------------------------------------------------+---------+
 ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]                  ; 4       ;
 ; ula:ula_|i2s_intf:i2s_intf_|bitcount[0]                  ; 2       ;
-; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 136     ;
+; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 138     ;
 ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]                 ; 2       ;
 ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]                 ; 2       ;
 ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]                 ; 2       ;
@@ -2300,7 +2300,6 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
 ; ula:ula_|i2s_intf:i2s_intf_|bdivider[0]                  ; 6       ;
 ; ula:ula_|i2s_intf:i2s_intf_|bdivider[4]                  ; 2       ;
 ; ula:ula_|i2s_intf:i2s_intf_|bdivider[2]                  ; 2       ;
-; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff    ; 59      ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1]             ; 2       ;
@@ -2309,6 +2308,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]             ; 2       ;
+; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff    ; 59      ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2]             ; 2       ;
@@ -2331,16 +2331,16 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3]             ; 2       ;
-; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3]             ; 2       ;
+; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]             ; 2       ;
-; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]             ; 2       ;
 ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]             ; 2       ;
+; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]             ; 2       ;
 ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff    ; 68      ;
 ; z80_top_direct_n:z80_|resets:resets_|x1                  ; 2       ;
 ; z80_top_direct_n:z80_|fpga_reset                         ; 2       ;
@@ -2378,7 +2378,7 @@ Baseline Area              : 4 LEs
 Area if Restructured       : 2 LEs
 Saving if Restructured     : 2 LEs
 Registered                 : Yes
-Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
+Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
 
 Multiplexer Inputs         : 6:1
 Bus Width                  : 5 bits
@@ -2402,7 +2402,7 @@ Baseline Area              : 42 LEs
 Area if Restructured       : 14 LEs
 Saving if Restructured     : 28 LEs
 Registered                 : Yes
-Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
+Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
 
 Multiplexer Inputs         : 5:1
 Bus Width                  : 3 bits
@@ -2434,7 +2434,7 @@ Baseline Area              : 10 LEs
 Area if Restructured       : 4 LEs
 Saving if Restructured     : 6 LEs
 Registered                 : Yes
-Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
+Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
 
 Multiplexer Inputs         : 10:1
 Bus Width                  : 2 bits
@@ -2458,7 +2458,7 @@ Baseline Area              : 72 LEs
 Area if Restructured       : 52 LEs
 Saving if Restructured     : 20 LEs
 Registered                 : Yes
-Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
+Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
 
 Multiplexer Inputs         : 3:1
 Bus Width                  : 16 bits
@@ -2466,7 +2466,7 @@ Baseline Area              : 32 LEs
 Area if Restructured       : 32 LEs
 Saving if Restructured     : 0 LEs
 Registered                 : Yes
-Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6]
+Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5]
 
 Multiplexer Inputs         : 4:1
 Bus Width                  : 3 bits
@@ -2498,7 +2498,7 @@ Baseline Area              : 8 LEs
 Area if Restructured       : 6 LEs
 Saving if Restructured     : 2 LEs
 Registered                 : No
-Example Multiplexer Output : |spectrum|Mux0
+Example Multiplexer Output : |spectrum|Mux2
 
 Multiplexer Inputs         : 8:1
 Bus Width                  : 6 bits
@@ -2506,7 +2506,7 @@ Baseline Area              : 30 LEs
 Area if Restructured       : 24 LEs
 Saving if Restructured     : 6 LEs
 Registered                 : No
-Example Multiplexer Output : |spectrum|Selector1
+Example Multiplexer Output : |spectrum|Selector3
 
 Multiplexer Inputs         : 9:1
 Bus Width                  : 2 bits
@@ -2514,7 +2514,7 @@ Baseline Area              : 12 LEs
 Area if Restructured       : 6 LEs
 Saving if Restructured     : 6 LEs
 Registered                 : No
-Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Ack
+Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Idle
 
 Multiplexer Inputs         : 11:1
 Bus Width                  : 2 bits
@@ -3357,7 +3357,7 @@ Value          : 7
 Type           : Signed Integer
 
 Parameter Name : CLK0_MULTIPLY_BY
-Value          : 72
+Value          : 1007
 Type           : Signed Integer
 
 Parameter Name : CLK9_DIVIDE_BY
@@ -3397,7 +3397,7 @@ Value          : 25
 Type           : Signed Integer
 
 Parameter Name : CLK0_DIVIDE_BY
-Value          : 143
+Value          : 2000
 Type           : Signed Integer
 
 Parameter Name : CLK9_PHASE_SHIFT
@@ -4883,11 +4883,6 @@ Details  : Connected to dangling logic. Logic that only feeds a dangling port wi
 +--------------------------------------------------------------------------------+
 ; Port Connectivity Checks: "ula:ula_"                                           ;
 +--------------------------------------------------------------------------------+
-Port     : clk_vram
-Type     : Output
-Severity : Info
-Details  : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
-
 Port     : pressed
 Type     : Output
 Severity : Info
@@ -4953,7 +4948,7 @@ Details  : Input port expression (16 bits) is wider than the input port (14 bits
 Info: *******************************************************************
 Info: Running Quartus II 32-bit Analysis & Synthesis
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-    Info: Processing started: Thu Mar 31 14:03:37 2022
+    Info: Processing started: Fri Apr  1 18:55:04 2022
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
 Warning (20028): Parallel compilation is not licensed and has been disabled
 Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
@@ -5064,8 +5059,10 @@ Info (12021): Found 1 design units, including 1 entities, in source file rom_scr
     Info (12023): Found entity 1: rom_scr
 Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v
     Info (12023): Found entity 1: pll_video
+Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v
+    Info (12023): Found entity 1: ram_video
 Info (12127): Elaborating entity "spectrum" for the top level hierarchy
-Warning (10034): Output port "LED[7..3]" at spectrum.sv(1) has no driver
+Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver
 Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver
 Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver
 Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
@@ -5169,9 +5166,9 @@ Info (12128): Elaborating entity "altpll" for hierarchy "ula:ula_|pll:pll_|altpl
 Info (12130): Elaborated megafunction instantiation "ula:ula_|pll:pll_|altpll:altpll_component"
 Info (12133): Instantiated megafunction "ula:ula_|pll:pll_|altpll:altpll_component" with the following parameter:
     Info (12134): Parameter "bandwidth_type" = "AUTO"
-    Info (12134): Parameter "clk0_divide_by" = "143"
+    Info (12134): Parameter "clk0_divide_by" = "2000"
     Info (12134): Parameter "clk0_duty_cycle" = "50"
-    Info (12134): Parameter "clk0_multiply_by" = "72"
+    Info (12134): Parameter "clk0_multiply_by" = "1007"
     Info (12134): Parameter "clk0_phase_shift" = "0"
     Info (12134): Parameter "clk1_divide_by" = "25"
     Info (12134): Parameter "clk1_duty_cycle" = "50"
@@ -5377,7 +5374,6 @@ Info (13000): Registers with preset signals will power-up high
 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
 Warning (13024): Output pins are stuck at VCC or GND
     Warning (13410): Pin "LED[1]" is stuck at GND
-    Warning (13410): Pin "LED[3]" is stuck at GND
     Warning (13410): Pin "LED[4]" is stuck at GND
     Warning (13410): Pin "LED[5]" is stuck at GND
     Warning (13410): Pin "LED[6]" is stuck at GND
@@ -5393,16 +5389,16 @@ Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
 Warning (21074): Design contains 2 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "SW[0]"
     Warning (15610): No output dependent on input pin "SW[3]"
-Info (21057): Implemented 2739 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 2747 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 10 input pins
+    Info (21058): Implemented 11 input pins
     Info (21059): Implemented 62 output pins
     Info (21060): Implemented 2 bidirectional pins
-    Info (21061): Implemented 2600 logic cells
+    Info (21061): Implemented 2607 logic cells
     Info (21064): Implemented 64 RAM segments
     Info (21065): Implemented 1 PLLs
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 111 warnings
+Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings
-    Info: Peak virtual memory: 442 megabytes
+    Info: Peak virtual memory: 441 megabytes
-    Info: Processing ended: Thu Mar 31 14:03:50 2022
+    Info: Processing ended: Fri Apr  1 18:55:17 2022
     Info: Elapsed time: 00:00:13
     Info: Total CPU time (on all processors): 00:00:13
 

output_files/spectrum.map.summary

@@ -1,13 +1,13 @@
-Analysis & Synthesis Status : Successful - Thu Mar 31 14:03:50 2022
+Analysis & Synthesis Status : Successful - Fri Apr  1 18:55:17 2022
 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
 Revision Name : spectrum
 Top-level Entity Name : spectrum
 Family : Cyclone IV E
-Total logic elements : 2,530
+Total logic elements : 2,537
-    Total combinational functions : 2,262
+    Total combinational functions : 2,269
     Dedicated logic registers : 592
 Total registers : 592
-Total pins : 74
+Total pins : 75
 Total virtual pins : 0
 Total memory bits : 524,288
 Embedded Multiplier 9-bit elements : 0

output_files/spectrum.pin

@@ -89,7 +89,7 @@ GND                          : B2        : gnd    :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+raw_loader_in                : B6        : input  : 3.3-V LVTTL       :         : 8         : Y              
 PS2_DAT                      : B7        : input  : 3.3-V LVTTL       :         : 8         : Y              
 GND+                         : B8        :        :                   :         : 8         :                
 SW[2]                        : B9        : input  : 3.3-V LVTTL       :         : 7         : Y              

output_files/spectrum.sta.summary

@@ -3,31 +3,31 @@ TimeQuest Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
-Slack : -18.442
+Slack : -18.123
-TNS   : -343.502
+TNS   : -549.338
-
-Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.732
-TNS   : -41.482
 
 Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -3.760
+Slack : -7.533
-TNS   : -51.393
+TNS   : -284.813
+
+Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -4.740
+TNS   : -42.810
 
 Type  : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : -2.914
 TNS   : -2.914
 
 Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
-Slack : -0.980
+Slack : 0.210
-TNS   : -15.725
+TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : 0.342
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.342
+Slack : 0.344
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
@@ -35,19 +35,19 @@ Slack : 0.357
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -6.277
+Slack : -6.223
-TNS   : -463.435
+TNS   : -459.348
 
 Type  : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.683
+Slack : 3.698
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 9.489
+Slack : 9.488
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 19.600
+Slack : 19.602
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
@@ -59,31 +59,31 @@ Slack : 35.503
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -17.588
+Slack : -17.311
-TNS   : -332.785
+TNS   : -526.609
-
-Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.423
-TNS   : -38.803
 
 Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -3.309
+Slack : -6.686
-TNS   : -45.165
+TNS   : -253.661
+
+Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -4.428
+TNS   : -40.009
 
 Type  : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : -2.785
 TNS   : -2.785
 
-Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
-Slack : -0.780
-TNS   : -12.413
-
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : 0.298
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.298
+Slack : 0.300
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.304
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
@@ -91,23 +91,23 @@ Slack : 0.311
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -5.784
+Slack : -5.744
-TNS   : -426.554
+TNS   : -423.582
 
 Type  : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.369
+Slack : 3.374
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 9.488
+Slack : 9.489
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 19.594
+Slack : 19.600
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 20.588
+Slack : 20.591
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
@@ -115,31 +115,31 @@ Slack : 35.491
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -15.171
+Slack : -14.971
-TNS   : -291.784
+TNS   : -442.545
+
+Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -4.979
+TNS   : -171.124
 
 Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -3.800
+Slack : -3.775
-TNS   : -34.909
+TNS   : -35.541
 
 Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : -2.784
 TNS   : -2.784
 
-Type  : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -2.194
-TNS   : -30.204
-
 Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
-Slack : -0.698
+Slack : -0.053
-TNS   : -11.143
+TNS   : -0.089
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
 Slack : 0.177
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.179
+Slack : 0.178
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
@@ -147,11 +147,11 @@ Slack : 0.186
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.738
+Slack : -4.693
-TNS   : -361.836
+TNS   : -358.284
 
 Type  : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 2.515
+Slack : 2.518
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
@@ -159,7 +159,7 @@ Slack : 9.208
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 19.640
+Slack : 19.609
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'

pll.v

@@ -102,9 +102,9 @@ module pll (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 143,
+		altpll_component.clk0_divide_by = 2000,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 72,
+		altpll_component.clk0_multiply_by = 1007,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.clk1_divide_by = 25,
 		altpll_component.clk1_duty_cycle = 50,

ram_video.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_video.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_video_bb.v"]

ram_video.v

@@ -0,0 +1,244 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram_video.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram_video (
+	address_a,
+	address_b,
+	clock_a,
+	clock_b,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[13:0]  address_a;
+	input	[13:0]  address_b;
+	input	  clock_a;
+	input	  clock_b;
+	input	[7:0]  data_a;
+	input	[7:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[7:0]  q_a;
+	output	[7:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock_a;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] sub_wire1;
+	wire [7:0] q_a = sub_wire0[7:0];
+	wire [7:0] q_b = sub_wire1[7:0];
+
+	altsyncram	altsyncram_component (
+				.clock0 (clock_a),
+				.wren_a (wren_a),
+				.address_b (address_b),
+				.clock1 (clock_b),
+				.data_b (data_b),
+				.wren_b (wren_b),
+				.address_a (address_a),
+				.data_a (data_a),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK1",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK1",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 16384,
+		altsyncram_component.numwords_b = 16384,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.outdata_reg_b = "CLOCK1",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 14,
+		altsyncram_component.widthad_b = 14,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_b = 8,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]"
+// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0
+// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

ram_video_bb.v

@@ -0,0 +1,182 @@
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram_video.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module ram_video (
+	address_a,
+	address_b,
+	clock_a,
+	clock_b,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[13:0]  address_a;
+	input	[13:0]  address_b;
+	input	  clock_a;
+	input	  clock_b;
+	input	[7:0]  data_a;
+	input	[7:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[7:0]  q_a;
+	output	[7:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock_a;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]"
+// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0
+// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_video_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf