benny/de0-zx-spectrum
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Added ROM based LED patterns

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This commit is contained in:
Adrian Scripca
2022-03-30 12:47:42 +03:00
parent fa29e9f3f6
commit c59b02b186
95 changed files with 13813 additions and 13354 deletions
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output_files/spectrum.map.rpt
+445 -43
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum
Wed Mar 30 11:51:29 2022
Wed Mar 30 12:38:28 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -13,10 +13,14 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
13. altsyncram Parameter Settings by Entity Instance
14. Elapsed Time Per Partition
15. Analysis & Synthesis Messages
@@ -42,18 +46,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ;
; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 35 ;
; Total combinational functions ; 28 ;
; Dedicated logic registers ; 35 ;
; Total registers ; 35 ;
; Total logic elements ; 33 ;
; Total combinational functions ; 33 ;
; Dedicated logic registers ; 24 ;
; Total registers ; 24 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total memory bits ; 64 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
@@ -400,6 +404,78 @@ Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v
Library :
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
Library :
File Name with User-Entered Path : stratix_ram_block.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
Library :
File Name with User-Entered Path : lpm_mux.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc
Library :
File Name with User-Entered Path : lpm_decode.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc
Library :
File Name with User-Entered Path : aglobal131.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc
Library :
File Name with User-Entered Path : a_rdenreg.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
Library :
File Name with User-Entered Path : altrom.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc
Library :
File Name with User-Entered Path : altram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
Library :
File Name with User-Entered Path : altdpram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library :
File Name with User-Entered Path : db/altsyncram_ro91.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf
Library :
+--------------------------------------------------------------------------------+
@@ -409,28 +485,29 @@ Library :
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 35 ;
; Estimated Total logic elements ; 33 ;
; ; ;
; Total combinational functions ; 28 ;
; Total combinational functions ; 33 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 27 ;
; -- <=2 input functions ; 22 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 26 ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 20 ;
; ; ;
; Total registers ; 35 ;
; -- Dedicated logic registers ; 35 ;
; Total registers ; 24 ;
; -- Dedicated logic registers ; 24 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
; Total memory bits ; 64 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 35 ;
; Total fan-out ; 141 ;
; Average fan-out ; 1.74 ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 183 ;
; Average fan-out ; 2.20 ;
+---------------------------------------------+----------------+
@@ -438,9 +515,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 28 (28)
LC Registers : 35 (35)
Memory Bits : 0
LC Combinationals : 33 (33)
LC Registers : 24 (24)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -448,19 +525,75 @@ Pins : 9
Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
Library Name : work
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Port A Depth : 8
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 64
MIF : led_patterns.mif
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+
Vendor : Altera
IP Core Name : ROM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|rom0:rom
IP Include File : /home/benny/work/fpga/projects/rom0.v
+--------------------------------------------------------------------------------+
+------------------------------------------------------+
@@ -468,7 +601,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 35 ;
; Total registers ; 24 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
@@ -478,6 +611,252 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------+
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : ROM
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 3
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 8
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_ro91
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+------------------------------------------+
; Name ; Value ;
+-------------------------------------------+------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 8 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+------------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
@@ -493,26 +872,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:28 2022
Info: Processing started: Wed Mar 30 12:38:26 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "LED[7]" is stuck at GND
Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "8"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "widthad_a" = "3"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf
Info (12023): Found entity 1: altsyncram_ro91
Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated"
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 35 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 11:51:29 2022
Info: Elapsed time: 00:00:01
Info (21061): Implemented 54 logic cells
Info (21064): Implemented 8 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 384 megabytes
Info: Processing ended: Wed Mar 30 12:38:28 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01