Added ROM based LED patterns
This commit is contained in:
+352
-253
@@ -1,5 +1,5 @@
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Fitter report for spectrum
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Wed Mar 30 11:51:35 2022
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Wed Mar 30 12:38:34 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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@@ -29,19 +29,21 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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21. Control Signals
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22. Global & Other Fast Signals
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23. Non-Global High Fan-Out Signals
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24. Routing Usage Summary
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25. LAB Logic Elements
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26. LAB-wide Signals
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27. LAB Signals Sourced
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28. LAB Signals Sourced Out
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29. LAB Distinct Inputs
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30. I/O Rules Summary
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31. I/O Rules Details
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32. I/O Rules Matrix
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33. Fitter Device Options
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34. Operating Settings and Conditions
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35. Fitter Messages
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36. Fitter Suppressed Messages
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24. Fitter RAM Summary
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25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
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26. Routing Usage Summary
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27. LAB Logic Elements
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28. LAB-wide Signals
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29. LAB Signals Sourced
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30. LAB Signals Sourced Out
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31. LAB Distinct Inputs
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32. I/O Rules Summary
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33. I/O Rules Details
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34. I/O Rules Matrix
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35. Fitter Device Options
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36. Operating Settings and Conditions
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37. Fitter Messages
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38. Fitter Suppressed Messages
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@@ -67,20 +69,20 @@ applicable agreement for further details.
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+---------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+--------------------------------------------+
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; Fitter Status ; Successful - Wed Mar 30 11:51:35 2022 ;
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; Fitter Status ; Successful - Wed Mar 30 12:38:34 2022 ;
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; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE22F17C6 ;
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; Timing Models ; Final ;
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; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
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; Total combinational functions ; 28 / 22,320 ( < 1 % ) ;
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; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
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; Total registers ; 35 ;
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; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
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; Total combinational functions ; 33 / 22,320 ( < 1 % ) ;
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; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
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; Total registers ; 24 ;
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; Total pins ; 9 / 154 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 608,256 ( 0 % ) ;
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; Total memory bits ; 64 / 608,256 ( < 1 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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+------------------------------------+--------------------------------------------+
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@@ -2372,14 +2374,14 @@ From Design Partitions [A] :
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From Rapid Recompile [B] :
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Type : -- Requested
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Total [A + B] : 0.00 % ( 0 / 93 )
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From Design Partitions [A] : 0.00 % ( 0 / 93 )
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From Rapid Recompile [B] : 0.00 % ( 0 / 93 )
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Total [A + B] : 0.00 % ( 0 / 95 )
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From Design Partitions [A] : 0.00 % ( 0 / 95 )
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From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
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Type : -- Achieved
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Total [A + B] : 0.00 % ( 0 / 93 )
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From Design Partitions [A] : 0.00 % ( 0 / 93 )
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From Rapid Recompile [B] : 0.00 % ( 0 / 93 )
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Total [A + B] : 0.00 % ( 0 / 95 )
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From Design Partitions [A] : 0.00 % ( 0 / 95 )
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From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
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Type :
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Total [A + B] :
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@@ -2430,7 +2432,7 @@ Contents : hard_block:auto_generated_inst
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; Incremental Compilation Placement Preservation ;
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+--------------------------------------------------------------------------------+
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Partition Name : Top
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Preservation Achieved : 0.00 % ( 0 / 83 )
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Preservation Achieved : 0.00 % ( 0 / 85 )
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Preservation Level Used : N/A
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Netlist Type Used : Source File
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Preservation Method : N/A
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@@ -2452,54 +2454,54 @@ Notes :
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The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin.
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+---------------------------------------------------------------------+
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; Fitter Resource Usage Summary ;
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+---------------------------------------------+-----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+-----------------------+
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; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
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; -- Combinational with no register ; 0 ;
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; -- Register only ; 7 ;
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; -- Combinational with a register ; 28 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 0 ;
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; -- 3 input functions ; 1 ;
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; -- <=2 input functions ; 27 ;
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; -- Register only ; 7 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 2 ;
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; -- arithmetic mode ; 26 ;
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; ; ;
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; Total registers* ; 35 / 23,018 ( < 1 % ) ;
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; -- Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
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; -- I/O registers ; 0 / 698 ( 0 % ) ;
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; ; ;
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; Total LABs: partially or completely used ; 5 / 1,395 ( < 1 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 9 / 154 ( 6 % ) ;
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; -- Clock pins ; 1 / 7 ( 14 % ) ;
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; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
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; ; ;
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; Global signals ; 1 ;
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; M9Ks ; 0 / 66 ( 0 % ) ;
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; Total block memory bits ; 0 / 608,256 ( 0 % ) ;
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; Total block memory implementation bits ; 0 / 608,256 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
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; PLLs ; 0 / 4 ( 0 % ) ;
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; Global clocks ; 1 / 20 ( 5 % ) ;
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; JTAGs ; 0 / 1 ( 0 % ) ;
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; CRC blocks ; 0 / 1 ( 0 % ) ;
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; ASMI blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Maximum fan-out ; 35 ;
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; Highest non-global fan-out ; 2 ;
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; Total fan-out ; 154 ;
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; Average fan-out ; 1.56 ;
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+---------------------------------------------+-----------------------+
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+-----------------------------------------------------------------------+
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; Fitter Resource Usage Summary ;
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+---------------------------------------------+-------------------------+
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; Resource ; Usage ;
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+---------------------------------------------+-------------------------+
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; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
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; -- Combinational with no register ; 9 ;
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; -- Register only ; 0 ;
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; -- Combinational with a register ; 24 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 10 ;
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; -- 3 input functions ; 1 ;
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; -- <=2 input functions ; 22 ;
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; -- Register only ; 0 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 13 ;
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; -- arithmetic mode ; 20 ;
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; ; ;
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; Total registers* ; 24 / 23,018 ( < 1 % ) ;
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; -- Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
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; -- I/O registers ; 0 / 698 ( 0 % ) ;
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; ; ;
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; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 9 / 154 ( 6 % ) ;
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; -- Clock pins ; 1 / 7 ( 14 % ) ;
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; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
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; ; ;
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; Global signals ; 1 ;
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; M9Ks ; 1 / 66 ( 2 % ) ;
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; Total block memory bits ; 64 / 608,256 ( < 1 % ) ;
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; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
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; PLLs ; 0 / 4 ( 0 % ) ;
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; Global clocks ; 1 / 20 ( 5 % ) ;
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; JTAGs ; 0 / 1 ( 0 % ) ;
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; CRC blocks ; 0 / 1 ( 0 % ) ;
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; ASMI blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Maximum fan-out ; 25 ;
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; Highest non-global fan-out ; 4 ;
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; Total fan-out ; 161 ;
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; Average fan-out ; 1.85 ;
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+---------------------------------------------+-------------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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@@ -2516,19 +2518,19 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : Total logic elements
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Top : 35 / 22320 ( < 1 % )
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Top : 33 / 22320 ( < 1 % )
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hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
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Statistic : -- Combinational with no register
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Top : 0
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Top : 9
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hard_block:auto_generated_inst : 0
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Statistic : -- Register only
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Top : 7
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Top : 0
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hard_block:auto_generated_inst : 0
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Statistic : -- Combinational with a register
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Top : 28
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Top : 24
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hard_block:auto_generated_inst : 0
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Statistic :
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@@ -2540,7 +2542,7 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : -- 4 input functions
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Top : 0
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Top : 10
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hard_block:auto_generated_inst : 0
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Statistic : -- 3 input functions
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@@ -2548,11 +2550,11 @@ Top : 1
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hard_block:auto_generated_inst : 0
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Statistic : -- <=2 input functions
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Top : 27
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Top : 22
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hard_block:auto_generated_inst : 0
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Statistic : -- Register only
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Top : 7
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Top : 0
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hard_block:auto_generated_inst : 0
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Statistic :
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@@ -2564,11 +2566,11 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : -- normal mode
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Top : 2
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Top : 13
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hard_block:auto_generated_inst : 0
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Statistic : -- arithmetic mode
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Top : 26
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Top : 20
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hard_block:auto_generated_inst : 0
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Statistic :
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@@ -2576,11 +2578,11 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : Total registers
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Top : 35
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Top : 24
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hard_block:auto_generated_inst : 0
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Statistic : -- Dedicated logic registers
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Top : 35 / 22320 ( < 1 % )
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Top : 24 / 22320 ( < 1 % )
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hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
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Statistic : -- I/O registers
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@@ -2592,7 +2594,7 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : Total LABs: partially or completely used
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Top : 5 / 1395 ( < 1 % )
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Top : 3 / 1395 ( < 1 % )
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hard_block:auto_generated_inst : 0 / 1395 ( 0 % )
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Statistic :
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@@ -2612,13 +2614,17 @@ Top : 0 / 132 ( 0 % )
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hard_block:auto_generated_inst : 0 / 132 ( 0 % )
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Statistic : Total memory bits
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Top : 0
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Top : 64
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hard_block:auto_generated_inst : 0
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Statistic : Total RAM block bits
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Top : 0
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Top : 9216
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hard_block:auto_generated_inst : 0
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Statistic : M9K
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Top : 1 / 66 ( 1 % )
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hard_block:auto_generated_inst : 0 / 66 ( 0 % )
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Statistic : Clock control block
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Top : 1 / 24 ( 4 % )
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hard_block:auto_generated_inst : 0 / 24 ( 0 % )
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@@ -2656,11 +2662,11 @@ Top :
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hard_block:auto_generated_inst :
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Statistic : -- Total Connections
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Top : 149
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Top : 156
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hard_block:auto_generated_inst : 5
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Statistic : -- Registered Connections
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Top : 43
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Top : 38
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hard_block:auto_generated_inst : 0
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Statistic :
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@@ -2767,7 +2773,7 @@ I/O Bank : 3
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X coordinate : 27
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Y coordinate : 0
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Z coordinate : 21
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Combinational Fan-Out : 35
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Combinational Fan-Out : 25
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Registered Fan-Out : 0
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Global : yes
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Input Register : no
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@@ -6219,21 +6225,72 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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; Fitter Resource Utilization by Entity ;
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+--------------------------------------------------------------------------------+
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Compilation Hierarchy Node : |spectrum
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Logic Cells : 35 (35)
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Dedicated Logic Registers : 35 (35)
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Logic Cells : 33 (33)
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Dedicated Logic Registers : 24 (24)
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I/O Registers : 0 (0)
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Memory Bits : 0
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M9Ks : 0
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Memory Bits : 64
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M9Ks : 1
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 9
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Virtual Pins : 0
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LUT-Only LCs : 0 (0)
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Register-Only LCs : 7 (7)
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LUT/Register LCs : 28 (28)
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LUT-Only LCs : 9 (9)
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Register-Only LCs : 0 (0)
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LUT/Register LCs : 24 (24)
|
||||
Full Hierarchy Name : |spectrum
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |rom0:rom|
|
||||
Logic Cells : 0 (0)
|
||||
Dedicated Logic Registers : 0 (0)
|
||||
I/O Registers : 0 (0)
|
||||
Memory Bits : 64
|
||||
M9Ks : 1
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
LUT-Only LCs : 0 (0)
|
||||
Register-Only LCs : 0 (0)
|
||||
LUT/Register LCs : 0 (0)
|
||||
Full Hierarchy Name : |spectrum|rom0:rom
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
Logic Cells : 0 (0)
|
||||
Dedicated Logic Registers : 0 (0)
|
||||
I/O Registers : 0 (0)
|
||||
Memory Bits : 64
|
||||
M9Ks : 1
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
LUT-Only LCs : 0 (0)
|
||||
Register-Only LCs : 0 (0)
|
||||
LUT/Register LCs : 0 (0)
|
||||
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
|
||||
Logic Cells : 0 (0)
|
||||
Dedicated Logic Registers : 0 (0)
|
||||
I/O Registers : 0 (0)
|
||||
Memory Bits : 64
|
||||
M9Ks : 1
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
LUT-Only LCs : 0 (0)
|
||||
Register-Only LCs : 0 (0)
|
||||
LUT/Register LCs : 0 (0)
|
||||
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
|
||||
Library Name : work
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
@@ -6332,7 +6389,7 @@ Setting :
|
||||
+--------------------------------------------------------------------------------+
|
||||
Name : CLOCK_50
|
||||
Location : PIN_R8
|
||||
Fan-Out : 35
|
||||
Fan-Out : 25
|
||||
Usage : Clock
|
||||
Global : yes
|
||||
Global Resource Used : Global Clock
|
||||
@@ -6347,8 +6404,8 @@ Enable Signal Source Name : --
|
||||
+--------------------------------------------------------------------------------+
|
||||
Name : CLOCK_50
|
||||
Location : PIN_R8
|
||||
Fan-Out : 35
|
||||
Fan-Out Using Intentional Clock Skew : 12
|
||||
Fan-Out : 25
|
||||
Fan-Out Using Intentional Clock Skew : 3
|
||||
Global Resource Used : Global Clock
|
||||
Global Line Name : GCLK18
|
||||
Enable Signal Source Name : --
|
||||
@@ -6356,101 +6413,139 @@ Enable Signal Source Name : --
|
||||
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Non-Global High Fan-Out Signals ;
|
||||
+----------------+----------------+
|
||||
; Name ; Fan-Out ;
|
||||
+----------------+----------------+
|
||||
; counter[0] ; 2 ;
|
||||
; counter[27] ; 2 ;
|
||||
; counter[26] ; 2 ;
|
||||
; counter[25] ; 2 ;
|
||||
; counter[24] ; 2 ;
|
||||
; counter[23] ; 2 ;
|
||||
; counter[22] ; 2 ;
|
||||
; counter[21] ; 2 ;
|
||||
; counter[0]~81 ; 1 ;
|
||||
; LED[6]~reg0 ; 1 ;
|
||||
; LED[5]~reg0 ; 1 ;
|
||||
; LED[4]~reg0 ; 1 ;
|
||||
; LED[3]~reg0 ; 1 ;
|
||||
; LED[2]~reg0 ; 1 ;
|
||||
; LED[1]~reg0 ; 1 ;
|
||||
; LED[0]~reg0 ; 1 ;
|
||||
; counter[27]~79 ; 1 ;
|
||||
; counter[26]~78 ; 1 ;
|
||||
; counter[26]~77 ; 1 ;
|
||||
; counter[25]~76 ; 1 ;
|
||||
; counter[25]~75 ; 1 ;
|
||||
; counter[24]~74 ; 1 ;
|
||||
; counter[24]~73 ; 1 ;
|
||||
; counter[23]~72 ; 1 ;
|
||||
; counter[23]~71 ; 1 ;
|
||||
; counter[22]~70 ; 1 ;
|
||||
; counter[22]~69 ; 1 ;
|
||||
; counter[21]~68 ; 1 ;
|
||||
; counter[21]~67 ; 1 ;
|
||||
; counter[20]~66 ; 1 ;
|
||||
; counter[20]~65 ; 1 ;
|
||||
; counter[19]~64 ; 1 ;
|
||||
; counter[19]~63 ; 1 ;
|
||||
; counter[18]~62 ; 1 ;
|
||||
; counter[18]~61 ; 1 ;
|
||||
; counter[17]~60 ; 1 ;
|
||||
; counter[17]~59 ; 1 ;
|
||||
; counter[16]~58 ; 1 ;
|
||||
; counter[16]~57 ; 1 ;
|
||||
; counter[15]~56 ; 1 ;
|
||||
; counter[15]~55 ; 1 ;
|
||||
; counter[14]~54 ; 1 ;
|
||||
; counter[14]~53 ; 1 ;
|
||||
; counter[13]~52 ; 1 ;
|
||||
; counter[13]~51 ; 1 ;
|
||||
; counter[12]~50 ; 1 ;
|
||||
; counter[12]~49 ; 1 ;
|
||||
; counter[11]~48 ; 1 ;
|
||||
; counter[11]~47 ; 1 ;
|
||||
; counter[10]~46 ; 1 ;
|
||||
; counter[10]~45 ; 1 ;
|
||||
; counter[9]~44 ; 1 ;
|
||||
; counter[9]~43 ; 1 ;
|
||||
; counter[8]~42 ; 1 ;
|
||||
; counter[8]~41 ; 1 ;
|
||||
; counter[7]~40 ; 1 ;
|
||||
; counter[7]~39 ; 1 ;
|
||||
; counter[6]~38 ; 1 ;
|
||||
; counter[6]~37 ; 1 ;
|
||||
; counter[5]~36 ; 1 ;
|
||||
; counter[5]~35 ; 1 ;
|
||||
; counter[4]~34 ; 1 ;
|
||||
; counter[4]~33 ; 1 ;
|
||||
; counter[3]~32 ; 1 ;
|
||||
; counter[3]~31 ; 1 ;
|
||||
; counter[2]~30 ; 1 ;
|
||||
; counter[2]~29 ; 1 ;
|
||||
; counter[1]~28 ; 1 ;
|
||||
; counter[1]~27 ; 1 ;
|
||||
; counter[1] ; 1 ;
|
||||
; counter[2] ; 1 ;
|
||||
; counter[3] ; 1 ;
|
||||
; counter[4] ; 1 ;
|
||||
; counter[5] ; 1 ;
|
||||
; counter[6] ; 1 ;
|
||||
; counter[7] ; 1 ;
|
||||
; counter[8] ; 1 ;
|
||||
; counter[9] ; 1 ;
|
||||
; counter[10] ; 1 ;
|
||||
; counter[11] ; 1 ;
|
||||
; counter[12] ; 1 ;
|
||||
; counter[13] ; 1 ;
|
||||
; counter[14] ; 1 ;
|
||||
; counter[15] ; 1 ;
|
||||
; counter[16] ; 1 ;
|
||||
; counter[17] ; 1 ;
|
||||
; counter[18] ; 1 ;
|
||||
; counter[19] ; 1 ;
|
||||
; counter[20] ; 1 ;
|
||||
+----------------+----------------+
|
||||
+------------------------------------------------------------------------------------------+
|
||||
; Non-Global High Fan-Out Signals ;
|
||||
+--------------------------------------------------------------------------------+---------+
|
||||
; Name ; Fan-Out ;
|
||||
+--------------------------------------------------------------------------------+---------+
|
||||
; address[0] ; 4 ;
|
||||
; Add0~40 ; 4 ;
|
||||
; Equal0~4 ; 3 ;
|
||||
; address[1] ; 3 ;
|
||||
; Add0~38 ; 3 ;
|
||||
; Add0~36 ; 3 ;
|
||||
; Add0~34 ; 3 ;
|
||||
; Add0~32 ; 3 ;
|
||||
; Equal0~5 ; 2 ;
|
||||
; address[2] ; 2 ;
|
||||
; Add0~30 ; 2 ;
|
||||
; Add0~28 ; 2 ;
|
||||
; Add0~26 ; 2 ;
|
||||
; Add0~24 ; 2 ;
|
||||
; Add0~22 ; 2 ;
|
||||
; Add0~20 ; 2 ;
|
||||
; Add0~18 ; 2 ;
|
||||
; Add0~16 ; 2 ;
|
||||
; Add0~14 ; 2 ;
|
||||
; Add0~12 ; 2 ;
|
||||
; Add0~10 ; 2 ;
|
||||
; Add0~8 ; 2 ;
|
||||
; Add0~6 ; 2 ;
|
||||
; Add0~4 ; 2 ;
|
||||
; Add0~2 ; 2 ;
|
||||
; Add0~0 ; 2 ;
|
||||
; address[2]~3 ; 1 ;
|
||||
; address[1]~2 ; 1 ;
|
||||
; address[1]~1 ; 1 ;
|
||||
; Equal0~7 ; 1 ;
|
||||
; Equal0~6 ; 1 ;
|
||||
; address[0]~0 ; 1 ;
|
||||
; Equal0~3 ; 1 ;
|
||||
; Equal0~2 ; 1 ;
|
||||
; Equal0~1 ; 1 ;
|
||||
; Equal0~0 ; 1 ;
|
||||
; counter[0] ; 1 ;
|
||||
; counter[1] ; 1 ;
|
||||
; counter[2] ; 1 ;
|
||||
; counter[3] ; 1 ;
|
||||
; counter[4] ; 1 ;
|
||||
; counter[5] ; 1 ;
|
||||
; counter[6] ; 1 ;
|
||||
; counter[7] ; 1 ;
|
||||
; counter[8] ; 1 ;
|
||||
; counter[9] ; 1 ;
|
||||
; counter[10] ; 1 ;
|
||||
; counter[11] ; 1 ;
|
||||
; counter[12] ; 1 ;
|
||||
; counter[13] ; 1 ;
|
||||
; counter[14] ; 1 ;
|
||||
; counter[15] ; 1 ;
|
||||
; counter[16] ; 1 ;
|
||||
; counter[17] ; 1 ;
|
||||
; counter[18] ; 1 ;
|
||||
; counter[19] ; 1 ;
|
||||
; counter[20] ; 1 ;
|
||||
; Add0~39 ; 1 ;
|
||||
; Add0~37 ; 1 ;
|
||||
; Add0~35 ; 1 ;
|
||||
; Add0~33 ; 1 ;
|
||||
; Add0~31 ; 1 ;
|
||||
; Add0~29 ; 1 ;
|
||||
; Add0~27 ; 1 ;
|
||||
; Add0~25 ; 1 ;
|
||||
; Add0~23 ; 1 ;
|
||||
; Add0~21 ; 1 ;
|
||||
; Add0~19 ; 1 ;
|
||||
; Add0~17 ; 1 ;
|
||||
; Add0~15 ; 1 ;
|
||||
; Add0~13 ; 1 ;
|
||||
; Add0~11 ; 1 ;
|
||||
; Add0~9 ; 1 ;
|
||||
; Add0~7 ; 1 ;
|
||||
; Add0~5 ; 1 ;
|
||||
; Add0~3 ; 1 ;
|
||||
; Add0~1 ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] ; 1 ;
|
||||
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] ; 1 ;
|
||||
+--------------------------------------------------------------------------------+---------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Fitter RAM Summary ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
|
||||
Type : AUTO
|
||||
Mode : ROM
|
||||
Clock Mode : Single Clock
|
||||
Port A Depth : 8
|
||||
Port A Width : 8
|
||||
Port B Depth : --
|
||||
Port B Width : --
|
||||
Port A Input Registers : yes
|
||||
Port A Output Registers : yes
|
||||
Port B Input Registers : --
|
||||
Port B Output Registers : --
|
||||
Size : 64
|
||||
Implementation Port A Depth : 8
|
||||
Implementation Port A Width : 8
|
||||
Implementation Port B Depth : --
|
||||
Implementation Port B Width : --
|
||||
Implementation Bits : 64
|
||||
M9Ks : 1
|
||||
MIF : led_patterns.mif
|
||||
Location : M9K_X33_Y26_N0
|
||||
Mixed Width RDW Mode : Don't care
|
||||
Port A RDW Mode : Old data
|
||||
Port B RDW Mode : Old data
|
||||
Fits in MLABs : No - Unknown
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
|
||||
|
||||
|
||||
RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal)
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM ;
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ;
|
||||
+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
|
||||
;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ;
|
||||
|
||||
|
||||
+-----------------------------------------------+
|
||||
@@ -6458,65 +6553,65 @@ Enable Signal Source Name : --
|
||||
+-----------------------+-----------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+-----------------------+
|
||||
; Block interconnects ; 16 / 71,559 ( < 1 % ) ;
|
||||
; C16 interconnects ; 0 / 2,597 ( 0 % ) ;
|
||||
; C4 interconnects ; 9 / 46,848 ( < 1 % ) ;
|
||||
; Direct links ; 4 / 71,559 ( < 1 % ) ;
|
||||
; Block interconnects ; 42 / 71,559 ( < 1 % ) ;
|
||||
; C16 interconnects ; 3 / 2,597 ( < 1 % ) ;
|
||||
; C4 interconnects ; 20 / 46,848 ( < 1 % ) ;
|
||||
; Direct links ; 24 / 71,559 ( < 1 % ) ;
|
||||
; Global clocks ; 1 / 20 ( 5 % ) ;
|
||||
; Local interconnects ; 28 / 24,624 ( < 1 % ) ;
|
||||
; R24 interconnects ; 4 / 2,496 ( < 1 % ) ;
|
||||
; R4 interconnects ; 17 / 62,424 ( < 1 % ) ;
|
||||
; Local interconnects ; 24 / 24,624 ( < 1 % ) ;
|
||||
; R24 interconnects ; 7 / 2,496 ( < 1 % ) ;
|
||||
; R4 interconnects ; 27 / 62,424 ( < 1 % ) ;
|
||||
+-----------------------+-----------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 5) ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 2 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 3) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 0 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+-----------------------------+
|
||||
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 5) ;
|
||||
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ;
|
||||
+------------------------------------+-----------------------------+
|
||||
; 1 Clock ; 5 ;
|
||||
; 1 Clock ; 3 ;
|
||||
+------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 5) ;
|
||||
; Number of Signals Sourced (Average = 19.00) ; Number of LABs (Total = 3) ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
@@ -6529,43 +6624,46 @@ Enable Signal Source Name : --
|
||||
; 19 ; 0 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 0 ;
|
||||
; 22 ; 1 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 0 ;
|
||||
; 25 ; 0 ;
|
||||
; 26 ; 0 ;
|
||||
; 27 ; 0 ;
|
||||
; 28 ; 2 ;
|
||||
; 26 ; 1 ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced Out (Average = 2.80) ; Number of LABs (Total = 5) ;
|
||||
; Number of Signals Sourced Out (Average = 4.33) ; Number of LABs (Total = 3) ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
; 0 ; 1 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Distinct Inputs (Average = 2.60) ; Number of LABs (Total = 5) ;
|
||||
; Number of Distinct Inputs (Average = 4.67) ; Number of LABs (Total = 3) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 1 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@@ -7338,6 +7436,7 @@ Info (169124): Fitter converted 5 user pins into dedicated programming pins
|
||||
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
|
||||
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
|
||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332144): No user constrained base clocks found in the design
|
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||||
@@ -7503,10 +7602,10 @@ Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
@@ -7517,9 +7616,9 @@ Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V
|
||||
Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8
|
||||
Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg
|
||||
Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings
|
||||
Info: Peak virtual memory: 588 megabytes
|
||||
Info: Processing ended: Wed Mar 30 11:51:36 2022
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Peak virtual memory: 600 megabytes
|
||||
Info: Processing ended: Wed Mar 30 12:38:34 2022
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user