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Added ROM based LED patterns

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This commit is contained in:
Adrian Scripca
2022-03-30 12:47:42 +03:00
parent fa29e9f3f6
commit c59b02b186
95 changed files with 13813 additions and 13354 deletions
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db/spectrum.hier_info
+111 -44
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@@ -1,47 +1,114 @@
|spectrum
CLOCK_50 => LED[0]~reg0.CLK
CLOCK_50 => LED[1]~reg0.CLK
CLOCK_50 => LED[2]~reg0.CLK
CLOCK_50 => LED[3]~reg0.CLK
CLOCK_50 => LED[4]~reg0.CLK
CLOCK_50 => LED[5]~reg0.CLK
CLOCK_50 => LED[6]~reg0.CLK
CLOCK_50 => LED[7]~reg0.CLK
CLOCK_50 => counter[0].CLK
CLOCK_50 => counter[1].CLK
CLOCK_50 => counter[2].CLK
CLOCK_50 => counter[3].CLK
CLOCK_50 => counter[4].CLK
CLOCK_50 => counter[5].CLK
CLOCK_50 => counter[6].CLK
CLOCK_50 => counter[7].CLK
CLOCK_50 => counter[8].CLK
CLOCK_50 => counter[9].CLK
CLOCK_50 => counter[10].CLK
CLOCK_50 => counter[11].CLK
CLOCK_50 => counter[12].CLK
CLOCK_50 => counter[13].CLK
CLOCK_50 => counter[14].CLK
CLOCK_50 => counter[15].CLK
CLOCK_50 => counter[16].CLK
CLOCK_50 => counter[17].CLK
CLOCK_50 => counter[18].CLK
CLOCK_50 => counter[19].CLK
CLOCK_50 => counter[20].CLK
CLOCK_50 => counter[21].CLK
CLOCK_50 => counter[22].CLK
CLOCK_50 => counter[23].CLK
CLOCK_50 => counter[24].CLK
CLOCK_50 => counter[25].CLK
CLOCK_50 => counter[26].CLK
CLOCK_50 => counter[27].CLK
LED[0] <= LED[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= LED[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= LED[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= LED[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= LED[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[5] <= LED[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[6] <= LED[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[7] <= LED[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLOCK_50 => CLOCK_50.IN1
LED[0] <= rom0:rom.q
LED[1] <= rom0:rom.q
LED[2] <= rom0:rom.q
LED[3] <= rom0:rom.q
LED[4] <= rom0:rom.q
LED[5] <= rom0:rom.q
LED[6] <= rom0:rom.q
LED[7] <= rom0:rom.q
|spectrum|rom0:rom
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
clock => clock.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
|spectrum|rom0:rom|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ro91:auto_generated.address_a[0]
address_a[1] => altsyncram_ro91:auto_generated.address_a[1]
address_a[2] => altsyncram_ro91:auto_generated.address_a[2]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ro91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ro91:auto_generated.q_a[0]
q_a[1] <= altsyncram_ro91:auto_generated.q_a[1]
q_a[2] <= altsyncram_ro91:auto_generated.q_a[2]
q_a[3] <= altsyncram_ro91:auto_generated.q_a[3]
q_a[4] <= altsyncram_ro91:auto_generated.q_a[4]
q_a[5] <= altsyncram_ro91:auto_generated.q_a[5]
q_a[6] <= altsyncram_ro91:auto_generated.q_a[6]
q_a[7] <= altsyncram_ro91:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>
|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT