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Added RAM16

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This commit is contained in:
Adrian Scripca
2022-03-30 14:23:28 +03:00
parent 9d6eb7a9fa
commit bd2a66037c
97 changed files with 23178 additions and 19024 deletions
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db/altsyncram_88g2.tdf
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--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION decode_jsa (data[0..0], enable)
RETURNS ( eq[1..0]);
FUNCTION decode_c8a (data[0..0])
RETURNS ( eq[1..0]);
FUNCTION mux_3nb (data[15..0], sel[0..0])
RETURNS ( result[7..0]);
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = lut 2 M9K 16 reg 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_88g2
(
address_a[13..0] : input;
address_b[13..0] : input;
clock0 : input;
data_a[7..0] : input;
data_b[7..0] : input;
q_a[7..0] : output;
q_b[7..0] : output;
wren_a : input;
wren_b : input;
)
VARIABLE
address_reg_a[0..0] : dffe;
address_reg_b[0..0] : dffe;
out_address_reg_a[0..0] : dffe;
out_address_reg_b[0..0] : dffe;
decode2 : decode_jsa;
decode3 : decode_jsa;
rden_decode_a : decode_c8a;
rden_decode_b : decode_c8a;
mux4 : mux_3nb;
mux5 : mux_3nb;
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_sel[0..0] : WIRE;
address_a_wire[13..0] : WIRE;
address_b_sel[0..0] : WIRE;
address_b_wire[13..0] : WIRE;
w_addr_val_a7w[0..0] : WIRE;
w_addr_val_b4w[0..0] : WIRE;
w_addr_val_b8w[0..0] : WIRE;
wren_decode_addr_sel_a[0..0] : WIRE;
wren_decode_addr_sel_b[0..0] : WIRE;
BEGIN
address_reg_a[].clk = clock0;
address_reg_a[].d = address_a_sel[];
address_reg_b[].clk = clock0;
address_reg_b[].d = address_b_sel[];
out_address_reg_a[].clk = clock0;
out_address_reg_a[].d = address_reg_a[].q;
out_address_reg_b[].clk = clock0;
out_address_reg_b[].d = address_reg_b[].q;
decode2.data[0..0] = address_a_wire[13..13];
decode2.enable = wren_a;
decode3.data[] = w_addr_val_b4w[];
decode3.enable = wren_b;
rden_decode_a.data[] = w_addr_val_a7w[];
rden_decode_b.data[] = w_addr_val_b8w[];
mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]);
mux4.sel[] = out_address_reg_a[].q;
mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]);
mux5.sel[] = out_address_reg_b[].q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[15..0].clk1 = clock0;
ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]);
ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]);
ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[15..0].portare = B"1111111111111111";
ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]);
ram_block1a[0].portbdatain[] = ( data_b[0..0]);
ram_block1a[1].portbdatain[] = ( data_b[1..1]);
ram_block1a[2].portbdatain[] = ( data_b[2..2]);
ram_block1a[3].portbdatain[] = ( data_b[3..3]);
ram_block1a[4].portbdatain[] = ( data_b[4..4]);
ram_block1a[5].portbdatain[] = ( data_b[5..5]);
ram_block1a[6].portbdatain[] = ( data_b[6..6]);
ram_block1a[7].portbdatain[] = ( data_b[7..7]);
ram_block1a[8].portbdatain[] = ( data_b[0..0]);
ram_block1a[9].portbdatain[] = ( data_b[1..1]);
ram_block1a[10].portbdatain[] = ( data_b[2..2]);
ram_block1a[11].portbdatain[] = ( data_b[3..3]);
ram_block1a[12].portbdatain[] = ( data_b[4..4]);
ram_block1a[13].portbdatain[] = ( data_b[5..5]);
ram_block1a[14].portbdatain[] = ( data_b[6..6]);
ram_block1a[15].portbdatain[] = ( data_b[7..7]);
ram_block1a[15..0].portbre = B"1111111111111111";
ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
address_a_sel[0..0] = address_a[13..13];
address_a_wire[] = address_a[];
address_b_sel[0..0] = address_b[13..13];
address_b_wire[] = address_b[];
q_a[] = mux4.result[];
q_b[] = mux5.result[];
w_addr_val_a7w[] = wren_decode_addr_sel_a[];
w_addr_val_b4w[0..0] = address_b_wire[13..13];
w_addr_val_b8w[] = wren_decode_addr_sel_b[];
wren_decode_addr_sel_a[0..0] = address_a_wire[13..13];
wren_decode_addr_sel_b[0..0] = address_b_wire[13..13];
END;
--VALID FILE
db/altsyncram_bui2.tdf
+781
View File
@@ -0,0 +1,781 @@
--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION decode_jsa (data[0..0], enable)
RETURNS ( eq[1..0]);
FUNCTION decode_c8a (data[0..0])
RETURNS ( eq[1..0]);
FUNCTION mux_3nb (data[15..0], sel[0..0])
RETURNS ( result[7..0]);
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 16 reg 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_bui2
(
address_a[13..0] : input;
address_b[13..0] : input;
clock0 : input;
data_a[7..0] : input;
data_b[7..0] : input;
q_a[7..0] : output;
q_b[7..0] : output;
wren_a : input;
wren_b : input;
)
VARIABLE
address_reg_a[0..0] : dffe;
address_reg_b[0..0] : dffe;
out_address_reg_a[0..0] : dffe;
out_address_reg_b[0..0] : dffe;
decode2 : decode_jsa;
decode3 : decode_jsa;
rden_decode_a : decode_c8a;
rden_decode_b : decode_c8a;
mux4 : mux_3nb;
mux5 : mux_3nb;
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "ena1",
CLK1_INPUT_CLOCK_ENABLE = "none",
CLK1_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock1",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
PORT_B_READ_ENABLE_CLOCK = "clock1",
PORT_B_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_sel[0..0] : WIRE;
address_a_wire[13..0] : WIRE;
address_b_sel[0..0] : WIRE;
address_b_wire[13..0] : WIRE;
w_addr_val_a2w[0..0] : WIRE;
w_addr_val_a7w[0..0] : WIRE;
w_addr_val_b4w[0..0] : WIRE;
w_addr_val_b8w[0..0] : WIRE;
wren_decode_addr_sel_a[0..0] : WIRE;
wren_decode_addr_sel_b[0..0] : WIRE;
BEGIN
address_reg_a[].clk = clock0;
address_reg_a[].d = address_a_sel[];
address_reg_b[].clk = clock0;
address_reg_b[].d = address_b_sel[];
out_address_reg_a[].clk = clock0;
out_address_reg_a[].d = address_reg_a[].q;
out_address_reg_b[].clk = clock0;
out_address_reg_b[].d = address_reg_b[].q;
decode2.data[] = w_addr_val_a2w[];
decode2.enable = wren_a;
decode3.data[] = w_addr_val_b4w[];
decode3.enable = wren_b;
rden_decode_a.data[] = w_addr_val_a7w[];
rden_decode_b.data[] = w_addr_val_b8w[];
mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]);
mux4.sel[] = out_address_reg_a[].q;
mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]);
mux5.sel[] = out_address_reg_b[].q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[15..0].clk1 = clock0;
ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]);
ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]);
ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[15..0].portare = B"1111111111111111";
ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]);
ram_block1a[0].portbdatain[] = ( data_b[0..0]);
ram_block1a[1].portbdatain[] = ( data_b[1..1]);
ram_block1a[2].portbdatain[] = ( data_b[2..2]);
ram_block1a[3].portbdatain[] = ( data_b[3..3]);
ram_block1a[4].portbdatain[] = ( data_b[4..4]);
ram_block1a[5].portbdatain[] = ( data_b[5..5]);
ram_block1a[6].portbdatain[] = ( data_b[6..6]);
ram_block1a[7].portbdatain[] = ( data_b[7..7]);
ram_block1a[8].portbdatain[] = ( data_b[0..0]);
ram_block1a[9].portbdatain[] = ( data_b[1..1]);
ram_block1a[10].portbdatain[] = ( data_b[2..2]);
ram_block1a[11].portbdatain[] = ( data_b[3..3]);
ram_block1a[12].portbdatain[] = ( data_b[4..4]);
ram_block1a[13].portbdatain[] = ( data_b[5..5]);
ram_block1a[14].portbdatain[] = ( data_b[6..6]);
ram_block1a[15].portbdatain[] = ( data_b[7..7]);
ram_block1a[15..0].portbre = B"1111111111111111";
ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
address_a_sel[0..0] = address_a[13..13];
address_a_wire[] = address_a[];
address_b_sel[0..0] = address_b[13..13];
address_b_wire[] = address_b[];
q_a[] = mux4.result[];
q_b[] = mux5.result[];
w_addr_val_a2w[0..0] = address_a_wire[13..13];
w_addr_val_a7w[] = wren_decode_addr_sel_a[];
w_addr_val_b4w[0..0] = address_b_wire[13..13];
w_addr_val_b8w[] = wren_decode_addr_sel_b[];
wren_decode_addr_sel_a[0..0] = address_a_wire[13..13];
wren_decode_addr_sel_b[0..0] = address_b_wire[13..13];
END;
--VALID FILE
db/decode_jsa.tdf
+35
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=2 LPM_WIDTH=1 data enable eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 1
SUBDESIGN decode_jsa
(
data[0..0] : input;
enable : input;
eq[1..0] : output;
)
VARIABLE
eq_node[1..0] : WIRE;
BEGIN
eq[] = eq_node[];
eq_node[] = ( (data[] & enable), ((! data[]) & enable));
END;
--VALID FILE
db/logic_util_heursitic.dat
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db/prev_cmp_spectrum.qmsg
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db/spectrum.asm.qmsg
+6 -6
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635142046 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637238255 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:21 2022 " "Processing started: Wed Mar 30 13:12:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:18 2022 " "Processing started: Wed Mar 30 13:47:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648635143022 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648637239291 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648635143049 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648637239318 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:23 2022 " "Processing ended: Wed Mar 30 13:12:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648635143323 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:19 2022 " "Processing ended: Wed Mar 30 13:47:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648637239598 ""}
db/spectrum.asm.rdb
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db/spectrum.asm_labs.ddb
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db/spectrum.cbx.xml
+1
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@@ -1,6 +1,7 @@
<?xml version="1.0" ?> <?xml version="1.0" ?>
<LOG_ROOT> <LOG_ROOT>
<PROJECT NAME="spectrum"> <PROJECT NAME="spectrum">
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|ram16:ram0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_bui2.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/> <CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/>
</PROJECT> </PROJECT>
</LOG_ROOT> </LOG_ROOT>
db/spectrum.cmp.bpm
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db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
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db/spectrum.eda.qmsg
+12 -12
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@@ -1,12 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635147928 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637244327 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:27 2022 " "Processing started: Wed Mar 30 13:12:27 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing started: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148267 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244673 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148299 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244704 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148332 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244734 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148365 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244765 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148393 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244794 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148420 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244820 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148446 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244846 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148473 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244872 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "343 " "Peak virtual memory: 343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:28 2022 " "Processing ended: Wed Mar 30 13:12:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing ended: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""}
db/spectrum.fit.qmsg
+49 -48
View File
File diff suppressed because one or more lines are too long
db/spectrum.hier_info
+782 -5
View File
@@ -1,9 +1,9 @@
|spectrum |spectrum
CLOCK_50 => CLOCK_50.IN1 CLOCK_50 => CLOCK_50.IN2
LED[0] <= rom0:rom.q LED[0] <= ram16:ram0.q_a
LED[1] <= rom0:rom.q LED[1] <= ram16:ram0.q_a
LED[2] <= rom0:rom.q LED[2] <= ram16:ram0.q_a
LED[3] <= rom0:rom.q LED[3] <= ram16:ram0.q_a
LED[4] <= rom0:rom.q LED[4] <= rom0:rom.q
LED[5] <= rom0:rom.q LED[5] <= rom0:rom.q
LED[6] <= rom0:rom.q LED[6] <= rom0:rom.q
@@ -380,3 +380,780 @@ sel[0] => result_node[0].IN0
sel[0] => _.IN0 sel[0] => _.IN0
|spectrum|ram16:ram0
address_a[0] => address_a[0].IN1
address_a[1] => address_a[1].IN1
address_a[2] => address_a[2].IN1
address_a[3] => address_a[3].IN1
address_a[4] => address_a[4].IN1
address_a[5] => address_a[5].IN1
address_a[6] => address_a[6].IN1
address_a[7] => address_a[7].IN1
address_a[8] => address_a[8].IN1
address_a[9] => address_a[9].IN1
address_a[10] => address_a[10].IN1
address_a[11] => address_a[11].IN1
address_a[12] => address_a[12].IN1
address_a[13] => address_a[13].IN1
address_b[0] => address_b[0].IN1
address_b[1] => address_b[1].IN1
address_b[2] => address_b[2].IN1
address_b[3] => address_b[3].IN1
address_b[4] => address_b[4].IN1
address_b[5] => address_b[5].IN1
address_b[6] => address_b[6].IN1
address_b[7] => address_b[7].IN1
address_b[8] => address_b[8].IN1
address_b[9] => address_b[9].IN1
address_b[10] => address_b[10].IN1
address_b[11] => address_b[11].IN1
address_b[12] => address_b[12].IN1
address_b[13] => address_b[13].IN1
clock => clock.IN1
data_a[0] => data_a[0].IN1
data_a[1] => data_a[1].IN1
data_a[2] => data_a[2].IN1
data_a[3] => data_a[3].IN1
data_a[4] => data_a[4].IN1
data_a[5] => data_a[5].IN1
data_a[6] => data_a[6].IN1
data_a[7] => data_a[7].IN1
data_b[0] => data_b[0].IN1
data_b[1] => data_b[1].IN1
data_b[2] => data_b[2].IN1
data_b[3] => data_b[3].IN1
data_b[4] => data_b[4].IN1
data_b[5] => data_b[5].IN1
data_b[6] => data_b[6].IN1
data_b[7] => data_b[7].IN1
wren_a => wren_a.IN1
wren_b => wren_b.IN1
q_a[0] <= altsyncram:altsyncram_component.q_a
q_a[1] <= altsyncram:altsyncram_component.q_a
q_a[2] <= altsyncram:altsyncram_component.q_a
q_a[3] <= altsyncram:altsyncram_component.q_a
q_a[4] <= altsyncram:altsyncram_component.q_a
q_a[5] <= altsyncram:altsyncram_component.q_a
q_a[6] <= altsyncram:altsyncram_component.q_a
q_a[7] <= altsyncram:altsyncram_component.q_a
q_b[0] <= altsyncram:altsyncram_component.q_b
q_b[1] <= altsyncram:altsyncram_component.q_b
q_b[2] <= altsyncram:altsyncram_component.q_b
q_b[3] <= altsyncram:altsyncram_component.q_b
q_b[4] <= altsyncram:altsyncram_component.q_b
q_b[5] <= altsyncram:altsyncram_component.q_b
q_b[6] <= altsyncram:altsyncram_component.q_b
q_b[7] <= altsyncram:altsyncram_component.q_b
|spectrum|ram16:ram0|altsyncram:altsyncram_component
wren_a => altsyncram_bui2:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => altsyncram_bui2:auto_generated.wren_b
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_bui2:auto_generated.data_a[0]
data_a[1] => altsyncram_bui2:auto_generated.data_a[1]
data_a[2] => altsyncram_bui2:auto_generated.data_a[2]
data_a[3] => altsyncram_bui2:auto_generated.data_a[3]
data_a[4] => altsyncram_bui2:auto_generated.data_a[4]
data_a[5] => altsyncram_bui2:auto_generated.data_a[5]
data_a[6] => altsyncram_bui2:auto_generated.data_a[6]
data_a[7] => altsyncram_bui2:auto_generated.data_a[7]
data_b[0] => altsyncram_bui2:auto_generated.data_b[0]
data_b[1] => altsyncram_bui2:auto_generated.data_b[1]
data_b[2] => altsyncram_bui2:auto_generated.data_b[2]
data_b[3] => altsyncram_bui2:auto_generated.data_b[3]
data_b[4] => altsyncram_bui2:auto_generated.data_b[4]
data_b[5] => altsyncram_bui2:auto_generated.data_b[5]
data_b[6] => altsyncram_bui2:auto_generated.data_b[6]
data_b[7] => altsyncram_bui2:auto_generated.data_b[7]
address_a[0] => altsyncram_bui2:auto_generated.address_a[0]
address_a[1] => altsyncram_bui2:auto_generated.address_a[1]
address_a[2] => altsyncram_bui2:auto_generated.address_a[2]
address_a[3] => altsyncram_bui2:auto_generated.address_a[3]
address_a[4] => altsyncram_bui2:auto_generated.address_a[4]
address_a[5] => altsyncram_bui2:auto_generated.address_a[5]
address_a[6] => altsyncram_bui2:auto_generated.address_a[6]
address_a[7] => altsyncram_bui2:auto_generated.address_a[7]
address_a[8] => altsyncram_bui2:auto_generated.address_a[8]
address_a[9] => altsyncram_bui2:auto_generated.address_a[9]
address_a[10] => altsyncram_bui2:auto_generated.address_a[10]
address_a[11] => altsyncram_bui2:auto_generated.address_a[11]
address_a[12] => altsyncram_bui2:auto_generated.address_a[12]
address_a[13] => altsyncram_bui2:auto_generated.address_a[13]
address_b[0] => altsyncram_bui2:auto_generated.address_b[0]
address_b[1] => altsyncram_bui2:auto_generated.address_b[1]
address_b[2] => altsyncram_bui2:auto_generated.address_b[2]
address_b[3] => altsyncram_bui2:auto_generated.address_b[3]
address_b[4] => altsyncram_bui2:auto_generated.address_b[4]
address_b[5] => altsyncram_bui2:auto_generated.address_b[5]
address_b[6] => altsyncram_bui2:auto_generated.address_b[6]
address_b[7] => altsyncram_bui2:auto_generated.address_b[7]
address_b[8] => altsyncram_bui2:auto_generated.address_b[8]
address_b[9] => altsyncram_bui2:auto_generated.address_b[9]
address_b[10] => altsyncram_bui2:auto_generated.address_b[10]
address_b[11] => altsyncram_bui2:auto_generated.address_b[11]
address_b[12] => altsyncram_bui2:auto_generated.address_b[12]
address_b[13] => altsyncram_bui2:auto_generated.address_b[13]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_bui2:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_bui2:auto_generated.q_a[0]
q_a[1] <= altsyncram_bui2:auto_generated.q_a[1]
q_a[2] <= altsyncram_bui2:auto_generated.q_a[2]
q_a[3] <= altsyncram_bui2:auto_generated.q_a[3]
q_a[4] <= altsyncram_bui2:auto_generated.q_a[4]
q_a[5] <= altsyncram_bui2:auto_generated.q_a[5]
q_a[6] <= altsyncram_bui2:auto_generated.q_a[6]
q_a[7] <= altsyncram_bui2:auto_generated.q_a[7]
q_b[0] <= altsyncram_bui2:auto_generated.q_b[0]
q_b[1] <= altsyncram_bui2:auto_generated.q_b[1]
q_b[2] <= altsyncram_bui2:auto_generated.q_b[2]
q_b[3] <= altsyncram_bui2:auto_generated.q_b[3]
q_b[4] <= altsyncram_bui2:auto_generated.q_b[4]
q_b[5] <= altsyncram_bui2:auto_generated.q_b[5]
q_b[6] <= altsyncram_bui2:auto_generated.q_b[6]
q_b[7] <= altsyncram_bui2:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_jsa:decode2.data[0]
address_a[13] => decode_c8a:rden_decode_a.data[0]
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[9] => ram_block1a8.PORTBADDR9
address_b[9] => ram_block1a9.PORTBADDR9
address_b[9] => ram_block1a10.PORTBADDR9
address_b[9] => ram_block1a11.PORTBADDR9
address_b[9] => ram_block1a12.PORTBADDR9
address_b[9] => ram_block1a13.PORTBADDR9
address_b[9] => ram_block1a14.PORTBADDR9
address_b[9] => ram_block1a15.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
address_b[10] => ram_block1a8.PORTBADDR10
address_b[10] => ram_block1a9.PORTBADDR10
address_b[10] => ram_block1a10.PORTBADDR10
address_b[10] => ram_block1a11.PORTBADDR10
address_b[10] => ram_block1a12.PORTBADDR10
address_b[10] => ram_block1a13.PORTBADDR10
address_b[10] => ram_block1a14.PORTBADDR10
address_b[10] => ram_block1a15.PORTBADDR10
address_b[11] => ram_block1a0.PORTBADDR11
address_b[11] => ram_block1a1.PORTBADDR11
address_b[11] => ram_block1a2.PORTBADDR11
address_b[11] => ram_block1a3.PORTBADDR11
address_b[11] => ram_block1a4.PORTBADDR11
address_b[11] => ram_block1a5.PORTBADDR11
address_b[11] => ram_block1a6.PORTBADDR11
address_b[11] => ram_block1a7.PORTBADDR11
address_b[11] => ram_block1a8.PORTBADDR11
address_b[11] => ram_block1a9.PORTBADDR11
address_b[11] => ram_block1a10.PORTBADDR11
address_b[11] => ram_block1a11.PORTBADDR11
address_b[11] => ram_block1a12.PORTBADDR11
address_b[11] => ram_block1a13.PORTBADDR11
address_b[11] => ram_block1a14.PORTBADDR11
address_b[11] => ram_block1a15.PORTBADDR11
address_b[12] => ram_block1a0.PORTBADDR12
address_b[12] => ram_block1a1.PORTBADDR12
address_b[12] => ram_block1a2.PORTBADDR12
address_b[12] => ram_block1a3.PORTBADDR12
address_b[12] => ram_block1a4.PORTBADDR12
address_b[12] => ram_block1a5.PORTBADDR12
address_b[12] => ram_block1a6.PORTBADDR12
address_b[12] => ram_block1a7.PORTBADDR12
address_b[12] => ram_block1a8.PORTBADDR12
address_b[12] => ram_block1a9.PORTBADDR12
address_b[12] => ram_block1a10.PORTBADDR12
address_b[12] => ram_block1a11.PORTBADDR12
address_b[12] => ram_block1a12.PORTBADDR12
address_b[12] => ram_block1a13.PORTBADDR12
address_b[12] => ram_block1a14.PORTBADDR12
address_b[12] => ram_block1a15.PORTBADDR12
address_b[13] => address_reg_b[0].DATAIN
address_b[13] => decode_jsa:decode3.data[0]
address_b[13] => decode_c8a:rden_decode_b.data[0]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a0.CLK1
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a1.CLK1
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a2.CLK1
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a3.CLK1
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a4.CLK1
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a5.CLK1
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a6.CLK1
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a7.CLK1
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a8.CLK1
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a9.CLK1
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a10.CLK1
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a11.CLK1
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a12.CLK1
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a13.CLK1
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a14.CLK1
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a15.CLK1
clock0 => address_reg_a[0].CLK
clock0 => address_reg_b[0].CLK
clock0 => out_address_reg_a[0].CLK
clock0 => out_address_reg_b[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_b[0] => ram_block1a0.PORTBDATAIN
data_b[0] => ram_block1a8.PORTBDATAIN
data_b[1] => ram_block1a1.PORTBDATAIN
data_b[1] => ram_block1a9.PORTBDATAIN
data_b[2] => ram_block1a2.PORTBDATAIN
data_b[2] => ram_block1a10.PORTBDATAIN
data_b[3] => ram_block1a3.PORTBDATAIN
data_b[3] => ram_block1a11.PORTBDATAIN
data_b[4] => ram_block1a4.PORTBDATAIN
data_b[4] => ram_block1a12.PORTBDATAIN
data_b[5] => ram_block1a5.PORTBDATAIN
data_b[5] => ram_block1a13.PORTBDATAIN
data_b[6] => ram_block1a6.PORTBDATAIN
data_b[6] => ram_block1a14.PORTBDATAIN
data_b[7] => ram_block1a7.PORTBDATAIN
data_b[7] => ram_block1a15.PORTBDATAIN
q_a[0] <= mux_3nb:mux4.result[0]
q_a[1] <= mux_3nb:mux4.result[1]
q_a[2] <= mux_3nb:mux4.result[2]
q_a[3] <= mux_3nb:mux4.result[3]
q_a[4] <= mux_3nb:mux4.result[4]
q_a[5] <= mux_3nb:mux4.result[5]
q_a[6] <= mux_3nb:mux4.result[6]
q_a[7] <= mux_3nb:mux4.result[7]
q_b[0] <= mux_3nb:mux5.result[0]
q_b[1] <= mux_3nb:mux5.result[1]
q_b[2] <= mux_3nb:mux5.result[2]
q_b[3] <= mux_3nb:mux5.result[3]
q_b[4] <= mux_3nb:mux5.result[4]
q_b[5] <= mux_3nb:mux5.result[5]
q_b[6] <= mux_3nb:mux5.result[6]
q_b[7] <= mux_3nb:mux5.result[7]
wren_a => decode_jsa:decode2.enable
wren_b => decode_jsa:decode3.enable
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode3
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_a
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_b
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0
db/spectrum.hif
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<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR > <TR >
<TD >ram0|altsyncram_component|auto_generated|mux5</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|mux4</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|rden_decode_b</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|rden_decode_a</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|decode3</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated|decode2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0|altsyncram_component|auto_generated</TD>
<TD >47</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ram0</TD>
<TD >47</TD>
<TD >21</TD>
<TD >0</TD>
<TD >21</TD>
<TD >16</TD>
<TD >21</TD>
<TD >21</TD>
<TD >21</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >rom|altsyncram_component|auto_generated|mux2</TD> <TD >rom|altsyncram_component|auto_generated|mux2</TD>
<TD >17</TD> <TD >17</TD>
<TD >0</TD> <TD >0</TD>
db/spectrum.lpc.rdb
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+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Hierarchy : ram0|altsyncram_component|auto_generated|mux5
Input : 17
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|mux4
Input : 17
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|rden_decode_b
Input : 1
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|rden_decode_a
Input : 1
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|decode3
Input : 2
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated|decode2
Input : 2
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0|altsyncram_component|auto_generated
Input : 47
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 16
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : ram0
Input : 47
Constant Input : 21
Unused Input : 0
Floating Input : 21
Output : 16
Constant Output : 21
Unused Output : 21
Floating Output : 21
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : rom|altsyncram_component|auto_generated|mux2 Hierarchy : rom|altsyncram_component|auto_generated|mux2
Input : 17 Input : 17
Constant Input : 0 Constant Input : 0
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635144709 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637241068 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:24 2022 " "Processing started: Wed Mar 30 13:12:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:20 2022 " "Processing started: Wed Mar 30 13:47:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635144711 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637241070 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648635144738 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648637241098 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635144851 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637241220 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144852 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241222 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648635145098 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648637241477 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648635145098 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648637241477 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648637241608 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241609 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648635145226 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648637241610 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648635145236 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648637241625 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145248 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145248 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637241637 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637241637 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.788 " "Worst-case setup slack is -1.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.788 -88.557 CLOCK_50 " " -1.788 -88.557 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.812 " "Worst-case setup slack is -1.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.812 -85.179 CLOCK_50 " " -1.812 -85.179 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.260 " "Worst-case hold slack is 0.260" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.260 0.000 CLOCK_50 " " 0.260 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.836 CLOCK_50 " " -3.000 -110.836 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.480 CLOCK_50 " " -3.000 -119.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145268 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637241663 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648635145291 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648637241687 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648635145672 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648637242078 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145692 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242100 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145695 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145695 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242103 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242103 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.527 " "Worst-case setup slack is -1.527" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.527 -72.611 CLOCK_50 " " -1.527 -72.611 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.531 " "Worst-case setup slack is -1.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.531 -69.352 CLOCK_50 " " -1.531 -69.352 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.255 0.000 CLOCK_50 " " 0.255 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145699 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242107 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145700 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242108 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.824 CLOCK_50 " " -3.000 -110.824 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.478 CLOCK_50 " " -3.000 -119.478 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145717 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637242132 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145841 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242265 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145842 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145842 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242266 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242266 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.529 " "Worst-case setup slack is -0.529" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.529 -18.538 CLOCK_50 " " -0.529 -18.538 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -0.444 " "Worst-case setup slack is -0.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.444 -17.149 CLOCK_50 " " -0.444 -17.149 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.123 " "Worst-case hold slack is 0.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.123 0.000 CLOCK_50 " " 0.123 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145847 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242272 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145848 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242273 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -93.684 CLOCK_50 " " -3.000 -93.684 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.404 CLOCK_50 " " -3.000 -99.404 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146144 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146145 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "407 " "Peak virtual memory: 407 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:26 2022 " "Processing ended: Wed Mar 30 13:12:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "419 " "Peak virtual memory: 419 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:22 2022 " "Processing ended: Wed Mar 30 13:47:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""}
db/spectrum.sta.rdb
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db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
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db/spectrum.tiscmp.fast_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_85c.ddb
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db/spectrum.vpr.ammdb
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greybox_tmp/cbx_args.txt
+24 -3
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@@ -1,16 +1,37 @@
ADDRESS_ACLR_A=NONE ADDRESS_REG_B=CLOCK0
CLOCK_ENABLE_INPUT_A=BYPASS CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=./rom/gw03.hex CLOCK_ENABLE_OUTPUT_B=BYPASS
INDATA_REG_B=CLOCK0
INIT_FILE=./led_patterns.mif
INTENDED_DEVICE_FAMILY="Cyclone IV E" INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_TYPE=altsyncram
NUMWORDS_A=16384 NUMWORDS_A=16384
OPERATION_MODE=ROM NUMWORDS_B=16384
OPERATION_MODE=BIDIR_DUAL_PORT
OUTDATA_ACLR_A=NONE OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=CLOCK0 OUTDATA_REG_A=CLOCK0
OUTDATA_REG_B=CLOCK0
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
WIDTHAD_A=14 WIDTHAD_A=14
WIDTHAD_B=14
WIDTH_A=8 WIDTH_A=8
WIDTH_B=8
WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK0
DEVICE_FAMILY="Cyclone IV E" DEVICE_FAMILY="Cyclone IV E"
address_a address_a
address_b
clock0 clock0
data_a
data_b
wren_a
wren_b
q_a q_a
q_b
incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
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output_files/spectrum.asm.rpt
+8 -8
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@@ -1,5 +1,5 @@
Assembler report for spectrum Assembler report for spectrum
Wed Mar 30 13:12:23 2022 Wed Mar 30 13:47:19 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 30 13:12:23 2022 ; ; Assembler Status ; Successful - Wed Mar 30 13:47:19 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ; ; Option ; Setting ;
+----------------+-----------------------+ +----------------+-----------------------+
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x00315633 ; ; JTAG usercode ; 0x0021F0FE ;
; Checksum ; 0x00315633 ; ; Checksum ; 0x0021F0FE ;
+----------------+-----------------------+ +----------------+-----------------------+
@@ -173,14 +173,14 @@ Default Value : On
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:12:21 2022 Info: Processing started: Wed Mar 30 13:47:18 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 385 megabytes Info: Peak virtual memory: 375 megabytes
Info: Processing ended: Wed Mar 30 13:12:23 2022 Info: Processing ended: Wed Mar 30 13:47:19 2022
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.done
+1 -1
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@@ -1 +1 @@
Wed Mar 30 13:12:28 2022 Wed Mar 30 13:47:24 2022
output_files/spectrum.eda.rpt
+6 -6
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum EDA Netlist Writer report for spectrum
Wed Mar 30 13:12:28 2022 Wed Mar 30 13:47:24 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+ +-------------------------------------------------------------------+
; EDA Netlist Writer Summary ; ; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+ +---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:12:28 2022 ; ; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:47:24 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:12:27 2022 Info: Processing started: Wed Mar 30 13:47:24 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
@@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 343 megabytes Info: Peak virtual memory: 347 megabytes
Info: Processing ended: Wed Mar 30 13:12:28 2022 Info: Processing ended: Wed Mar 30 13:47:24 2022
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.fit.rpt
+4391 -2280
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output_files/spectrum.fit.summary
+4 -4
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@@ -1,16 +1,16 @@
Fitter Status : Successful - Wed Mar 30 13:12:20 2022 Fitter Status : Successful - Wed Mar 30 13:47:16 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Device : EP4CE22F17C6 Device : EP4CE22F17C6
Timing Models : Final Timing Models : Final
Total logic elements : 55 / 22,320 ( < 1 % ) Total logic elements : 50 / 22,320 ( < 1 % )
Total combinational functions : 52 / 22,320 ( < 1 % ) Total combinational functions : 48 / 22,320 ( < 1 % )
Dedicated logic registers : 38 / 22,320 ( < 1 % ) Dedicated logic registers : 38 / 22,320 ( < 1 % )
Total registers : 38 Total registers : 38
Total pins : 9 / 154 ( 6 % ) Total pins : 9 / 154 ( 6 % )
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 131,072 / 608,256 ( 22 % ) Total memory bits : 98,304 / 608,256 ( 16 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
output_files/spectrum.flow.rpt
+37 -19
View File
@@ -1,5 +1,5 @@
Flow report for spectrum Flow report for spectrum
Wed Mar 30 13:12:28 2022 Wed Mar 30 13:47:24 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,20 +40,20 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Mar 30 13:12:28 2022 ; ; Flow Status ; Successful - Wed Mar 30 13:47:24 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 55 / 22,320 ( < 1 % ) ; ; Total logic elements ; 50 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 52 / 22,320 ( < 1 % ) ; ; Total combinational functions ; 48 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
; Total registers ; 38 ; ; Total registers ; 38 ;
; Total pins ; 9 / 154 ( 6 % ) ; ; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 131,072 / 608,256 ( 22 % ) ; ; Total memory bits ; 98,304 / 608,256 ( 16 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/30/2022 13:12:12 ; ; Start date & time ; 03/30/2022 13:47:07 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
+-------------------+---------------------+ +-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164863513225804 Value : 0.164863722728310
Default Value : -- Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
@@ -97,6 +97,18 @@ Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
Assignment Name : IP_TOOL_NAME
Value : RAM: 2-PORT
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION Assignment Name : IP_TOOL_VERSION
Value : 13.1 Value : 13.1
Default Value : -- Default Value : --
@@ -121,6 +133,12 @@ Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
Assignment Name : MISC_FILE
Value : ram16_bb.v
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
Value : 1.2V Value : 1.2V
Default Value : -- Default Value : --
@@ -158,40 +176,40 @@ Section Id : --
; Flow Elapsed Time ; ; Flow Elapsed Time ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis Module Name : Analysis & Synthesis
Elapsed Time : 00:00:02 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 381 MB Peak Virtual Memory : 384 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:02
Module Name : Fitter Module Name : Fitter
Elapsed Time : 00:00:06 Elapsed Time : 00:00:07
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 595 MB Peak Virtual Memory : 594 MB
Total CPU Time (on all processors) : 00:00:06 Total CPU Time (on all processors) : 00:00:06
Module Name : Assembler Module Name : Assembler
Elapsed Time : 00:00:02 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 385 MB Peak Virtual Memory : 375 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : TimeQuest Timing Analyzer Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:02 Elapsed Time : 00:00:02
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 407 MB Peak Virtual Memory : 419 MB
Total CPU Time (on all processors) : 00:00:02 Total CPU Time (on all processors) : 00:00:02
Module Name : EDA Netlist Writer Module Name : EDA Netlist Writer
Elapsed Time : 00:00:01 Elapsed Time : 00:00:00
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 331 MB Peak Virtual Memory : 339 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : Total Module Name : Total
Elapsed Time : 00:00:13 Elapsed Time : 00:00:11
Average Processors Used : -- Average Processors Used : --
Peak Virtual Memory : -- Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:11 Total CPU Time (on all processors) : 00:00:12
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
output_files/spectrum.jdi
+1 -1
View File
@@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="517dc0b141e7ba08df4a"/> <hash md5_digest_80b="a9c298635caa38134033"/>
</project> </project>
<file_info> <file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/> <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+528 -44
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum Analysis & Synthesis report for spectrum
Wed Mar 30 13:12:13 2022 Wed Mar 30 13:47:09 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -15,12 +15,18 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
7. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary 8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary 9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics 10. Registers Removed During Synthesis
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated 11. Removed Registers Triggering Further Register Optimizations
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 12. General Register Statistics
13. altsyncram Parameter Settings by Entity Instance 13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
14. Elapsed Time Per Partition 14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
15. Analysis & Synthesis Messages 15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
17. altsyncram Parameter Settings by Entity Instance
18. Port Connectivity Checks: "ram16:ram0"
19. Port Connectivity Checks: "rom0:rom"
20. Elapsed Time Per Partition
21. Analysis & Synthesis Messages
@@ -46,18 +52,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ; ; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 54 ; ; Total logic elements ; 50 ;
; Total combinational functions ; 52 ; ; Total combinational functions ; 48 ;
; Dedicated logic registers ; 38 ; ; Dedicated logic registers ; 38 ;
; Total registers ; 38 ; ; Total registers ; 38 ;
; Total pins ; 9 ; ; Total pins ; 9 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 131,072 ; ; Total memory bits ; 98,304 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ; ; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -405,12 +411,24 @@ File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library : Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v File Name with User-Entered Path : rom0.v
Used in Netlist : yes Used in Netlist : yes
File Type : User Wizard-Generated File File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v
Library : Library :
File Name with User-Entered Path : ram16.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
Library :
File Name with User-Entered Path : altsyncram.tdf File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes Used in Netlist : yes
File Type : Megafunction File Type : Megafunction
@@ -488,6 +506,18 @@ Used in Netlist : yes
File Type : Auto-Generated Megafunction File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf
Library : Library :
File Name with User-Entered Path : db/altsyncram_bui2.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf
Library :
File Name with User-Entered Path : db/decode_jsa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
Library :
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -497,16 +527,16 @@ Library :
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Estimated Total logic elements ; 54 ; ; Estimated Total logic elements ; 50 ;
; ; ; ; ; ;
; Total combinational functions ; 52 ; ; Total combinational functions ; 48 ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 8 ; ; -- 4 input functions ; 7 ;
; -- 3 input functions ; 10 ; ; -- 3 input functions ; 6 ;
; -- <=2 input functions ; 34 ; ; -- <=2 input functions ; 35 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 20 ; ; -- normal mode ; 16 ;
; -- arithmetic mode ; 32 ; ; -- arithmetic mode ; 32 ;
; ; ; ; ; ;
; Total registers ; 38 ; ; Total registers ; 38 ;
@@ -514,12 +544,12 @@ Library :
; -- I/O registers ; 0 ; ; -- I/O registers ; 0 ;
; ; ; ; ; ;
; I/O pins ; 9 ; ; I/O pins ; 9 ;
; Total memory bits ; 131072 ; ; Total memory bits ; 98304 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ; ; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 54 ; ; Maximum fan-out ; 50 ;
; Total fan-out ; 473 ; ; Total fan-out ; 401 ;
; Average fan-out ; 3.81 ; ; Average fan-out ; 3.46 ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
@@ -527,9 +557,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum Compilation Hierarchy Node : |spectrum
LC Combinationals : 52 (44) LC Combinationals : 48 (44)
LC Registers : 38 (36) LC Registers : 38 (36)
Memory Bits : 131072 Memory Bits : 98304
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -538,10 +568,46 @@ Virtual Pins : 0
Full Hierarchy Name : |spectrum Full Hierarchy Name : |spectrum
Library Name : work Library Name : work
Compilation Hierarchy Node : |ram16:ram0|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
Library Name : work
Compilation Hierarchy Node : |rom0:rom| Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 8 (0) LC Combinationals : 4 (0)
LC Registers : 2 (0) LC Registers : 2 (0)
Memory Bits : 131072 Memory Bits : 65536
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -551,9 +617,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component| Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 8 (0) LC Combinationals : 4 (0)
LC Registers : 2 (0) LC Registers : 2 (0)
Memory Bits : 131072 Memory Bits : 65536
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -563,9 +629,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
LC Combinationals : 8 (0) LC Combinationals : 4 (0)
LC Registers : 2 (2) LC Registers : 2 (2)
Memory Bits : 131072 Memory Bits : 65536
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -575,7 +641,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
Library Name : work Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2| Compilation Hierarchy Node : |mux_3nb:mux2|
LC Combinationals : 8 (8) LC Combinationals : 4 (4)
LC Registers : 0 (0) LC Registers : 0 (0)
Memory Bits : 0 Memory Bits : 0
DSP Elements : 0 DSP Elements : 0
@@ -593,6 +659,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ; ; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : True Dual Port
Port A Depth : 16384
Port A Width : 8
Port B Depth : 16384
Port B Width : 8
Size : 131072
MIF : led_patterns.mif
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO Type : AUTO
Mode : ROM Mode : ROM
@@ -609,6 +685,14 @@ MIF : ./rom/gw03.hex
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ; ; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Vendor : Altera
IP Core Name : RAM: 2-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram16:ram0
IP Include File : /home/benny/work/fpga/projects/ram16.v
Vendor : Altera Vendor : Altera
IP Core Name : ROM: 1-PORT IP Core Name : ROM: 1-PORT
Version : 13.1 Version : 13.1
@@ -620,6 +704,42 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; address[0] ; Merged with A[0] ;
; address[1] ; Merged with A[1] ;
; address[2] ; Merged with A[2] ;
; address[3] ; Merged with A[3] ;
; address[4] ; Merged with A[4] ;
; address[5] ; Merged with A[5] ;
; address[6] ; Merged with A[6] ;
; address[7] ; Merged with A[7] ;
; address[8] ; Merged with A[8] ;
; address[9] ; Merged with A[9] ;
; address[10] ; Merged with A[10] ;
; address[11] ; Merged with A[11] ;
; address[12] ; Merged with A[12] ;
; address[13] ; Merged with A[13] ;
; A[14,15] ; Lost fanout ;
; Total Number of Removed Registers = 18 ; ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------+
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
+--------------------------------------------------------------------------------+
+------------------------------------------------------+ +------------------------------------------------------+
; General Register Statistics ; ; General Register Statistics ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@@ -646,6 +766,17 @@ To : -
+--------------------------------------------------------------------------------+
; Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; ; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -861,12 +992,227 @@ Type : Untyped
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : BIDIR_DUAL_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_B
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_B
Value : 16384
Type : Signed Integer
Parameter Name : INDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Signed Integer
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_bui2
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ; ; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+------------------------------------------+ +-------------------------------------------+--------------------------------------------+
; Name ; Value ; ; Name ; Value ;
+-------------------------------------------+------------------------------------------+ +-------------------------------------------+--------------------------------------------+
; Number of entity instances ; 1 ; ; Number of entity instances ; 2 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; ; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ; ; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ; ; -- WIDTH_A ; 8 ;
@@ -878,7 +1224,80 @@ Note: In order to hide this table in the UI and the text report file, please set
; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ; ; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+------------------------------------------+ ; Entity Instance ; ram16:ram0|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; BIDIR_DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 16384 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; CLOCK0 ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram16:ram0" ;
+--------------------------------------------------------------------------------+
Port : address_a
Type : Input
Severity : Warning
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : address_a[13..3]
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_a[7..4]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_a
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_a[-1]
Type : Input
Severity : Info
Details : Stuck at GND
Port : data_b
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_b
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_b
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_b[-1]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "rom0:rom" ;
+--------------------------------------------------------------------------------+
Port : q[3..0]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
+-------------------------------+ +-------------------------------+
@@ -896,16 +1315,20 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:12:11 2022 Info: Processing started: Wed Mar 30 13:47:07 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum Info (12023): Found entity 1: spectrum
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0 Info (12023): Found entity 1: rom0
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
Info (12023): Found entity 1: ram16
Info (12127): Elaborating entity "spectrum" for the top level hierarchy Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22) Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14) Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
@@ -933,17 +1356,78 @@ Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2" Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
Info (12128): Elaborating entity "ram16" for hierarchy "ram16:ram0"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram16:ram0|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram16:ram0|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram16:ram0|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_reg_b" = "CLOCK0"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
Info (12134): Parameter "indata_reg_b" = "CLOCK0"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "numwords_b" = "16384"
Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_aclr_b" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "widthad_b" = "14"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_b" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12134): Parameter "width_byteena_b" = "1"
Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf
Info (12023): Found entity 1: altsyncram_bui2
Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (286030): Timing-Driven Synthesis is running Info (286030): Timing-Driven Synthesis is running
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins Info (21059): Implemented 8 output pins
Info (21061): Implemented 54 logic cells Info (21061): Implemented 50 logic cells
Info (21064): Implemented 16 RAM segments Info (21064): Implemented 12 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings
Info: Peak virtual memory: 392 megabytes Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 13:12:13 2022 Info: Processing ended: Wed Mar 30 13:47:09 2022
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.map.summary
+4 -4
View File
@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Mar 30 13:12:13 2022 Analysis & Synthesis Status : Successful - Wed Mar 30 13:47:09 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Total logic elements : 54 Total logic elements : 50
Total combinational functions : 52 Total combinational functions : 48
Dedicated logic registers : 38 Dedicated logic registers : 38
Total registers : 38 Total registers : 38
Total pins : 9 Total pins : 9
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 131,072 Total memory bits : 98,304
Embedded Multiplier 9-bit elements : 0 Embedded Multiplier 9-bit elements : 0
Total PLLs : 0 Total PLLs : 0
output_files/spectrum.sof
BIN
View File
Binary file not shown.
output_files/spectrum.sta.rpt
+4589 -4589
View File
File diff suppressed because it is too large Load Diff
output_files/spectrum.sta.summary
+12 -12
View File
@@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50' Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -1.788 Slack : -1.812
TNS : -88.557 TNS : -85.179
Type : Slow 1200mV 85C Model Hold 'CLOCK_50' Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.260 Slack : 0.343
TNS : 0.000 TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -110.836 TNS : -119.480
Type : Slow 1200mV 0C Model Setup 'CLOCK_50' Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -1.527 Slack : -1.531
TNS : -72.611 TNS : -69.352
Type : Slow 1200mV 0C Model Hold 'CLOCK_50' Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.255 Slack : 0.299
TNS : 0.000 TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -110.824 TNS : -119.478
Type : Fast 1200mV 0C Model Setup 'CLOCK_50' Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -0.529 Slack : -0.444
TNS : -18.538 TNS : -17.149
Type : Fast 1200mV 0C Model Hold 'CLOCK_50' Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.123 Slack : 0.178
TNS : 0.000 TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -93.684 TNS : -99.404
------------------------------------------------------------ ------------------------------------------------------------
ram16.qip
+4
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@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram16.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram16_bb.v"]
ram16.v
+244
View File
@@ -0,0 +1,244 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram16 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "led_patterns.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]"
// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
ram16_bb.v
+180
View File
@@ -0,0 +1,180 @@
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram16 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]"
// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
simulation/modelsim/spectrum.vo
+1157 -1439
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simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
+1157 -1439
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simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
+1242 -1348
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simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
+1157 -1439
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simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
+1499 -1605
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simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
+1157 -1439
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simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
+1226 -1332
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simulation/modelsim/spectrum_modelsim.xrf
+49 -54
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@@ -4,6 +4,8 @@ source_file = 1, /home/benny/work/fpga/projects/output_files/led_patterns.mif
source_file = 1, /home/benny/work/fpga/projects/led_patterns.mif source_file = 1, /home/benny/work/fpga/projects/led_patterns.mif
source_file = 1, /home/benny/work/fpga/projects/rom0.qip source_file = 1, /home/benny/work/fpga/projects/rom0.qip
source_file = 1, /home/benny/work/fpga/projects/rom0.v source_file = 1, /home/benny/work/fpga/projects/rom0.v
source_file = 1, /home/benny/work/fpga/projects/ram16.qip
source_file = 1, /home/benny/work/fpga/projects/ram16.v
source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
@@ -19,6 +21,8 @@ source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf
source_file = 1, /home/benny/work/fpga/projects/rom/gw03.hex source_file = 1, /home/benny/work/fpga/projects/rom/gw03.hex
source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf
source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf
source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf
source_file = 1, /home/benny/work/fpga/projects/db/decode_jsa.tdf
design_name = spectrum design_name = spectrum
instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1
instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1
@@ -53,7 +57,6 @@ instance = comp, \counter[9] , counter[9], spectrum, 1
instance = comp, \counter[10]~39 , counter[10]~39, spectrum, 1 instance = comp, \counter[10]~39 , counter[10]~39, spectrum, 1
instance = comp, \counter[10] , counter[10], spectrum, 1 instance = comp, \counter[10] , counter[10], spectrum, 1
instance = comp, \counter[11]~41 , counter[11]~41, spectrum, 1 instance = comp, \counter[11]~41 , counter[11]~41, spectrum, 1
instance = comp, \counter[11]~feeder , counter[11]~feeder, spectrum, 1
instance = comp, \counter[11] , counter[11], spectrum, 1 instance = comp, \counter[11] , counter[11], spectrum, 1
instance = comp, \counter[12]~43 , counter[12]~43, spectrum, 1 instance = comp, \counter[12]~43 , counter[12]~43, spectrum, 1
instance = comp, \counter[12] , counter[12], spectrum, 1 instance = comp, \counter[12] , counter[12], spectrum, 1
@@ -71,71 +74,63 @@ instance = comp, \counter[18]~55 , counter[18]~55, spectrum, 1
instance = comp, \counter[18] , counter[18], spectrum, 1 instance = comp, \counter[18] , counter[18], spectrum, 1
instance = comp, \counter[19]~57 , counter[19]~57, spectrum, 1 instance = comp, \counter[19]~57 , counter[19]~57, spectrum, 1
instance = comp, \counter[19] , counter[19], spectrum, 1 instance = comp, \counter[19] , counter[19], spectrum, 1
instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1
instance = comp, \counter[20] , counter[20], spectrum, 1
instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1
instance = comp, \counter[21] , counter[21], spectrum, 1
instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 instance = comp, \Equal0~5 , Equal0~5, spectrum, 1
instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 instance = comp, \Equal0~0 , Equal0~0, spectrum, 1
instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 instance = comp, \Equal0~1 , Equal0~1, spectrum, 1
instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 instance = comp, \Equal0~2 , Equal0~2, spectrum, 1
instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 instance = comp, \Equal0~3 , Equal0~3, spectrum, 1
instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 instance = comp, \Equal0~4 , Equal0~4, spectrum, 1
instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1
instance = comp, \counter[20] , counter[20], spectrum, 1
instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1
instance = comp, \counter[21] , counter[21], spectrum, 1
instance = comp, \Equal0~7 , Equal0~7, spectrum, 1
instance = comp, \address[0]~39 , address[0]~39, spectrum, 1
instance = comp, \address[0] , address[0], spectrum, 1
instance = comp, \address[1]~13 , address[1]~13, spectrum, 1
instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 instance = comp, \Equal0~6 , Equal0~6, spectrum, 1
instance = comp, \address[1] , address[1], spectrum, 1 instance = comp, \A[0]~39 , A[0]~39, spectrum, 1
instance = comp, \address[2]~15 , address[2]~15, spectrum, 1 instance = comp, \A[0] , A[0], spectrum, 1
instance = comp, \address[2] , address[2], spectrum, 1 instance = comp, \A[1]~13 , A[1]~13, spectrum, 1
instance = comp, \address[3]~17 , address[3]~17, spectrum, 1 instance = comp, \A[1] , A[1], spectrum, 1
instance = comp, \address[3] , address[3], spectrum, 1 instance = comp, \A[2]~15 , A[2]~15, spectrum, 1
instance = comp, \address[4]~19 , address[4]~19, spectrum, 1 instance = comp, \A[2] , A[2], spectrum, 1
instance = comp, \address[4] , address[4], spectrum, 1 instance = comp, \A[3]~17 , A[3]~17, spectrum, 1
instance = comp, \address[5]~21 , address[5]~21, spectrum, 1 instance = comp, \A[3] , A[3], spectrum, 1
instance = comp, \address[5] , address[5], spectrum, 1 instance = comp, \A[4]~19 , A[4]~19, spectrum, 1
instance = comp, \address[6]~23 , address[6]~23, spectrum, 1 instance = comp, \A[4] , A[4], spectrum, 1
instance = comp, \address[6] , address[6], spectrum, 1 instance = comp, \A[5]~21 , A[5]~21, spectrum, 1
instance = comp, \address[7]~25 , address[7]~25, spectrum, 1 instance = comp, \A[5] , A[5], spectrum, 1
instance = comp, \address[7] , address[7], spectrum, 1 instance = comp, \A[6]~23 , A[6]~23, spectrum, 1
instance = comp, \address[8]~27 , address[8]~27, spectrum, 1 instance = comp, \A[6] , A[6], spectrum, 1
instance = comp, \address[8] , address[8], spectrum, 1 instance = comp, \A[7]~25 , A[7]~25, spectrum, 1
instance = comp, \address[9]~29 , address[9]~29, spectrum, 1 instance = comp, \A[7] , A[7], spectrum, 1
instance = comp, \address[9] , address[9], spectrum, 1 instance = comp, \A[8]~27 , A[8]~27, spectrum, 1
instance = comp, \address[10]~31 , address[10]~31, spectrum, 1 instance = comp, \A[8] , A[8], spectrum, 1
instance = comp, \address[10] , address[10], spectrum, 1 instance = comp, \A[9]~29 , A[9]~29, spectrum, 1
instance = comp, \address[11]~33 , address[11]~33, spectrum, 1 instance = comp, \A[9] , A[9], spectrum, 1
instance = comp, \address[11] , address[11], spectrum, 1 instance = comp, \A[10]~31 , A[10]~31, spectrum, 1
instance = comp, \address[12]~35 , address[12]~35, spectrum, 1 instance = comp, \A[10] , A[10], spectrum, 1
instance = comp, \address[12] , address[12], spectrum, 1 instance = comp, \A[11]~33 , A[11]~33, spectrum, 1
instance = comp, \address[13]~37 , address[13]~37, spectrum, 1 instance = comp, \A[11] , A[11], spectrum, 1
instance = comp, \address[13] , address[13], spectrum, 1 instance = comp, \A[12]~35 , A[12]~35, spectrum, 1
instance = comp, \A[12] , A[12], spectrum, 1
instance = comp, \A[13]~37 , A[13]~37, spectrum, 1
instance = comp, \A[13] , A[13], spectrum, 1
instance = comp, \~GND , ~GND, spectrum, 1
instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1
instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1
instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1
instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~0, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[3]~3, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~4, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~1, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~6, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~2, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~3, spectrum, 1
simulation/modelsim/spectrum_v.sdo
+1499 -1605
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File diff suppressed because it is too large Load Diff
spectrum.qsf
+1
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@@ -410,4 +410,5 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MIF_FILE output_files/led_patterns.mif set_global_assignment -name MIF_FILE output_files/led_patterns.mif
set_global_assignment -name MIF_FILE led_patterns.mif set_global_assignment -name MIF_FILE led_patterns.mif
set_global_assignment -name QIP_FILE rom0.qip set_global_assignment -name QIP_FILE rom0.qip
set_global_assignment -name QIP_FILE ram16.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
spectrum.v
+30 -1
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@@ -12,13 +12,42 @@ rom0 rom(
.q(mem_data) .q(mem_data)
); );
reg [15:0] A; // Global address bus
wire [7:0] D; // CPU data bus
wire [7:0] ram_data; // Internal 16K RAM data
wire RamWE;
// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;
assign RamWE = 0;
wire[12:0] vram_address;
wire[7:0] vram_data;
ram16 ram0(
.clock(CLOCK_50),
.address_a({12'b0, A[2:0]}),
.data_a(D),
.q_a(ram_data),
.wren_a(0),
// .address_b({1'b0, vram_address}),
.address_b(A[13:0]),
.data_b(8'b0),
.q_b(vram_data),
.wren_b(0)
);
reg[21:0] counter; reg[21:0] counter;
always @(posedge CLOCK_50) always @(posedge CLOCK_50)
begin begin
counter <= counter + 1; counter <= counter + 1;
if (counter == 0) if (counter == 0)
begin
address <= address + 1; address <= address + 1;
A <= A + 1;
end end
assign LED = mem_data; end
assign LED[3:0] = ram_data[3:0];
assign LED[7:4] = mem_data[7:4];
endmodule endmodule