diff --git a/db/altsyncram_88g2.tdf b/db/altsyncram_88g2.tdf new file mode 100644 index 0000000..85aa1b4 --- /dev/null +++ b/db/altsyncram_88g2.tdf @@ -0,0 +1,747 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_jsa (data[0..0], enable) +RETURNS ( eq[1..0]); +FUNCTION decode_c8a (data[0..0]) +RETURNS ( eq[1..0]); +FUNCTION mux_3nb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 2 M9K 16 reg 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_88g2 +( + address_a[13..0] : input; + address_b[13..0] : input; + clock0 : input; + data_a[7..0] : input; + data_b[7..0] : input; + q_a[7..0] : output; + q_b[7..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + address_reg_a[0..0] : dffe; + address_reg_b[0..0] : dffe; + out_address_reg_a[0..0] : dffe; + out_address_reg_b[0..0] : dffe; + decode2 : decode_jsa; + decode3 : decode_jsa; + rden_decode_a : decode_c8a; + rden_decode_b : decode_c8a; + mux4 : mux_3nb; + mux5 : mux_3nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[0..0] : WIRE; + address_a_wire[13..0] : WIRE; + address_b_sel[0..0] : WIRE; + address_b_wire[13..0] : WIRE; + w_addr_val_a7w[0..0] : WIRE; + w_addr_val_b4w[0..0] : WIRE; + w_addr_val_b8w[0..0] : WIRE; + wren_decode_addr_sel_a[0..0] : WIRE; + wren_decode_addr_sel_b[0..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + out_address_reg_b[].clk = clock0; + out_address_reg_b[].d = address_reg_b[].q; + decode2.data[0..0] = address_a_wire[13..13]; + decode2.enable = wren_a; + decode3.data[] = w_addr_val_b4w[]; + decode3.enable = wren_b; + rden_decode_a.data[] = w_addr_val_a7w[]; + rden_decode_b.data[] = w_addr_val_b8w[]; + mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]); + mux4.sel[] = out_address_reg_a[].q; + mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]); + mux5.sel[] = out_address_reg_b[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].clk1 = clock0; + ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]); + ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]); + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[15..0].portare = B"1111111111111111"; + ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[0..0]); + ram_block1a[9].portbdatain[] = ( data_b[1..1]); + ram_block1a[10].portbdatain[] = ( data_b[2..2]); + ram_block1a[11].portbdatain[] = ( data_b[3..3]); + ram_block1a[12].portbdatain[] = ( data_b[4..4]); + ram_block1a[13].portbdatain[] = ( data_b[5..5]); + ram_block1a[14].portbdatain[] = ( data_b[6..6]); + ram_block1a[15].portbdatain[] = ( data_b[7..7]); + ram_block1a[15..0].portbre = B"1111111111111111"; + ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[0..0] = address_a[13..13]; + address_a_wire[] = address_a[]; + address_b_sel[0..0] = address_b[13..13]; + address_b_wire[] = address_b[]; + q_a[] = mux4.result[]; + q_b[] = mux5.result[]; + w_addr_val_a7w[] = wren_decode_addr_sel_a[]; + w_addr_val_b4w[0..0] = address_b_wire[13..13]; + w_addr_val_b8w[] = wren_decode_addr_sel_b[]; + wren_decode_addr_sel_a[0..0] = address_a_wire[13..13]; + wren_decode_addr_sel_b[0..0] = address_b_wire[13..13]; +END; +--VALID FILE diff --git a/db/altsyncram_bui2.tdf b/db/altsyncram_bui2.tdf new file mode 100644 index 0000000..8f0438d --- /dev/null +++ b/db/altsyncram_bui2.tdf @@ -0,0 +1,781 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK0" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_jsa (data[0..0], enable) +RETURNS ( eq[1..0]); +FUNCTION decode_c8a (data[0..0]) +RETURNS ( eq[1..0]); +FUNCTION mux_3nb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 16 reg 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_bui2 +( + address_a[13..0] : input; + address_b[13..0] : input; + clock0 : input; + data_a[7..0] : input; + data_b[7..0] : input; + q_a[7..0] : output; + q_b[7..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + address_reg_a[0..0] : dffe; + address_reg_b[0..0] : dffe; + out_address_reg_a[0..0] : dffe; + out_address_reg_b[0..0] : dffe; + decode2 : decode_jsa; + decode3 : decode_jsa; + rden_decode_a : decode_c8a; + rden_decode_b : decode_c8a; + mux4 : mux_3nb; + mux5 : mux_3nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CLK1_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock1", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_OUT_CLOCK = "clock1", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + POWER_UP_UNINITIALIZED = "false", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[0..0] : WIRE; + address_a_wire[13..0] : WIRE; + address_b_sel[0..0] : WIRE; + address_b_wire[13..0] : WIRE; + w_addr_val_a2w[0..0] : WIRE; + w_addr_val_a7w[0..0] : WIRE; + w_addr_val_b4w[0..0] : WIRE; + w_addr_val_b8w[0..0] : WIRE; + wren_decode_addr_sel_a[0..0] : WIRE; + wren_decode_addr_sel_b[0..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + out_address_reg_b[].clk = clock0; + out_address_reg_b[].d = address_reg_b[].q; + decode2.data[] = w_addr_val_a2w[]; + decode2.enable = wren_a; + decode3.data[] = w_addr_val_b4w[]; + decode3.enable = wren_b; + rden_decode_a.data[] = w_addr_val_a7w[]; + rden_decode_b.data[] = w_addr_val_b8w[]; + mux4.data[] = ( ram_block1a[15..0].portadataout[0..0]); + mux4.sel[] = out_address_reg_a[].q; + mux5.data[] = ( ram_block1a[15..0].portbdataout[0..0]); + mux5.sel[] = out_address_reg_b[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].clk1 = clock0; + ram_block1a[15..0].ena0 = ( rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..1], rden_decode_a.eq[1..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0], rden_decode_a.eq[0..0]); + ram_block1a[15..0].ena1 = ( rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..1], rden_decode_b.eq[1..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0], rden_decode_b.eq[0..0]); + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[15..0].portare = B"1111111111111111"; + ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[0..0]); + ram_block1a[9].portbdatain[] = ( data_b[1..1]); + ram_block1a[10].portbdatain[] = ( data_b[2..2]); + ram_block1a[11].portbdatain[] = ( data_b[3..3]); + ram_block1a[12].portbdatain[] = ( data_b[4..4]); + ram_block1a[13].portbdatain[] = ( data_b[5..5]); + ram_block1a[14].portbdatain[] = ( data_b[6..6]); + ram_block1a[15].portbdatain[] = ( data_b[7..7]); + ram_block1a[15..0].portbre = B"1111111111111111"; + ram_block1a[15..0].portbwe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[0..0] = address_a[13..13]; + address_a_wire[] = address_a[]; + address_b_sel[0..0] = address_b[13..13]; + address_b_wire[] = address_b[]; + q_a[] = mux4.result[]; + q_b[] = mux5.result[]; + w_addr_val_a2w[0..0] = address_a_wire[13..13]; + w_addr_val_a7w[] = wren_decode_addr_sel_a[]; + w_addr_val_b4w[0..0] = address_b_wire[13..13]; + w_addr_val_b8w[] = wren_decode_addr_sel_b[]; + wren_decode_addr_sel_a[0..0] = address_a_wire[13..13]; + wren_decode_addr_sel_b[0..0] = address_b_wire[13..13]; +END; +--VALID FILE diff --git a/db/decode_jsa.tdf b/db/decode_jsa.tdf new file mode 100644 index 0000000..a6753e2 --- /dev/null +++ b/db/decode_jsa.tdf @@ -0,0 +1,35 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=2 LPM_WIDTH=1 data enable eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 1 +SUBDESIGN decode_jsa +( + data[0..0] : input; + enable : input; + eq[1..0] : output; +) +VARIABLE + eq_node[1..0] : WIRE; + +BEGIN + eq[] = eq_node[]; + eq_node[] = ( (data[] & enable), ((! data[]) & enable)); +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index 793e066..4c0e94d 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 0881b5a..1209810 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,139 +1,154 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634803174 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:43 2022 " "Processing started: Wed Mar 30 13:06:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648634803341 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803407 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803407 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648634803460 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(18) " "Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648634803462 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(20) " "Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648634803462 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803472 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803521 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648634803522 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803569 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803569 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803570 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803611 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803612 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803653 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803653 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803654 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648634804177 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648634804394 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648634804394 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "101 " "Implemented 101 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_LCELLS" "76 " "Implemented 76 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648634804440 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648634804440 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "392 " "Peak virtual memory: 392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:44 2022 " "Processing ended: Wed Mar 30 13:06:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634805764 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634805765 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:45 2022 " "Processing started: Wed Mar 30 13:06:45 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634805765 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648634805765 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648634805765 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648634805789 ""} -{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648634805790 ""} -{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648634805790 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648634805837 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648634805841 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805881 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805882 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805882 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648634805956 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648634805967 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648634806173 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 601 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 603 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 605 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 609 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648634806178 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648634806180 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648634806182 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648634806857 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648634806858 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648634806860 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648634806860 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648634806861 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648634806870 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 596 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648634806870 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648634807110 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648634807111 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648634807111 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648634807112 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648634807112 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648634807113 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648634807113 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648634807113 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648634807113 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648634807114 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648634807114 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648634807129 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634807135 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648634808106 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634808179 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648634808188 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648634808979 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634808979 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648634809228 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648634809877 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648634809877 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634810349 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648634810350 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648634810350 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648634810362 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648634810415 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648634810595 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648634810641 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648634810790 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634811085 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648634811434 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648634811437 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648634811437 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648634811493 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:51 2022 " "Processing ended: Wed Mar 30 13:06:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648634811738 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648634813398 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634813399 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:53 2022 " "Processing started: Wed Mar 30 13:06:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634813399 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648634813399 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648634813399 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648634814362 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648634814388 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:54 2022 " "Processing ended: Wed Mar 30 13:06:54 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648634814651 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648634814756 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648634816039 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:55 2022 " "Processing started: Wed Mar 30 13:06:55 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634816040 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648634816067 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648634816188 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816190 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816236 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816236 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648634816441 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648634816442 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816443 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816443 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648634816572 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816573 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648634816573 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648634816584 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634816597 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634816597 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.318 " "Worst-case setup slack is -3.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.318 -121.810 CLOCK_50 " " -3.318 -121.810 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.345 " "Worst-case hold slack is 0.345" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.345 0.000 CLOCK_50 " " 0.345 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634816600 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634816600 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.850 CLOCK_50 " " -3.000 -110.850 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648634816618 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648634816642 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648634817030 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817051 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634817054 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634817054 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.835 " "Worst-case setup slack is -2.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.835 -101.390 CLOCK_50 " " -2.835 -101.390 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817058 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817059 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.818 CLOCK_50 " " -3.000 -110.818 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648634817078 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817204 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634817204 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634817204 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.447 " "Worst-case setup slack is -1.447" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.447 -37.857 CLOCK_50 " " -1.447 -37.857 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 CLOCK_50 " " 0.179 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817210 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817211 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -94.264 CLOCK_50 " " -3.000 -94.264 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648634817512 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648634817513 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "418 " "Peak virtual memory: 418 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:57 2022 " "Processing ended: Wed Mar 30 13:06:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634819209 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:59 2022 " "Processing started: Wed Mar 30 13:06:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819534 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819566 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819600 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819632 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819660 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819685 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819711 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819737 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:59 2022 " "Processing ended: Wed Mar 30 13:06:59 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 160 s " "Quartus II Full Compilation was successful. 0 errors, 160 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634819883 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637110730 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637110731 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:45:10 2022 " "Processing started: Wed Mar 30 13:45:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637110731 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637110731 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637110731 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637110904 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637110973 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637110973 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637110976 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637110976 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637110977 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637110977 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648637111033 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RamWE spectrum.v(19) " "Verilog HDL or VHDL warning at spectrum.v(19): object \"RamWE\" assigned a value but never read" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1648637111035 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(43) " "Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637111036 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(46) " "Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 46 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637111036 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 spectrum.v(47) " "Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637111036 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111049 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111099 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111100 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111101 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637111101 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637111150 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637111150 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111150 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637111193 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637111193 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111194 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637111237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637111237 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111237 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.v" "ram0" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111240 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111244 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111245 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637111245 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bui2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bui2 " "Found entity 1: altsyncram_bui2" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637111294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637111294 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bui2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated " "Elaborating entity \"altsyncram_bui2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111295 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637111338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637111338 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_bui2.tdf" "decode2" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637111338 ""} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 376 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 416 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 456 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 496 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 536 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 576 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 616 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 656 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 42 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 64 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 86 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 108 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a4 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 130 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a5 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a5\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 152 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a6 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a6\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 174 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a7 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a7\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 196 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 218 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 240 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 262 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 284 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a12 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 306 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a13 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 328 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a14 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 350 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a15 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 372 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637111397 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1648637111397 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1648637111397 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648637111767 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648637111893 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "16 " "16 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648637111997 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648637112121 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637112121 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "61 " "Implemented 61 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648637112170 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648637112170 ""} { "Info" "ICUT_CUT_TM_LCELLS" "44 " "Implemented 44 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648637112170 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648637112170 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648637112170 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637112180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:45:12 2022 " "Processing ended: Wed Mar 30 13:45:12 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637112180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637112180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637112180 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637112180 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637113573 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637113574 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:45:13 2022 " "Processing started: Wed Mar 30 13:45:13 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637113574 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648637113574 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648637113574 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648637113600 ""} +{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648637113601 ""} +{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648637113601 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648637113649 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648637113653 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637113697 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637113698 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637113698 ""} +{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637113759 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"} } { } 0 119042 "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" 0 0 "Fitter" 0 -1 1648637113759 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648637113777 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648637113789 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637114002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637114002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637114002 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648637114002 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 601 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637114007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 603 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637114007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 605 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637114007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637114007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 609 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637114007 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648637114007 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648637114009 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648637114011 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648637114720 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648637114721 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648637114724 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648637114724 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648637114724 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648637114734 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 598 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648637114734 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648637114995 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637114995 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637114996 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637114997 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637114997 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648637114998 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648637114998 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648637114998 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648637114998 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648637114998 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648637114998 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637115014 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648637115014 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637115021 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648637116070 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637116143 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648637116151 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648637116826 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637116826 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648637117090 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y23 X31_Y34 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y23 to location X31_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y23 to location X31_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y23 to location X31_Y34"} 21 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648637117779 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648637117779 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637118253 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648637118253 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648637118253 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648637118268 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637118324 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637118505 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637118553 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637118702 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637119034 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648637119422 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 26 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648637119425 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648637119425 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648637119481 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "592 " "Peak virtual memory: 592 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637119723 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:45:19 2022 " "Processing ended: Wed Mar 30 13:45:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637119723 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637119723 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637119723 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648637119723 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648637121347 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637121348 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:45:21 2022 " "Processing started: Wed Mar 30 13:45:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637121348 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648637121348 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648637121348 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648637122298 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648637122324 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637122569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:45:22 2022 " "Processing ended: Wed Mar 30 13:45:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637122569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637122569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637122569 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648637122569 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648637122640 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648637124022 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:45:23 2022 " "Processing started: Wed Mar 30 13:45:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637124022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637124022 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637124023 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648637124056 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637124179 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637124181 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637124227 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637124228 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648637124442 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648637124443 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124444 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124444 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648637124576 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124577 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648637124577 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648637124587 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637124599 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637124599 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.811 " "Worst-case setup slack is -1.811" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.811 -75.542 CLOCK_50 " " -1.811 -75.542 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124600 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637124600 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124601 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637124601 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637124602 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637124603 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -126.150 CLOCK_50 " " -3.000 -126.150 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637124603 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637124603 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637124626 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648637124651 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648637125063 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125084 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637125087 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637125087 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.531 " "Worst-case setup slack is -1.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125088 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125088 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.531 -60.869 CLOCK_50 " " -1.531 -60.869 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125088 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125088 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125089 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125089 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125089 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125089 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637125090 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637125091 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -126.144 CLOCK_50 " " -3.000 -126.144 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125092 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637125115 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125244 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637125245 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637125245 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.421 " "Worst-case setup slack is -0.421" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.421 -13.573 CLOCK_50 " " -0.421 -13.573 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125246 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 CLOCK_50 " " 0.179 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125249 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637125250 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637125252 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -102.086 CLOCK_50 " " -3.000 -102.086 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637125253 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637125253 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637125570 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637125570 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "418 " "Peak virtual memory: 418 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637125608 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:45:25 2022 " "Processing ended: Wed Mar 30 13:45:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637125608 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637125608 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637125608 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637125608 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637127318 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637127319 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:45:27 2022 " "Processing started: Wed Mar 30 13:45:27 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637127319 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637127319 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637127320 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127653 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127680 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127707 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127735 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127762 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127787 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127812 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637127837 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637127875 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:45:27 2022 " "Processing ended: Wed Mar 30 13:45:27 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637127875 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637127875 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637127875 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637127875 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 189 s " "Quartus II Full Compilation was successful. 0 errors, 189 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637127950 ""} diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index f6b8a6c..d5c8cf9 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index f49b15e..da9b2fe 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(10).cnf.cdb b/db/spectrum.(10).cnf.cdb new file mode 100644 index 0000000..2e3bfdf Binary files /dev/null and b/db/spectrum.(10).cnf.cdb differ diff --git a/db/spectrum.(10).cnf.hdb b/db/spectrum.(10).cnf.hdb new file mode 100644 index 0000000..0ef3492 Binary files /dev/null and b/db/spectrum.(10).cnf.hdb differ diff --git a/db/spectrum.(11).cnf.cdb b/db/spectrum.(11).cnf.cdb new file mode 100644 index 0000000..7e17f99 Binary files /dev/null and b/db/spectrum.(11).cnf.cdb differ diff --git a/db/spectrum.(11).cnf.hdb b/db/spectrum.(11).cnf.hdb new file mode 100644 index 0000000..5c5c3a7 Binary files /dev/null and b/db/spectrum.(11).cnf.hdb differ diff --git a/db/spectrum.(12).cnf.cdb b/db/spectrum.(12).cnf.cdb new file mode 100644 index 0000000..1f984a7 Binary files /dev/null and b/db/spectrum.(12).cnf.cdb differ diff --git a/db/spectrum.(12).cnf.hdb b/db/spectrum.(12).cnf.hdb new file mode 100644 index 0000000..896eb4e Binary files /dev/null and b/db/spectrum.(12).cnf.hdb differ diff --git a/db/spectrum.(13).cnf.cdb b/db/spectrum.(13).cnf.cdb new file mode 100644 index 0000000..4ccc2d9 Binary files /dev/null and b/db/spectrum.(13).cnf.cdb differ diff --git a/db/spectrum.(13).cnf.hdb b/db/spectrum.(13).cnf.hdb new file mode 100644 index 0000000..d38adb7 Binary files /dev/null and b/db/spectrum.(13).cnf.hdb differ diff --git a/db/spectrum.(8).cnf.cdb b/db/spectrum.(8).cnf.cdb new file mode 100644 index 0000000..3c2e751 Binary files /dev/null and b/db/spectrum.(8).cnf.cdb differ diff --git a/db/spectrum.(8).cnf.hdb b/db/spectrum.(8).cnf.hdb new file mode 100644 index 0000000..6e477e5 Binary files /dev/null and b/db/spectrum.(8).cnf.hdb differ diff --git a/db/spectrum.(9).cnf.cdb b/db/spectrum.(9).cnf.cdb new file mode 100644 index 0000000..bfa03d5 Binary files /dev/null and b/db/spectrum.(9).cnf.cdb differ diff --git a/db/spectrum.(9).cnf.hdb b/db/spectrum.(9).cnf.hdb new file mode 100644 index 0000000..7fb3f79 Binary files /dev/null and b/db/spectrum.(9).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index 71e39ad..65c5773 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635142046 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:21 2022 " "Processing started: Wed Mar 30 13:12:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648635143022 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648635143049 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:23 2022 " "Processing ended: Wed Mar 30 13:12:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648635143323 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637238255 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:18 2022 " "Processing started: Wed Mar 30 13:47:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637238256 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648637238256 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648637239291 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648637239318 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:19 2022 " "Processing ended: Wed Mar 30 13:47:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637239598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648637239598 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index 42edf94..bee75cf 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index f597537..d2867ef 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cbx.xml b/db/spectrum.cbx.xml index 331b0f0..12dff67 100644 --- a/db/spectrum.cbx.xml +++ b/db/spectrum.cbx.xml @@ -1,6 +1,7 @@ + diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index 38e7f41..03c2ad8 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index ffc02ea..a8cf013 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index b5c9680..2af457f 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index bfa8deb..8b53df4 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 63cdcb7..bc6b577 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd index 2005c89..7fbf94b 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index dcb7668..71a027c 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635147928 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:27 2022 " "Processing started: Wed Mar 30 13:12:27 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148267 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148299 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148332 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148365 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148393 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148420 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148446 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148473 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "343 " "Peak virtual memory: 343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:28 2022 " "Processing ended: Wed Mar 30 13:12:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637244327 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing started: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637244328 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244673 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244704 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244734 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244765 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244794 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244820 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244846 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648637244872 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:24 2022 " "Processing ended: Wed Mar 30 13:47:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637244918 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index 75195a4..585bc84 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,48 +1,49 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648635134783 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648635134787 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134825 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134826 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134826 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648635134900 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648635134910 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648635135113 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 599 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 601 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 603 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 605 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648635135117 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648635135119 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648635135121 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648635135787 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648635135788 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648635135790 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648635135791 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648635135791 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648635135800 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 594 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648635135800 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648635136038 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648635136038 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648635136039 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648635136040 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648635136040 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648635136041 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648635136041 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648635136041 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648635136041 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648635136041 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648635136041 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648635136056 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635136063 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648635137043 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635137115 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648635137123 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648635137770 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635137770 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648635138018 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648635138667 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648635138667 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635139098 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648635139098 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648635139098 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648635139111 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648635139164 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648635139345 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648635139390 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648635139538 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635139840 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648635140193 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648635140197 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648635140197 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648635140253 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "595 " "Peak virtual memory: 595 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:20 2022 " "Processing ended: Wed Mar 30 13:12:20 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648635140493 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648637230636 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648637230642 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230686 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230687 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648637230687 ""} +{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2"} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3 " "Atom \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Quartus II" 0 -1 1648637230752 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3"} } { } 0 119042 "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" 0 0 "Fitter" 0 -1 1648637230752 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648637230771 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648637230784 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648637231004 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648637231004 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 609 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 611 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 613 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 615 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648637231009 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648637231009 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648637231010 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648637231012 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648637231699 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648637231700 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648637231702 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648637231702 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648637231703 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648637231712 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 604 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648637231712 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648637231960 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637231960 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648637231961 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637231962 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648637231962 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648637231963 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648637231963 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648637231963 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648637231963 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648637231963 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648637231963 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648637231978 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648637231978 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637231985 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648637233010 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637233086 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648637233095 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648637233849 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637233849 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648637234104 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648637234756 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648637234756 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637235213 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648637235213 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648637235213 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648637235226 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637235280 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637235460 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648637235507 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648637235657 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648637235962 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648637236322 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 26 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648637236325 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648637236325 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648637236389 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:16 2022 " "Processing ended: Wed Mar 30 13:47:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637236676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648637236676 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index a594bd4..a1ad3e1 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,9 +1,9 @@ |spectrum -CLOCK_50 => CLOCK_50.IN1 -LED[0] <= rom0:rom.q -LED[1] <= rom0:rom.q -LED[2] <= rom0:rom.q -LED[3] <= rom0:rom.q +CLOCK_50 => CLOCK_50.IN2 +LED[0] <= ram16:ram0.q_a +LED[1] <= ram16:ram0.q_a +LED[2] <= ram16:ram0.q_a +LED[3] <= ram16:ram0.q_a LED[4] <= rom0:rom.q LED[5] <= rom0:rom.q LED[6] <= rom0:rom.q @@ -380,3 +380,780 @@ sel[0] => result_node[0].IN0 sel[0] => _.IN0 +|spectrum|ram16:ram0 +address_a[0] => address_a[0].IN1 +address_a[1] => address_a[1].IN1 +address_a[2] => address_a[2].IN1 +address_a[3] => address_a[3].IN1 +address_a[4] => address_a[4].IN1 +address_a[5] => address_a[5].IN1 +address_a[6] => address_a[6].IN1 +address_a[7] => address_a[7].IN1 +address_a[8] => address_a[8].IN1 +address_a[9] => address_a[9].IN1 +address_a[10] => address_a[10].IN1 +address_a[11] => address_a[11].IN1 +address_a[12] => address_a[12].IN1 +address_a[13] => address_a[13].IN1 +address_b[0] => address_b[0].IN1 +address_b[1] => address_b[1].IN1 +address_b[2] => address_b[2].IN1 +address_b[3] => address_b[3].IN1 +address_b[4] => address_b[4].IN1 +address_b[5] => address_b[5].IN1 +address_b[6] => address_b[6].IN1 +address_b[7] => address_b[7].IN1 +address_b[8] => address_b[8].IN1 +address_b[9] => address_b[9].IN1 +address_b[10] => address_b[10].IN1 +address_b[11] => address_b[11].IN1 +address_b[12] => address_b[12].IN1 +address_b[13] => address_b[13].IN1 +clock => clock.IN1 +data_a[0] => data_a[0].IN1 +data_a[1] => data_a[1].IN1 +data_a[2] => data_a[2].IN1 +data_a[3] => data_a[3].IN1 +data_a[4] => data_a[4].IN1 +data_a[5] => data_a[5].IN1 +data_a[6] => data_a[6].IN1 +data_a[7] => data_a[7].IN1 +data_b[0] => data_b[0].IN1 +data_b[1] => data_b[1].IN1 +data_b[2] => data_b[2].IN1 +data_b[3] => data_b[3].IN1 +data_b[4] => data_b[4].IN1 +data_b[5] => data_b[5].IN1 +data_b[6] => data_b[6].IN1 +data_b[7] => data_b[7].IN1 +wren_a => wren_a.IN1 +wren_b => wren_b.IN1 +q_a[0] <= altsyncram:altsyncram_component.q_a +q_a[1] <= altsyncram:altsyncram_component.q_a +q_a[2] <= altsyncram:altsyncram_component.q_a +q_a[3] <= altsyncram:altsyncram_component.q_a +q_a[4] <= altsyncram:altsyncram_component.q_a +q_a[5] <= altsyncram:altsyncram_component.q_a +q_a[6] <= altsyncram:altsyncram_component.q_a +q_a[7] <= altsyncram:altsyncram_component.q_a +q_b[0] <= altsyncram:altsyncram_component.q_b +q_b[1] <= altsyncram:altsyncram_component.q_b +q_b[2] <= altsyncram:altsyncram_component.q_b +q_b[3] <= altsyncram:altsyncram_component.q_b +q_b[4] <= altsyncram:altsyncram_component.q_b +q_b[5] <= altsyncram:altsyncram_component.q_b +q_b[6] <= altsyncram:altsyncram_component.q_b +q_b[7] <= altsyncram:altsyncram_component.q_b + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component +wren_a => altsyncram_bui2:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => altsyncram_bui2:auto_generated.wren_b +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_bui2:auto_generated.data_a[0] +data_a[1] => altsyncram_bui2:auto_generated.data_a[1] +data_a[2] => altsyncram_bui2:auto_generated.data_a[2] +data_a[3] => altsyncram_bui2:auto_generated.data_a[3] +data_a[4] => altsyncram_bui2:auto_generated.data_a[4] +data_a[5] => altsyncram_bui2:auto_generated.data_a[5] +data_a[6] => altsyncram_bui2:auto_generated.data_a[6] +data_a[7] => altsyncram_bui2:auto_generated.data_a[7] +data_b[0] => altsyncram_bui2:auto_generated.data_b[0] +data_b[1] => altsyncram_bui2:auto_generated.data_b[1] +data_b[2] => altsyncram_bui2:auto_generated.data_b[2] +data_b[3] => altsyncram_bui2:auto_generated.data_b[3] +data_b[4] => altsyncram_bui2:auto_generated.data_b[4] +data_b[5] => altsyncram_bui2:auto_generated.data_b[5] +data_b[6] => altsyncram_bui2:auto_generated.data_b[6] +data_b[7] => altsyncram_bui2:auto_generated.data_b[7] +address_a[0] => altsyncram_bui2:auto_generated.address_a[0] +address_a[1] => altsyncram_bui2:auto_generated.address_a[1] +address_a[2] => altsyncram_bui2:auto_generated.address_a[2] +address_a[3] => altsyncram_bui2:auto_generated.address_a[3] +address_a[4] => altsyncram_bui2:auto_generated.address_a[4] +address_a[5] => altsyncram_bui2:auto_generated.address_a[5] +address_a[6] => altsyncram_bui2:auto_generated.address_a[6] +address_a[7] => altsyncram_bui2:auto_generated.address_a[7] +address_a[8] => altsyncram_bui2:auto_generated.address_a[8] +address_a[9] => altsyncram_bui2:auto_generated.address_a[9] +address_a[10] => altsyncram_bui2:auto_generated.address_a[10] +address_a[11] => altsyncram_bui2:auto_generated.address_a[11] +address_a[12] => altsyncram_bui2:auto_generated.address_a[12] +address_a[13] => altsyncram_bui2:auto_generated.address_a[13] +address_b[0] => altsyncram_bui2:auto_generated.address_b[0] +address_b[1] => altsyncram_bui2:auto_generated.address_b[1] +address_b[2] => altsyncram_bui2:auto_generated.address_b[2] +address_b[3] => altsyncram_bui2:auto_generated.address_b[3] +address_b[4] => altsyncram_bui2:auto_generated.address_b[4] +address_b[5] => altsyncram_bui2:auto_generated.address_b[5] +address_b[6] => altsyncram_bui2:auto_generated.address_b[6] +address_b[7] => altsyncram_bui2:auto_generated.address_b[7] +address_b[8] => altsyncram_bui2:auto_generated.address_b[8] +address_b[9] => altsyncram_bui2:auto_generated.address_b[9] +address_b[10] => altsyncram_bui2:auto_generated.address_b[10] +address_b[11] => altsyncram_bui2:auto_generated.address_b[11] +address_b[12] => altsyncram_bui2:auto_generated.address_b[12] +address_b[13] => altsyncram_bui2:auto_generated.address_b[13] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_bui2:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_bui2:auto_generated.q_a[0] +q_a[1] <= altsyncram_bui2:auto_generated.q_a[1] +q_a[2] <= altsyncram_bui2:auto_generated.q_a[2] +q_a[3] <= altsyncram_bui2:auto_generated.q_a[3] +q_a[4] <= altsyncram_bui2:auto_generated.q_a[4] +q_a[5] <= altsyncram_bui2:auto_generated.q_a[5] +q_a[6] <= altsyncram_bui2:auto_generated.q_a[6] +q_a[7] <= altsyncram_bui2:auto_generated.q_a[7] +q_b[0] <= altsyncram_bui2:auto_generated.q_b[0] +q_b[1] <= altsyncram_bui2:auto_generated.q_b[1] +q_b[2] <= altsyncram_bui2:auto_generated.q_b[2] +q_b[3] <= altsyncram_bui2:auto_generated.q_b[3] +q_b[4] <= altsyncram_bui2:auto_generated.q_b[4] +q_b[5] <= altsyncram_bui2:auto_generated.q_b[5] +q_b[6] <= altsyncram_bui2:auto_generated.q_b[6] +q_b[7] <= altsyncram_bui2:auto_generated.q_b[7] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[10] => ram_block1a0.PORTAADDR10 +address_a[10] => ram_block1a1.PORTAADDR10 +address_a[10] => ram_block1a2.PORTAADDR10 +address_a[10] => ram_block1a3.PORTAADDR10 +address_a[10] => ram_block1a4.PORTAADDR10 +address_a[10] => ram_block1a5.PORTAADDR10 +address_a[10] => ram_block1a6.PORTAADDR10 +address_a[10] => ram_block1a7.PORTAADDR10 +address_a[10] => ram_block1a8.PORTAADDR10 +address_a[10] => ram_block1a9.PORTAADDR10 +address_a[10] => ram_block1a10.PORTAADDR10 +address_a[10] => ram_block1a11.PORTAADDR10 +address_a[10] => ram_block1a12.PORTAADDR10 +address_a[10] => ram_block1a13.PORTAADDR10 +address_a[10] => ram_block1a14.PORTAADDR10 +address_a[10] => ram_block1a15.PORTAADDR10 +address_a[11] => ram_block1a0.PORTAADDR11 +address_a[11] => ram_block1a1.PORTAADDR11 +address_a[11] => ram_block1a2.PORTAADDR11 +address_a[11] => ram_block1a3.PORTAADDR11 +address_a[11] => ram_block1a4.PORTAADDR11 +address_a[11] => ram_block1a5.PORTAADDR11 +address_a[11] => ram_block1a6.PORTAADDR11 +address_a[11] => ram_block1a7.PORTAADDR11 +address_a[11] => ram_block1a8.PORTAADDR11 +address_a[11] => ram_block1a9.PORTAADDR11 +address_a[11] => ram_block1a10.PORTAADDR11 +address_a[11] => ram_block1a11.PORTAADDR11 +address_a[11] => ram_block1a12.PORTAADDR11 +address_a[11] => ram_block1a13.PORTAADDR11 +address_a[11] => ram_block1a14.PORTAADDR11 +address_a[11] => ram_block1a15.PORTAADDR11 +address_a[12] => ram_block1a0.PORTAADDR12 +address_a[12] => ram_block1a1.PORTAADDR12 +address_a[12] => ram_block1a2.PORTAADDR12 +address_a[12] => ram_block1a3.PORTAADDR12 +address_a[12] => ram_block1a4.PORTAADDR12 +address_a[12] => ram_block1a5.PORTAADDR12 +address_a[12] => ram_block1a6.PORTAADDR12 +address_a[12] => ram_block1a7.PORTAADDR12 +address_a[12] => ram_block1a8.PORTAADDR12 +address_a[12] => ram_block1a9.PORTAADDR12 +address_a[12] => ram_block1a10.PORTAADDR12 +address_a[12] => ram_block1a11.PORTAADDR12 +address_a[12] => ram_block1a12.PORTAADDR12 +address_a[12] => ram_block1a13.PORTAADDR12 +address_a[12] => ram_block1a14.PORTAADDR12 +address_a[12] => ram_block1a15.PORTAADDR12 +address_a[13] => address_reg_a[0].DATAIN +address_a[13] => decode_jsa:decode2.data[0] +address_a[13] => decode_c8a:rden_decode_a.data[0] +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +address_b[7] => ram_block1a2.PORTBADDR7 +address_b[7] => ram_block1a3.PORTBADDR7 +address_b[7] => ram_block1a4.PORTBADDR7 +address_b[7] => ram_block1a5.PORTBADDR7 +address_b[7] => ram_block1a6.PORTBADDR7 +address_b[7] => ram_block1a7.PORTBADDR7 +address_b[7] => ram_block1a8.PORTBADDR7 +address_b[7] => ram_block1a9.PORTBADDR7 +address_b[7] => ram_block1a10.PORTBADDR7 +address_b[7] => ram_block1a11.PORTBADDR7 +address_b[7] => ram_block1a12.PORTBADDR7 +address_b[7] => ram_block1a13.PORTBADDR7 +address_b[7] => ram_block1a14.PORTBADDR7 +address_b[7] => ram_block1a15.PORTBADDR7 +address_b[8] => ram_block1a0.PORTBADDR8 +address_b[8] => ram_block1a1.PORTBADDR8 +address_b[8] => ram_block1a2.PORTBADDR8 +address_b[8] => ram_block1a3.PORTBADDR8 +address_b[8] => ram_block1a4.PORTBADDR8 +address_b[8] => ram_block1a5.PORTBADDR8 +address_b[8] => ram_block1a6.PORTBADDR8 +address_b[8] => ram_block1a7.PORTBADDR8 +address_b[8] => ram_block1a8.PORTBADDR8 +address_b[8] => ram_block1a9.PORTBADDR8 +address_b[8] => ram_block1a10.PORTBADDR8 +address_b[8] => ram_block1a11.PORTBADDR8 +address_b[8] => ram_block1a12.PORTBADDR8 +address_b[8] => ram_block1a13.PORTBADDR8 +address_b[8] => ram_block1a14.PORTBADDR8 +address_b[8] => ram_block1a15.PORTBADDR8 +address_b[9] => ram_block1a0.PORTBADDR9 +address_b[9] => ram_block1a1.PORTBADDR9 +address_b[9] => ram_block1a2.PORTBADDR9 +address_b[9] => ram_block1a3.PORTBADDR9 +address_b[9] => ram_block1a4.PORTBADDR9 +address_b[9] => ram_block1a5.PORTBADDR9 +address_b[9] => ram_block1a6.PORTBADDR9 +address_b[9] => ram_block1a7.PORTBADDR9 +address_b[9] => ram_block1a8.PORTBADDR9 +address_b[9] => ram_block1a9.PORTBADDR9 +address_b[9] => ram_block1a10.PORTBADDR9 +address_b[9] => ram_block1a11.PORTBADDR9 +address_b[9] => ram_block1a12.PORTBADDR9 +address_b[9] => ram_block1a13.PORTBADDR9 +address_b[9] => ram_block1a14.PORTBADDR9 +address_b[9] => ram_block1a15.PORTBADDR9 +address_b[10] => ram_block1a0.PORTBADDR10 +address_b[10] => ram_block1a1.PORTBADDR10 +address_b[10] => ram_block1a2.PORTBADDR10 +address_b[10] => ram_block1a3.PORTBADDR10 +address_b[10] => ram_block1a4.PORTBADDR10 +address_b[10] => ram_block1a5.PORTBADDR10 +address_b[10] => ram_block1a6.PORTBADDR10 +address_b[10] => ram_block1a7.PORTBADDR10 +address_b[10] => ram_block1a8.PORTBADDR10 +address_b[10] => ram_block1a9.PORTBADDR10 +address_b[10] => ram_block1a10.PORTBADDR10 +address_b[10] => ram_block1a11.PORTBADDR10 +address_b[10] => ram_block1a12.PORTBADDR10 +address_b[10] => ram_block1a13.PORTBADDR10 +address_b[10] => ram_block1a14.PORTBADDR10 +address_b[10] => ram_block1a15.PORTBADDR10 +address_b[11] => ram_block1a0.PORTBADDR11 +address_b[11] => ram_block1a1.PORTBADDR11 +address_b[11] => ram_block1a2.PORTBADDR11 +address_b[11] => ram_block1a3.PORTBADDR11 +address_b[11] => ram_block1a4.PORTBADDR11 +address_b[11] => ram_block1a5.PORTBADDR11 +address_b[11] => ram_block1a6.PORTBADDR11 +address_b[11] => ram_block1a7.PORTBADDR11 +address_b[11] => ram_block1a8.PORTBADDR11 +address_b[11] => ram_block1a9.PORTBADDR11 +address_b[11] => ram_block1a10.PORTBADDR11 +address_b[11] => ram_block1a11.PORTBADDR11 +address_b[11] => ram_block1a12.PORTBADDR11 +address_b[11] => ram_block1a13.PORTBADDR11 +address_b[11] => ram_block1a14.PORTBADDR11 +address_b[11] => ram_block1a15.PORTBADDR11 +address_b[12] => ram_block1a0.PORTBADDR12 +address_b[12] => ram_block1a1.PORTBADDR12 +address_b[12] => ram_block1a2.PORTBADDR12 +address_b[12] => ram_block1a3.PORTBADDR12 +address_b[12] => ram_block1a4.PORTBADDR12 +address_b[12] => ram_block1a5.PORTBADDR12 +address_b[12] => ram_block1a6.PORTBADDR12 +address_b[12] => ram_block1a7.PORTBADDR12 +address_b[12] => ram_block1a8.PORTBADDR12 +address_b[12] => ram_block1a9.PORTBADDR12 +address_b[12] => ram_block1a10.PORTBADDR12 +address_b[12] => ram_block1a11.PORTBADDR12 +address_b[12] => ram_block1a12.PORTBADDR12 +address_b[12] => ram_block1a13.PORTBADDR12 +address_b[12] => ram_block1a14.PORTBADDR12 +address_b[12] => ram_block1a15.PORTBADDR12 +address_b[13] => address_reg_b[0].DATAIN +address_b[13] => decode_jsa:decode3.data[0] +address_b[13] => decode_c8a:rden_decode_b.data[0] +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a0.CLK1 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a1.CLK1 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a2.CLK1 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a3.CLK1 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a4.CLK1 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a5.CLK1 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a6.CLK1 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a7.CLK1 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a8.CLK1 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a9.CLK1 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a10.CLK1 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a11.CLK1 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a12.CLK1 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a13.CLK1 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a14.CLK1 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a15.CLK1 +clock0 => address_reg_a[0].CLK +clock0 => address_reg_b[0].CLK +clock0 => out_address_reg_a[0].CLK +clock0 => out_address_reg_b[0].CLK +data_a[0] => ram_block1a0.PORTADATAIN +data_a[0] => ram_block1a8.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[1] => ram_block1a9.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[2] => ram_block1a10.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[3] => ram_block1a11.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[4] => ram_block1a12.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[5] => ram_block1a13.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[6] => ram_block1a14.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[7] => ram_block1a15.PORTADATAIN +data_b[0] => ram_block1a0.PORTBDATAIN +data_b[0] => ram_block1a8.PORTBDATAIN +data_b[1] => ram_block1a1.PORTBDATAIN +data_b[1] => ram_block1a9.PORTBDATAIN +data_b[2] => ram_block1a2.PORTBDATAIN +data_b[2] => ram_block1a10.PORTBDATAIN +data_b[3] => ram_block1a3.PORTBDATAIN +data_b[3] => ram_block1a11.PORTBDATAIN +data_b[4] => ram_block1a4.PORTBDATAIN +data_b[4] => ram_block1a12.PORTBDATAIN +data_b[5] => ram_block1a5.PORTBDATAIN +data_b[5] => ram_block1a13.PORTBDATAIN +data_b[6] => ram_block1a6.PORTBDATAIN +data_b[6] => ram_block1a14.PORTBDATAIN +data_b[7] => ram_block1a7.PORTBDATAIN +data_b[7] => ram_block1a15.PORTBDATAIN +q_a[0] <= mux_3nb:mux4.result[0] +q_a[1] <= mux_3nb:mux4.result[1] +q_a[2] <= mux_3nb:mux4.result[2] +q_a[3] <= mux_3nb:mux4.result[3] +q_a[4] <= mux_3nb:mux4.result[4] +q_a[5] <= mux_3nb:mux4.result[5] +q_a[6] <= mux_3nb:mux4.result[6] +q_a[7] <= mux_3nb:mux4.result[7] +q_b[0] <= mux_3nb:mux5.result[0] +q_b[1] <= mux_3nb:mux5.result[1] +q_b[2] <= mux_3nb:mux5.result[2] +q_b[3] <= mux_3nb:mux5.result[3] +q_b[4] <= mux_3nb:mux5.result[4] +q_b[5] <= mux_3nb:mux5.result[5] +q_b[6] <= mux_3nb:mux5.result[6] +q_b[7] <= mux_3nb:mux5.result[7] +wren_a => decode_jsa:decode2.enable +wren_b => decode_jsa:decode3.enable + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2 +data[0] => eq_node[1].IN0 +data[0] => eq_node[0].IN0 +enable => eq_node[1].IN1 +enable => eq_node[0].IN1 +eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode3 +data[0] => eq_node[1].IN0 +data[0] => eq_node[0].IN0 +enable => eq_node[1].IN1 +enable => eq_node[0].IN1 +eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_a +data[0] => eq_node[1].IN0 +data[0] => eq_node[0].IN0 +eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_b +data[0] => eq_node[1].IN0 +data[0] => eq_node[0].IN0 +eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4 +data[0] => result_node[0].IN1 +data[1] => result_node[1].IN1 +data[2] => result_node[2].IN1 +data[3] => result_node[3].IN1 +data[4] => result_node[4].IN1 +data[5] => result_node[5].IN1 +data[6] => result_node[6].IN1 +data[7] => result_node[7].IN1 +data[8] => result_node[0].IN1 +data[9] => result_node[1].IN1 +data[10] => result_node[2].IN1 +data[11] => result_node[3].IN1 +data[12] => result_node[4].IN1 +data[13] => result_node[5].IN1 +data[14] => result_node[6].IN1 +data[15] => result_node[7].IN1 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => result_node[7].IN0 +sel[0] => _.IN0 +sel[0] => result_node[6].IN0 +sel[0] => _.IN0 +sel[0] => result_node[5].IN0 +sel[0] => _.IN0 +sel[0] => result_node[4].IN0 +sel[0] => _.IN0 +sel[0] => result_node[3].IN0 +sel[0] => _.IN0 +sel[0] => result_node[2].IN0 +sel[0] => _.IN0 +sel[0] => result_node[1].IN0 +sel[0] => _.IN0 +sel[0] => result_node[0].IN0 +sel[0] => _.IN0 + + +|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5 +data[0] => result_node[0].IN1 +data[1] => result_node[1].IN1 +data[2] => result_node[2].IN1 +data[3] => result_node[3].IN1 +data[4] => result_node[4].IN1 +data[5] => result_node[5].IN1 +data[6] => result_node[6].IN1 +data[7] => result_node[7].IN1 +data[8] => result_node[0].IN1 +data[9] => result_node[1].IN1 +data[10] => result_node[2].IN1 +data[11] => result_node[3].IN1 +data[12] => result_node[4].IN1 +data[13] => result_node[5].IN1 +data[14] => result_node[6].IN1 +data[15] => result_node[7].IN1 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => result_node[7].IN0 +sel[0] => _.IN0 +sel[0] => result_node[6].IN0 +sel[0] => _.IN0 +sel[0] => result_node[5].IN0 +sel[0] => _.IN0 +sel[0] => result_node[4].IN0 +sel[0] => _.IN0 +sel[0] => result_node[3].IN0 +sel[0] => _.IN0 +sel[0] => result_node[2].IN0 +sel[0] => _.IN0 +sel[0] => result_node[1].IN0 +sel[0] => _.IN0 +sel[0] => result_node[0].IN0 +sel[0] => _.IN0 + + diff --git a/db/spectrum.hif b/db/spectrum.hif index a5d2bd5..36e2c50 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index 294d6a6..fe13399 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index 4e15f36..7dd5a73 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -16,6 +16,134 @@ Output only Bidir +ram0|altsyncram_component|auto_generated|mux5 +17 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated|mux4 +17 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated|rden_decode_b +1 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated|rden_decode_a +1 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated|decode3 +2 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated|decode2 +2 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0|altsyncram_component|auto_generated +47 +0 +0 +0 +16 +0 +0 +0 +0 +0 +0 +0 +0 + + +ram0 +47 +21 +0 +21 +16 +21 +21 +21 +0 +0 +0 +0 +0 + + rom|altsyncram_component|auto_generated|mux2 17 0 diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 60aa6e4..06dffbc 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index f5b698d..5a0e28b 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1,6 +1,126 @@ +--------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +--------------------------------------------------------------------------------+ +Hierarchy : ram0|altsyncram_component|auto_generated|mux5 +Input : 17 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 8 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated|mux4 +Input : 17 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 8 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated|rden_decode_b +Input : 1 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated|rden_decode_a +Input : 1 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated|decode3 +Input : 2 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated|decode2 +Input : 2 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0|altsyncram_component|auto_generated +Input : 47 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 16 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : ram0 +Input : 47 +Constant Input : 21 +Unused Input : 0 +Floating Input : 21 +Output : 16 +Constant Output : 21 +Unused Output : 21 +Floating Output : 21 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + Hierarchy : rom|altsyncram_component|auto_generated|mux2 Input : 17 Constant Input : 0 diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index 2ca9d2f..5ea3969 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index afe5518..f6fcff8 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index 014c8c0..58e18ea 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index 9ceab4e..de51714 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index 6061c3b..5937733 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,23 +1,37 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635132020 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:11 2022 " "Processing started: Wed Mar 30 13:12:11 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635132212 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648635132338 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(18) " "Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(20) " "Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132350 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132402 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648635132403 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132452 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132495 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132537 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648635133078 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648635133316 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635133316 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648635133366 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648635133366 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "392 " "Peak virtual memory: 392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:13 2022 " "Processing ended: Wed Mar 30 13:12:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637227599 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:07 2022 " "Processing started: Wed Mar 30 13:47:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637227600 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637227779 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227848 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227850 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637227851 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637227851 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648637227909 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RamWE spectrum.v(19) " "Verilog HDL or VHDL warning at spectrum.v(19): object \"RamWE\" assigned a value but never read" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1648637227910 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(43) " "Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227911 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(46) " "Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 46 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227912 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 spectrum.v(47) " "Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648637227912 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227925 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227985 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637227987 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637227987 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228040 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228040 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228040 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228086 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228086 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228087 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228131 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228131 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228131 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.v" "ram0" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228134 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228138 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228139 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648637228139 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bui2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bui2 " "Found entity 1: altsyncram_bui2" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228191 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228191 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bui2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated " "Elaborating entity \"altsyncram_bui2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228191 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648637228237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648637228237 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_bui2.tdf" "decode2" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648637228237 ""} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 216 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a5\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 256 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a6\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 296 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a7\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 336 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 376 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 416 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 456 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 496 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 536 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 576 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 616 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15 " "Synthesized away node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_bui2:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_bui2.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_bui2.tdf" 656 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram16.v" "" { Text "/home/benny/work/fpga/projects/ram16.v" 97 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 38 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 42 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 64 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 86 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 108 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 218 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 240 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 262 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11 " "Synthesized away node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 284 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637228301 "|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1648637228301 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1648637228301 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648637228703 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648637228839 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648637228951 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648637229075 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648637229075 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_LCELLS" "50 " "Implemented 50 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648637229123 ""} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Implemented 12 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648637229123 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648637229123 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:09 2022 " "Processing ended: Wed Mar 30 13:47:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637229133 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index f2733e7..1e2c1ce 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index 05be201..222a9f1 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index f81bc6e..84b7971 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index 690c2ed..e51ca48 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index d836860..bdfc6af 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index 9e044fd..edee550 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index 965ec73..22990b4 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index ba4e5ec..a511ac1 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index 2cbcdfd..85dc783 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index d96709b..5029d44 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index 79a4646..bacae97 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index 7625903..75e1bec 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,42 +1,42 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635144709 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:24 2022 " "Processing started: Wed Mar 30 13:12:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635144711 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648635144738 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635144851 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144852 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648635145098 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648635145098 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648635145226 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648635145236 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145248 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145248 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.788 " "Worst-case setup slack is -1.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.788 -88.557 CLOCK_50 " " -1.788 -88.557 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.260 " "Worst-case hold slack is 0.260" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.260 0.000 CLOCK_50 " " 0.260 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.836 CLOCK_50 " " -3.000 -110.836 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145268 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648635145291 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648635145672 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145692 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145695 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145695 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.527 " "Worst-case setup slack is -1.527" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.527 -72.611 CLOCK_50 " " -1.527 -72.611 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.255 0.000 CLOCK_50 " " 0.255 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145699 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145700 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.824 CLOCK_50 " " -3.000 -110.824 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145717 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145841 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145842 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145842 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.529 " "Worst-case setup slack is -0.529" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.529 -18.538 CLOCK_50 " " -0.529 -18.538 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.123 " "Worst-case hold slack is 0.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.123 0.000 CLOCK_50 " " 0.123 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145847 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145848 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -93.684 CLOCK_50 " " -3.000 -93.684 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146144 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146145 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "407 " "Peak virtual memory: 407 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:26 2022 " "Processing ended: Wed Mar 30 13:12:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648637241068 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:47:20 2022 " "Processing started: Wed Mar 30 13:47:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648637241069 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648637241070 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648637241098 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648637241220 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241222 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648637241268 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648637241477 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648637241477 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241478 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648637241608 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241609 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648637241610 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648637241625 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637241637 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637241637 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.812 " "Worst-case setup slack is -1.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.812 -85.179 CLOCK_50 " " -1.812 -85.179 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241638 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241639 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637241640 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.480 CLOCK_50 " " -3.000 -119.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637241641 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637241663 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648637241687 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648637242078 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242100 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242103 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242103 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.531 " "Worst-case setup slack is -1.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.531 -69.352 CLOCK_50 " " -1.531 -69.352 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242104 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242106 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242107 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242108 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -119.478 CLOCK_50 " " -3.000 -119.478 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242109 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648637242132 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242265 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648637242266 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648637242266 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.444 " "Worst-case setup slack is -0.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.444 -17.149 CLOCK_50 " " -0.444 -17.149 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242268 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242270 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242272 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648637242273 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.404 CLOCK_50 " " -3.000 -99.404 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648637242275 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648637242585 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "419 " "Peak virtual memory: 419 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:47:22 2022 " "Processing ended: Wed Mar 30 13:47:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648637242628 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index b56815f..a86674c 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 4624648..a0003af 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index f14c9a9..6fd3789 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index 2229f97..6b2c006 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index b3bdc65..83447af 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index 9078051..9469000 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt index 43c0e8e..d46f83c 100644 --- a/greybox_tmp/cbx_args.txt +++ b/greybox_tmp/cbx_args.txt @@ -1,16 +1,37 @@ -ADDRESS_ACLR_A=NONE +ADDRESS_REG_B=CLOCK0 CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_INPUT_B=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS -INIT_FILE=./rom/gw03.hex +CLOCK_ENABLE_OUTPUT_B=BYPASS +INDATA_REG_B=CLOCK0 +INIT_FILE=./led_patterns.mif INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altsyncram NUMWORDS_A=16384 -OPERATION_MODE=ROM +NUMWORDS_B=16384 +OPERATION_MODE=BIDIR_DUAL_PORT OUTDATA_ACLR_A=NONE +OUTDATA_ACLR_B=NONE OUTDATA_REG_A=CLOCK0 +OUTDATA_REG_B=CLOCK0 +POWER_UP_UNINITIALIZED=FALSE +READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE +READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ +READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ WIDTHAD_A=14 +WIDTHAD_B=14 WIDTH_A=8 +WIDTH_B=8 WIDTH_BYTEENA_A=1 +WIDTH_BYTEENA_B=1 +WRCONTROL_WRADDRESS_REG_B=CLOCK0 DEVICE_FAMILY="Cyclone IV E" address_a +address_b clock0 +data_a +data_b +wren_a +wren_b q_a +q_b diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index 0895966..7f0da6d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 0c493b6..d606c40 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 1f8f2be..6ff57ac 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index 1426ce6..a8ef191 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index 79c3fa4..bdb5e6b 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index fafb254..1aad683 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index b9156de..7b33790 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index bd583cd..da6eadb 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index de9ae64..120e855 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index ee77b94..7eb234d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index df09700..41df0cd 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Wed Mar 30 13:12:23 2022 +Wed Mar 30 13:47:19 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Mar 30 13:12:23 2022 ; +; Assembler Status ; Successful - Wed Mar 30 13:47:19 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x00315633 ; -; Checksum ; 0x00315633 ; +; JTAG usercode ; 0x0021F0FE ; +; Checksum ; 0x0021F0FE ; +----------------+-----------------------+ @@ -173,14 +173,14 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:12:21 2022 + Info: Processing started: Wed Mar 30 13:47:18 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 385 megabytes - Info: Processing ended: Wed Mar 30 13:12:23 2022 - Info: Elapsed time: 00:00:02 + Info: Peak virtual memory: 375 megabytes + Info: Processing ended: Wed Mar 30 13:47:19 2022 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index cdf40b2..084eaca 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Wed Mar 30 13:12:28 2022 +Wed Mar 30 13:47:24 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index 63ed9b7..b9367c4 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Wed Mar 30 13:12:28 2022 +Wed Mar 30 13:47:24 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:12:28 2022 ; +; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:47:24 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:12:27 2022 + Info: Processing started: Wed Mar 30 13:47:24 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool @@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 343 megabytes - Info: Processing ended: Wed Mar 30 13:12:28 2022 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 347 megabytes + Info: Processing ended: Wed Mar 30 13:47:24 2022 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index d951405..994384f 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Wed Mar 30 13:12:20 2022 +Wed Mar 30 13:47:16 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -30,22 +30,21 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 22. Global & Other Fast Signals 23. Non-Global High Fan-Out Signals 24. Fitter RAM Summary - 25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM - 26. Routing Usage Summary - 27. LAB Logic Elements - 28. LAB-wide Signals - 29. LAB Signals Sourced - 30. LAB Signals Sourced Out - 31. LAB Distinct Inputs - 32. I/O Rules Summary - 33. I/O Rules Details - 34. I/O Rules Matrix - 35. Fitter Device Options - 36. Operating Settings and Conditions - 37. Estimated Delay Added for Hold Timing Summary - 38. Estimated Delay Added for Hold Timing Details - 39. Fitter Messages - 40. Fitter Suppressed Messages + 25. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM + 26. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM + 27. Routing Usage Summary + 28. LAB Logic Elements + 29. LAB-wide Signals + 30. LAB Signals Sourced + 31. LAB Signals Sourced Out + 32. LAB Distinct Inputs + 33. I/O Rules Summary + 34. I/O Rules Details + 35. I/O Rules Matrix + 36. Fitter Device Options + 37. Operating Settings and Conditions + 38. Fitter Messages + 39. Fitter Suppressed Messages @@ -71,20 +70,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Wed Mar 30 13:12:20 2022 ; +; Fitter Status ; Successful - Wed Mar 30 13:47:16 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 55 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 52 / 22,320 ( < 1 % ) ; +; Total logic elements ; 50 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 48 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; ; Total registers ; 38 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 131,072 / 608,256 ( 22 % ) ; +; Total memory bits ; 98,304 / 608,256 ( 16 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -2376,14 +2375,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 136 ) -From Design Partitions [A] : 0.00 % ( 0 / 136 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 136 ) +Total [A + B] : 0.00 % ( 0 / 127 ) +From Design Partitions [A] : 0.00 % ( 0 / 127 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 127 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 136 ) -From Design Partitions [A] : 0.00 % ( 0 / 136 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 136 ) +Total [A + B] : 0.00 % ( 0 / 127 ) +From Design Partitions [A] : 0.00 % ( 0 / 127 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 127 ) Type : Total [A + B] : @@ -2434,7 +2433,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 126 ) +Preservation Achieved : 0.00 % ( 0 / 117 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -2461,35 +2460,35 @@ The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spe +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 55 / 22,320 ( < 1 % ) ; -; -- Combinational with no register ; 17 ; -; -- Register only ; 3 ; -; -- Combinational with a register ; 35 ; +; Total logic elements ; 50 / 22,320 ( < 1 % ) ; +; -- Combinational with no register ; 12 ; +; -- Register only ; 2 ; +; -- Combinational with a register ; 36 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 10 ; -; -- <=2 input functions ; 34 ; -; -- Register only ; 3 ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 35 ; +; -- Register only ; 2 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 20 ; +; -- normal mode ; 16 ; ; -- arithmetic mode ; 32 ; ; ; ; ; Total registers* ; 38 / 23,018 ( < 1 % ) ; ; -- Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; ; -- I/O registers ; 0 / 698 ( 0 % ) ; ; ; ; -; Total LABs: partially or completely used ; 12 / 1,395 ( < 1 % ) ; +; Total LABs: partially or completely used ; 9 / 1,395 ( < 1 % ) ; ; Virtual pins ; 0 ; ; I/O pins ; 9 / 154 ( 6 % ) ; ; -- Clock pins ; 1 / 7 ( 14 % ) ; ; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; ; ; ; ; Global signals ; 1 ; -; M9Ks ; 16 / 66 ( 24 % ) ; -; Total block memory bits ; 131,072 / 608,256 ( 22 % ) ; -; Total block memory implementation bits ; 147,456 / 608,256 ( 24 % ) ; +; M9Ks ; 12 / 66 ( 18 % ) ; +; Total block memory bits ; 98,304 / 608,256 ( 16 % ) ; +; Total block memory implementation bits ; 110,592 / 608,256 ( 18 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; PLLs ; 0 / 4 ( 0 % ) ; ; Global clocks ; 1 / 20 ( 5 % ) ; @@ -2498,11 +2497,11 @@ The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spe ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Peak interconnect usage (total/H/V) ; 1% / 1% / 1% ; ; Maximum fan-out ; 54 ; -; Highest non-global fan-out ; 18 ; -; Total fan-out ; 482 ; -; Average fan-out ; 3.49 ; +; Highest non-global fan-out ; 48 ; +; Total fan-out ; 409 ; +; Average fan-out ; 3.17 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -2520,19 +2519,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 55 / 22320 ( < 1 % ) +Top : 50 / 22320 ( < 1 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 17 +Top : 12 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 3 +Top : 2 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 35 +Top : 36 hard_block:auto_generated_inst : 0 Statistic : @@ -2544,19 +2543,19 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 8 +Top : 7 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 10 +Top : 6 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 34 +Top : 35 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 3 +Top : 2 hard_block:auto_generated_inst : 0 Statistic : @@ -2568,7 +2567,7 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 20 +Top : 16 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode @@ -2596,7 +2595,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 12 / 1395 ( < 1 % ) +Top : 9 / 1395 ( < 1 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -2616,15 +2615,15 @@ Top : 0 / 132 ( 0 % ) hard_block:auto_generated_inst : 0 / 132 ( 0 % ) Statistic : Total memory bits -Top : 131072 +Top : 98304 hard_block:auto_generated_inst : 0 Statistic : Total RAM block bits -Top : 147456 +Top : 110592 hard_block:auto_generated_inst : 0 Statistic : M9K -Top : 16 / 66 ( 24 % ) +Top : 12 / 66 ( 18 % ) hard_block:auto_generated_inst : 0 / 66 ( 0 % ) Statistic : Clock control block @@ -2664,11 +2663,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 477 +Top : 464 hard_block:auto_generated_inst : 5 Statistic : -- Registered Connections -Top : 312 +Top : 258 hard_block:auto_generated_inst : 0 Statistic : @@ -6227,75 +6226,126 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 55 (45) +Logic Cells : 50 (44) Dedicated Logic Registers : 38 (36) I/O Registers : 0 (0) -Memory Bits : 131072 -M9Ks : 16 +Memory Bits : 98304 +M9Ks : 12 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 9 Virtual Pins : 0 -LUT-Only LCs : 17 (9) -Register-Only LCs : 3 (1) -LUT/Register LCs : 35 (35) +LUT-Only LCs : 12 (8) +Register-Only LCs : 2 (0) +LUT/Register LCs : 36 (36) Full Hierarchy Name : |spectrum Library Name : work -Compilation Hierarchy Node : |rom0:rom| -Logic Cells : 10 (0) -Dedicated Logic Registers : 2 (0) +Compilation Hierarchy Node : |ram16:ram0| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) -Memory Bits : 131072 -M9Ks : 16 +Memory Bits : 32768 +M9Ks : 4 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 8 (0) +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram16:ram0 +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 32768 +M9Ks : 4 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_bui2:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 32768 +M9Ks : 4 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated +Library Name : work + +Compilation Hierarchy Node : |rom0:rom| +Logic Cells : 6 (0) +Dedicated Logic Registers : 2 (0) +I/O Registers : 0 (0) +Memory Bits : 65536 +M9Ks : 8 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 4 (0) Register-Only LCs : 2 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 10 (0) +Logic Cells : 6 (0) Dedicated Logic Registers : 2 (0) I/O Registers : 0 (0) -Memory Bits : 131072 -M9Ks : 16 +Memory Bits : 65536 +M9Ks : 8 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 8 (0) +LUT-Only LCs : 4 (0) Register-Only LCs : 2 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| -Logic Cells : 10 (2) +Logic Cells : 6 (2) Dedicated Logic Registers : 2 (2) I/O Registers : 0 (0) -Memory Bits : 131072 -M9Ks : 16 +Memory Bits : 65536 +M9Ks : 8 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 8 (0) +LUT-Only LCs : 4 (0) Register-Only LCs : 2 (2) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated Library Name : work Compilation Hierarchy Node : |mux_3nb:mux2| -Logic Cells : 8 (8) +Logic Cells : 4 (4) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -6305,7 +6355,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 8 (8) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 @@ -6406,9 +6456,18 @@ Setting : +--------------------------------------------------------------------------------+ ; Control Signals ; +--------------------------------------------------------------------------------+ +Name : A[13] +Location : FF_X29_Y14_N25 +Fan-Out : 14 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 54 +Fan-Out : 50 Usage : Clock Global : yes Global Resource Used : Global Clock @@ -6416,17 +6475,8 @@ Global Line Name : GCLK18 Enable Signal Source Name : -- Name : Equal0~6 -Location : LCCOMB_X29_Y18_N26 -Fan-Out : 13 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : address[13] -Location : FF_X29_Y18_N25 -Fan-Out : 18 +Location : LCCOMB_X29_Y14_N30 +Fan-Out : 14 Usage : Clock enable Global : no Global Resource Used : -- @@ -6441,8 +6491,8 @@ Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 54 -Fan-Out Using Intentional Clock Skew : 3 +Fan-Out : 50 +Fan-Out Using Intentional Clock Skew : 16 Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- @@ -6455,27 +6505,26 @@ Enable Signal Source Name : -- +-------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +-------------------------------------------------------------------------------------------------------+---------+ -; address[0] ; 18 ; -; address[13] ; 18 ; -; address[12] ; 17 ; -; address[11] ; 17 ; -; address[10] ; 17 ; -; address[9] ; 17 ; -; address[8] ; 17 ; -; address[7] ; 17 ; -; address[6] ; 17 ; -; address[5] ; 17 ; -; address[4] ; 17 ; -; address[3] ; 17 ; -; address[2] ; 17 ; -; address[1] ; 17 ; -; Equal0~6 ; 13 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; 8 ; +; ~GND ; 48 ; +; A[0] ; 18 ; +; A[2] ; 17 ; +; A[1] ; 17 ; +; Equal0~6 ; 14 ; +; A[13] ; 14 ; +; A[12] ; 13 ; +; A[11] ; 13 ; +; A[10] ; 13 ; +; A[9] ; 13 ; +; A[8] ; 13 ; +; A[7] ; 13 ; +; A[6] ; 13 ; +; A[5] ; 13 ; +; A[4] ; 13 ; +; A[3] ; 13 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; 4 ; ; counter[0] ; 3 ; -; counter[21] ; 3 ; -; counter[20] ; 3 ; -; Equal0~5 ; 2 ; -; Equal0~4 ; 2 ; +; counter[21] ; 2 ; +; counter[20] ; 2 ; ; counter[19] ; 2 ; ; counter[18] ; 2 ; ; counter[17] ; 2 ; @@ -6496,21 +6545,18 @@ Enable Signal Source Name : -- ; counter[2] ; 2 ; ; counter[1] ; 2 ; ; counter[0]~63 ; 1 ; -; address[0]~39 ; 1 ; -; Equal0~7 ; 1 ; +; A[0]~39 ; 1 ; +; Equal0~5 ; 1 ; +; Equal0~4 ; 1 ; ; Equal0~3 ; 1 ; ; Equal0~2 ; 1 ; ; Equal0~1 ; 1 ; ; Equal0~0 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[7]~7 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[6]~6 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[5]~5 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[4]~4 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[3]~3 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[2]~2 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[1]~1 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[0]~0 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[7]~3 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[6]~2 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[5]~1 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[4]~0 ; 1 ; ; counter[21]~61 ; 1 ; ; counter[20]~60 ; 1 ; ; counter[20]~59 ; 1 ; @@ -6552,31 +6598,31 @@ Enable Signal Source Name : -- ; counter[2]~23 ; 1 ; ; counter[1]~22 ; 1 ; ; counter[1]~21 ; 1 ; -; address[13]~37 ; 1 ; -; address[12]~36 ; 1 ; -; address[12]~35 ; 1 ; -; address[11]~34 ; 1 ; -; address[11]~33 ; 1 ; -; address[10]~32 ; 1 ; -; address[10]~31 ; 1 ; -; address[9]~30 ; 1 ; -; address[9]~29 ; 1 ; -; address[8]~28 ; 1 ; -; address[8]~27 ; 1 ; -; address[7]~26 ; 1 ; -; address[7]~25 ; 1 ; -; address[6]~24 ; 1 ; -; address[6]~23 ; 1 ; -; address[5]~22 ; 1 ; -; address[5]~21 ; 1 ; -; address[4]~20 ; 1 ; -; address[4]~19 ; 1 ; -; address[3]~18 ; 1 ; -; address[3]~17 ; 1 ; -; address[2]~16 ; 1 ; -; address[2]~15 ; 1 ; -; address[1]~14 ; 1 ; -; address[1]~13 ; 1 ; +; A[13]~37 ; 1 ; +; A[12]~36 ; 1 ; +; A[12]~35 ; 1 ; +; A[11]~34 ; 1 ; +; A[11]~33 ; 1 ; +; A[10]~32 ; 1 ; +; A[10]~31 ; 1 ; +; A[9]~30 ; 1 ; +; A[9]~29 ; 1 ; +; A[8]~28 ; 1 ; +; A[8]~27 ; 1 ; +; A[7]~26 ; 1 ; +; A[7]~25 ; 1 ; +; A[6]~24 ; 1 ; +; A[6]~23 ; 1 ; +; A[5]~22 ; 1 ; +; A[5]~21 ; 1 ; +; A[4]~20 ; 1 ; +; A[4]~19 ; 1 ; +; A[3]~18 ; 1 ; +; A[3]~17 ; 1 ; +; A[2]~16 ; 1 ; +; A[2]~15 ; 1 ; +; A[1]~14 ; 1 ; +; A[1]~13 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 ; 1 ; @@ -6585,20 +6631,42 @@ Enable Signal Source Name : -- ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 ; 1 ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 ; 1 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 ; 1 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 ; 1 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 ; 1 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 ; 1 ; +-------------------------------------------------------------------------------------------------------+---------+ +--------------------------------------------------------------------------------+ ; Fitter RAM Summary ; +--------------------------------------------------------------------------------+ +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : True Dual Port +Clock Mode : Dual Clocks +Port A Depth : 16384 +Port A Width : 8 +Port B Depth : 16384 +Port B Width : 8 +Port A Input Registers : yes +Port A Output Registers : yes +Port B Input Registers : yes +Port B Output Registers : yes +Size : 131072 +Implementation Port A Depth : 8192 +Implementation Port A Width : 4 +Implementation Port B Depth : 8192 +Implementation Port B Width : 4 +Implementation Bits : 32768 +M9Ks : 4 +MIF : led_patterns.mif +Location : M9K_X33_Y12_N0, M9K_X33_Y11_N0, M9K_X33_Y13_N0, M9K_X33_Y14_N0 +Mixed Width RDW Mode : Don't care +Port A RDW Mode : Old data +Port B RDW Mode : Old data +Fits in MLABs : No - Unknown + Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Type : AUTO Mode : ROM @@ -6613,13 +6681,13 @@ Port B Input Registers : -- Port B Output Registers : -- Size : 131072 Implementation Port A Depth : 16384 -Implementation Port A Width : 8 +Implementation Port A Width : 4 Implementation Port B Depth : -- Implementation Port B Width : -- -Implementation Bits : 131072 -M9Ks : 16 +Implementation Bits : 65536 +M9Ks : 8 MIF : ./rom/gw03.hex -Location : M9K_X33_Y13_N0, M9K_X33_Y14_N0, M9K_X22_Y16_N0, M9K_X22_Y19_N0, M9K_X33_Y15_N0, M9K_X33_Y12_N0, M9K_X33_Y17_N0, M9K_X33_Y18_N0, M9K_X22_Y17_N0, M9K_X22_Y18_N0, M9K_X22_Y15_N0, M9K_X22_Y13_N0, M9K_X33_Y16_N0, M9K_X33_Y19_N0, M9K_X22_Y12_N0, M9K_X22_Y14_N0 +Location : M9K_X22_Y13_N0, M9K_X22_Y12_N0, M9K_X22_Y14_N0, M9K_X22_Y11_N0, M9K_X33_Y15_N0, M9K_X22_Y15_N0, M9K_X22_Y10_N0, M9K_X33_Y10_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -6629,2060 +6697,4116 @@ Fits in MLABs : No - Unknown Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(00000001) (1) (1) (01) ;(00000010) (2) (2) (02) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00000100) (4) (4) (04) ;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ; +;8;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;24;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;32;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;40;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;48;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;56;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;64;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;72;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;80;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;88;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;96;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15384;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15392;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15400;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15416;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15456;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15488;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15496;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15512;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15520;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15528;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15544;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15552;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15560;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15632;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15688;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15752;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15768;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15784;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15792;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15864;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15888;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15904;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15920;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15936;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15944;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15960;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15968;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15984;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15992;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16000;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16008;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16024;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16032;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16040;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16048;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16056;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16064;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16080;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16112;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16128;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16144;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16192;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; + + RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; +----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11110011) (363) (243) (F3) ;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11000011) (303) (195) (C3) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ; -;8;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(01000011) (103) (67) (43) ; -;16;(11000011) (303) (195) (C3) ;(11110010) (362) (242) (F2) ;(00010101) (25) (21) (15) ;(10101111) (257) (175) (AF) ;(11000011) (303) (195) (C3) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(00100000) (40) (32) (20) ; -;24;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(01111101) (175) (125) (7D) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; -;32;(11001101) (315) (205) (CD) ;(01110100) (164) (116) (74) ;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(11110111) (367) (247) (F7) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; -;40;(11000011) (303) (195) (C3) ;(01011011) (133) (91) (5B) ;(00110011) (63) (51) (33) ;(00111010) (72) (58) (3A) ;(00111000) (70) (56) (38) ;(01011100) (134) (92) (5C) ;(00001111) (17) (15) (0F) ;(11001001) (311) (201) (C9) ; -;48;(11000101) (305) (197) (C5) ;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(11000011) (303) (195) (C3) ;(10011110) (236) (158) (9E) ;(00010110) (26) (22) (16) ; -;56;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01111000) (170) (120) (78) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01111000) (170) (120) (78) ; -;64;(01011100) (134) (92) (5C) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(01000000) (100) (64) (40) ; -;72;(11000101) (305) (197) (C5) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00000010) (2) (2) (02) ;(11010001) (321) (209) (D1) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ; -;80;(11110001) (361) (241) (F1) ;(11111011) (373) (251) (FB) ;(11001001) (311) (201) (C9) ;(11100001) (341) (225) (E1) ;(01101110) (156) (110) (6E) ;(11111101) (375) (253) (FD) ;(01110101) (165) (117) (75) ;(00000000) (0) (0) (00) ; -;88;(11101101) (355) (237) (ED) ;(01111011) (173) (123) (7B) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11000011) (303) (195) (C3) ;(11000101) (305) (197) (C5) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ; -;96;(11010100) (324) (212) (D4) ;(00010110) (26) (22) (16) ;(11010010) (322) (210) (D2) ;(00011100) (34) (28) (1C) ;(00010010) (22) (18) (12) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ; -;104;(11001101) (315) (205) (CD) ;(01011111) (137) (95) (5F) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(11101001) (351) (233) (E9) ; -;112;(11100001) (341) (225) (E1) ;(11110001) (361) (241) (F1) ;(11101101) (355) (237) (ED) ;(01000101) (105) (69) (45) ;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ; -;120;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(11010000) (320) (208) (D0) ; -;128;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ; -;136;(00111111) (77) (63) (3F) ;(11011000) (330) (216) (D8) ;(00100011) (43) (35) (23) ;(11111110) (376) (254) (FE) ;(00010110) (26) (22) (16) ;(00111000) (70) (56) (38) ;(00000001) (1) (1) (01) ;(00100011) (43) (35) (23) ; -;144;(00110111) (67) (55) (37) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(10111111) (277) (191) (BF) ;(01010010) (122) (82) (52) ;(01001110) (116) (78) (4E) ; -;152;(11000100) (304) (196) (C4) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(01001011) (113) (75) (4B) ;(01000101) (105) (69) (45) ;(01011001) (131) (89) (59) ;(10100100) (244) (164) (A4) ;(01010000) (120) (80) (50) ; -;160;(11001001) (311) (201) (C9) ;(01000110) (106) (70) (46) ;(11001110) (316) (206) (CE) ;(01010000) (120) (80) (50) ;(01001111) (117) (79) (4F) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(11010100) (324) (212) (D4) ; -;168;(01010011) (123) (83) (53) ;(01000011) (103) (67) (43) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01000101) (105) (69) (45) ;(01001110) (116) (78) (4E) ;(10100100) (244) (164) (A4) ;(01000001) (101) (65) (41) ; -;176;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(11010010) (322) (210) (D2) ;(01000001) (101) (65) (41) ;(11010100) (324) (212) (D4) ;(01010100) (124) (84) (54) ;(01000001) (101) (65) (41) ;(11000010) (302) (194) (C2) ; -;184;(01010110) (126) (86) (56) ;(01000001) (101) (65) (41) ;(01001100) (114) (76) (4C) ;(10100100) (244) (164) (A4) ;(01000011) (103) (67) (43) ;(01001111) (117) (79) (4F) ;(01000100) (104) (68) (44) ;(11000101) (305) (197) (C5) ; -;192;(01010110) (126) (86) (56) ;(01000001) (101) (65) (41) ;(11001100) (314) (204) (CC) ;(01001100) (114) (76) (4C) ;(01000101) (105) (69) (45) ;(11001110) (316) (206) (CE) ;(01010011) (123) (83) (53) ;(01001001) (111) (73) (49) ; -;200;(11001110) (316) (206) (CE) ;(01000011) (103) (67) (43) ;(01001111) (117) (79) (4F) ;(11010011) (323) (211) (D3) ;(01010100) (124) (84) (54) ;(01000001) (101) (65) (41) ;(11001110) (316) (206) (CE) ;(01000001) (101) (65) (41) ; -;208;(01010011) (123) (83) (53) ;(11001110) (316) (206) (CE) ;(01000001) (101) (65) (41) ;(01000011) (103) (67) (43) ;(11010011) (323) (211) (D3) ;(01000001) (101) (65) (41) ;(01010100) (124) (84) (54) ;(11001110) (316) (206) (CE) ; -;216;(01001100) (114) (76) (4C) ;(11001110) (316) (206) (CE) ;(01000101) (105) (69) (45) ;(01011000) (130) (88) (58) ;(11010000) (320) (208) (D0) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(11010100) (324) (212) (D4) ; -;224;(01010011) (123) (83) (53) ;(01010001) (121) (81) (51) ;(11010010) (322) (210) (D2) ;(01010011) (123) (83) (53) ;(01000111) (107) (71) (47) ;(11001110) (316) (206) (CE) ;(01000001) (101) (65) (41) ;(01000010) (102) (66) (42) ; -;232;(11010011) (323) (211) (D3) ;(01010000) (120) (80) (50) ;(01000101) (105) (69) (45) ;(01000101) (105) (69) (45) ;(11001011) (313) (203) (CB) ;(01001001) (111) (73) (49) ;(11001110) (316) (206) (CE) ;(01010101) (125) (85) (55) ; -;240;(01010011) (123) (83) (53) ;(11010010) (322) (210) (D2) ;(01010011) (123) (83) (53) ;(01010100) (124) (84) (54) ;(01010010) (122) (82) (52) ;(10100100) (244) (164) (A4) ;(01000011) (103) (67) (43) ;(01001000) (110) (72) (48) ; -;248;(01010010) (122) (82) (52) ;(10100100) (244) (164) (A4) ;(01001110) (116) (78) (4E) ;(01001111) (117) (79) (4F) ;(11010100) (324) (212) (D4) ;(01000010) (102) (66) (42) ;(01001001) (111) (73) (49) ;(11001110) (316) (206) (CE) ; -;256;(01001111) (117) (79) (4F) ;(11010010) (322) (210) (D2) ;(01000001) (101) (65) (41) ;(01001110) (116) (78) (4E) ;(11000100) (304) (196) (C4) ;(00111100) (74) (60) (3C) ;(10111101) (275) (189) (BD) ;(00111110) (76) (62) (3E) ; -;264;(10111101) (275) (189) (BD) ;(00111100) (74) (60) (3C) ;(10111110) (276) (190) (BE) ;(01001100) (114) (76) (4C) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(11000101) (305) (197) (C5) ;(01010100) (124) (84) (54) ; -;272;(01001000) (110) (72) (48) ;(01000101) (105) (69) (45) ;(11001110) (316) (206) (CE) ;(01010100) (124) (84) (54) ;(11001111) (317) (207) (CF) ;(01010011) (123) (83) (53) ;(01010100) (124) (84) (54) ;(01000101) (105) (69) (45) ; -;280;(11010000) (320) (208) (D0) ;(01000100) (104) (68) (44) ;(01000101) (105) (69) (45) ;(01000110) (106) (70) (46) ;(00100000) (40) (32) (20) ;(01000110) (106) (70) (46) ;(11001110) (316) (206) (CE) ;(01000011) (103) (67) (43) ; -;288;(01000001) (101) (65) (41) ;(11010100) (324) (212) (D4) ;(01000110) (106) (70) (46) ;(01001111) (117) (79) (4F) ;(01010010) (122) (82) (52) ;(01001101) (115) (77) (4D) ;(01000001) (101) (65) (41) ;(11010100) (324) (212) (D4) ; -;296;(01001101) (115) (77) (4D) ;(01001111) (117) (79) (4F) ;(01010110) (126) (86) (56) ;(11000101) (305) (197) (C5) ;(01000101) (105) (69) (45) ;(01010010) (122) (82) (52) ;(01000001) (101) (65) (41) ;(01010011) (123) (83) (53) ; -;304;(11000101) (305) (197) (C5) ;(01001111) (117) (79) (4F) ;(01010000) (120) (80) (50) ;(01000101) (105) (69) (45) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(10100011) (243) (163) (A3) ;(01000011) (103) (67) (43) ; -;312;(01001100) (114) (76) (4C) ;(01001111) (117) (79) (4F) ;(01010011) (123) (83) (53) ;(01000101) (105) (69) (45) ;(00100000) (40) (32) (20) ;(10100011) (243) (163) (A3) ;(01001101) (115) (77) (4D) ;(01000101) (105) (69) (45) ; -;320;(01010010) (122) (82) (52) ;(01000111) (107) (71) (47) ;(11000101) (305) (197) (C5) ;(01010110) (126) (86) (56) ;(01000101) (105) (69) (45) ;(01010010) (122) (82) (52) ;(01001001) (111) (73) (49) ;(01000110) (106) (70) (46) ; -;328;(11011001) (331) (217) (D9) ;(01000010) (102) (66) (42) ;(01000101) (105) (69) (45) ;(01000101) (105) (69) (45) ;(11010000) (320) (208) (D0) ;(01000011) (103) (67) (43) ;(01001001) (111) (73) (49) ;(01010010) (122) (82) (52) ; -;336;(01000011) (103) (67) (43) ;(01001100) (114) (76) (4C) ;(11000101) (305) (197) (C5) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(11001011) (313) (203) (CB) ;(01010000) (120) (80) (50) ;(01000001) (101) (65) (41) ; -;344;(01010000) (120) (80) (50) ;(01000101) (105) (69) (45) ;(11010010) (322) (210) (D2) ;(01000110) (106) (70) (46) ;(01001100) (114) (76) (4C) ;(01000001) (101) (65) (41) ;(01010011) (123) (83) (53) ;(11001000) (310) (200) (C8) ; -;352;(01000010) (102) (66) (42) ;(01010010) (122) (82) (52) ;(01001001) (111) (73) (49) ;(01000111) (107) (71) (47) ;(01001000) (110) (72) (48) ;(11010100) (324) (212) (D4) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ; -;360;(01010110) (126) (86) (56) ;(01000101) (105) (69) (45) ;(01010010) (122) (82) (52) ;(01010011) (123) (83) (53) ;(11000101) (305) (197) (C5) ;(01001111) (117) (79) (4F) ;(01010110) (126) (86) (56) ;(01000101) (105) (69) (45) ; -;368;(11010010) (322) (210) (D2) ;(01001111) (117) (79) (4F) ;(01010101) (125) (85) (55) ;(11010100) (324) (212) (D4) ;(01001100) (114) (76) (4C) ;(01010000) (120) (80) (50) ;(01010010) (122) (82) (52) ;(01001001) (111) (73) (49) ; -;376;(01001110) (116) (78) (4E) ;(11010100) (324) (212) (D4) ;(01001100) (114) (76) (4C) ;(01001100) (114) (76) (4C) ;(01001001) (111) (73) (49) ;(01010011) (123) (83) (53) ;(11010100) (324) (212) (D4) ;(01010011) (123) (83) (53) ; -;384;(01010100) (124) (84) (54) ;(01001111) (117) (79) (4F) ;(11010000) (320) (208) (D0) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01000001) (101) (65) (41) ;(11000100) (304) (196) (C4) ;(01000100) (104) (68) (44) ; -;392;(01000001) (101) (65) (41) ;(01010100) (124) (84) (54) ;(11000001) (301) (193) (C1) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01010011) (123) (83) (53) ;(01010100) (124) (84) (54) ;(01001111) (117) (79) (4F) ; -;400;(01010010) (122) (82) (52) ;(11000101) (305) (197) (C5) ;(01001110) (116) (78) (4E) ;(01000101) (105) (69) (45) ;(11010111) (327) (215) (D7) ;(01000010) (102) (66) (42) ;(01001111) (117) (79) (4F) ;(01010010) (122) (82) (52) ; -;408;(01000100) (104) (68) (44) ;(01000101) (105) (69) (45) ;(11010010) (322) (210) (D2) ;(01000011) (103) (67) (43) ;(01001111) (117) (79) (4F) ;(01001110) (116) (78) (4E) ;(01010100) (124) (84) (54) ;(01001001) (111) (73) (49) ; -;416;(01001110) (116) (78) (4E) ;(01010101) (125) (85) (55) ;(11000101) (305) (197) (C5) ;(01000100) (104) (68) (44) ;(01001001) (111) (73) (49) ;(11001101) (315) (205) (CD) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ; -;424;(11001101) (315) (205) (CD) ;(01000110) (106) (70) (46) ;(01001111) (117) (79) (4F) ;(11010010) (322) (210) (D2) ;(01000111) (107) (71) (47) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ;(01010100) (124) (84) (54) ; -;432;(11001111) (317) (207) (CF) ;(01000111) (107) (71) (47) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ;(01010011) (123) (83) (53) ;(01010101) (125) (85) (55) ;(11000010) (302) (194) (C2) ;(01001001) (111) (73) (49) ; -;440;(01001110) (116) (78) (4E) ;(01010000) (120) (80) (50) ;(01010101) (125) (85) (55) ;(11010100) (324) (212) (D4) ;(01001100) (114) (76) (4C) ;(01001111) (117) (79) (4F) ;(01000001) (101) (65) (41) ;(11000100) (304) (196) (C4) ; -;448;(01001100) (114) (76) (4C) ;(01001001) (111) (73) (49) ;(01010011) (123) (83) (53) ;(11010100) (324) (212) (D4) ;(01001100) (114) (76) (4C) ;(01000101) (105) (69) (45) ;(11010100) (324) (212) (D4) ;(01010000) (120) (80) (50) ; -;456;(01000001) (101) (65) (41) ;(01010101) (125) (85) (55) ;(01010011) (123) (83) (53) ;(11000101) (305) (197) (C5) ;(01001110) (116) (78) (4E) ;(01000101) (105) (69) (45) ;(01011000) (130) (88) (58) ;(11010100) (324) (212) (D4) ; -;464;(01010000) (120) (80) (50) ;(01001111) (117) (79) (4F) ;(01001011) (113) (75) (4B) ;(11000101) (305) (197) (C5) ;(01010000) (120) (80) (50) ;(01010010) (122) (82) (52) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ; -;472;(11010100) (324) (212) (D4) ;(01010000) (120) (80) (50) ;(01001100) (114) (76) (4C) ;(01001111) (117) (79) (4F) ;(11010100) (324) (212) (D4) ;(01010010) (122) (82) (52) ;(01010101) (125) (85) (55) ;(11001110) (316) (206) (CE) ; -;480;(01010011) (123) (83) (53) ;(01000001) (101) (65) (41) ;(01010110) (126) (86) (56) ;(11000101) (305) (197) (C5) ;(01010010) (122) (82) (52) ;(01000001) (101) (65) (41) ;(01001110) (116) (78) (4E) ;(01000100) (104) (68) (44) ; -;488;(01001111) (117) (79) (4F) ;(01001101) (115) (77) (4D) ;(01001001) (111) (73) (49) ;(01011010) (132) (90) (5A) ;(11000101) (305) (197) (C5) ;(01001001) (111) (73) (49) ;(11000110) (306) (198) (C6) ;(01000011) (103) (67) (43) ; -;496;(01001100) (114) (76) (4C) ;(11010011) (323) (211) (D3) ;(01000100) (104) (68) (44) ;(01010010) (122) (82) (52) ;(01000001) (101) (65) (41) ;(11010111) (327) (215) (D7) ;(01000011) (103) (67) (43) ;(01001100) (114) (76) (4C) ; -;504;(01000101) (105) (69) (45) ;(01000001) (101) (65) (41) ;(11010010) (322) (210) (D2) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01010100) (124) (84) (54) ;(01010101) (125) (85) (55) ;(01010010) (122) (82) (52) ; -;512;(11001110) (316) (206) (CE) ;(01000011) (103) (67) (43) ;(01001111) (117) (79) (4F) ;(01010000) (120) (80) (50) ;(11011001) (331) (217) (D9) ;(01000010) (102) (66) (42) ;(01001000) (110) (72) (48) ;(01011001) (131) (89) (59) ; -;520;(00110110) (66) (54) (36) ;(00110101) (65) (53) (35) ;(01010100) (124) (84) (54) ;(01000111) (107) (71) (47) ;(01010110) (126) (86) (56) ;(01001110) (116) (78) (4E) ;(01001010) (112) (74) (4A) ;(01010101) (125) (85) (55) ; -;528;(00110111) (67) (55) (37) ;(00110100) (64) (52) (34) ;(01010010) (122) (82) (52) ;(01000110) (106) (70) (46) ;(01000011) (103) (67) (43) ;(01001101) (115) (77) (4D) ;(01001011) (113) (75) (4B) ;(01001001) (111) (73) (49) ; -;536;(00111000) (70) (56) (38) ;(00110011) (63) (51) (33) ;(01000101) (105) (69) (45) ;(01000100) (104) (68) (44) ;(01011000) (130) (88) (58) ;(00001110) (16) (14) (0E) ;(01001100) (114) (76) (4C) ;(01001111) (117) (79) (4F) ; -;544;(00111001) (71) (57) (39) ;(00110010) (62) (50) (32) ;(01010111) (127) (87) (57) ;(01010011) (123) (83) (53) ;(01011010) (132) (90) (5A) ;(00100000) (40) (32) (20) ;(00001101) (15) (13) (0D) ;(01010000) (120) (80) (50) ; -;552;(00110000) (60) (48) (30) ;(00110001) (61) (49) (31) ;(01010001) (121) (81) (51) ;(01000001) (101) (65) (41) ;(11100011) (343) (227) (E3) ;(11000100) (304) (196) (C4) ;(11100000) (340) (224) (E0) ;(11100100) (344) (228) (E4) ; -;560;(10110100) (264) (180) (B4) ;(10111100) (274) (188) (BC) ;(10111101) (275) (189) (BD) ;(10111011) (273) (187) (BB) ;(10101111) (257) (175) (AF) ;(10110000) (260) (176) (B0) ;(10110001) (261) (177) (B1) ;(11000000) (300) (192) (C0) ; -;568;(10100111) (247) (167) (A7) ;(10100110) (246) (166) (A6) ;(10111110) (276) (190) (BE) ;(10101101) (255) (173) (AD) ;(10110010) (262) (178) (B2) ;(10111010) (272) (186) (BA) ;(11100101) (345) (229) (E5) ;(10100101) (245) (165) (A5) ; -;576;(11000010) (302) (194) (C2) ;(11100001) (341) (225) (E1) ;(10110011) (263) (179) (B3) ;(10111001) (271) (185) (B9) ;(11000001) (301) (193) (C1) ;(10111000) (270) (184) (B8) ;(01111110) (176) (126) (7E) ;(11011100) (334) (220) (DC) ; -;584;(11011010) (332) (218) (DA) ;(01011100) (134) (92) (5C) ;(10110111) (267) (183) (B7) ;(01111011) (173) (123) (7B) ;(01111101) (175) (125) (7D) ;(11011000) (330) (216) (D8) ;(10111111) (277) (191) (BF) ;(10101110) (256) (174) (AE) ; -;592;(10101010) (252) (170) (AA) ;(10101011) (253) (171) (AB) ;(11011101) (335) (221) (DD) ;(11011110) (336) (222) (DE) ;(11011111) (337) (223) (DF) ;(01111111) (177) (127) (7F) ;(10110101) (265) (181) (B5) ;(11010110) (326) (214) (D6) ; -;600;(01111100) (174) (124) (7C) ;(11010101) (325) (213) (D5) ;(01011101) (135) (93) (5D) ;(11011011) (333) (219) (DB) ;(10110110) (266) (182) (B6) ;(11011001) (331) (217) (D9) ;(01011011) (133) (91) (5B) ;(11010111) (327) (215) (D7) ; -;608;(00001100) (14) (12) (0C) ;(00000111) (7) (7) (07) ;(00000110) (6) (6) (06) ;(00000100) (4) (4) (04) ;(00000101) (5) (5) (05) ;(00001000) (10) (8) (08) ;(00001010) (12) (10) (0A) ;(00001011) (13) (11) (0B) ; -;616;(00001001) (11) (9) (09) ;(00001111) (17) (15) (0F) ;(11100010) (342) (226) (E2) ;(00101010) (52) (42) (2A) ;(00111111) (77) (63) (3F) ;(11001101) (315) (205) (CD) ;(11001000) (310) (200) (C8) ;(11001100) (314) (204) (CC) ; -;624;(11001011) (313) (203) (CB) ;(01011110) (136) (94) (5E) ;(10101100) (254) (172) (AC) ;(00101101) (55) (45) (2D) ;(00101011) (53) (43) (2B) ;(00111101) (75) (61) (3D) ;(00101110) (56) (46) (2E) ;(00101100) (54) (44) (2C) ; -;632;(00111011) (73) (59) (3B) ;(00100010) (42) (34) (22) ;(11000111) (307) (199) (C7) ;(00111100) (74) (60) (3C) ;(11000011) (303) (195) (C3) ;(00111110) (76) (62) (3E) ;(11000101) (305) (197) (C5) ;(00101111) (57) (47) (2F) ; -;640;(11001001) (311) (201) (C9) ;(01100000) (140) (96) (60) ;(11000110) (306) (198) (C6) ;(00111010) (72) (58) (3A) ;(11010000) (320) (208) (D0) ;(11001110) (316) (206) (CE) ;(10101000) (250) (168) (A8) ;(11001010) (312) (202) (CA) ; -;648;(11010011) (323) (211) (D3) ;(11010100) (324) (212) (D4) ;(11010001) (321) (209) (D1) ;(11010010) (322) (210) (D2) ;(10101001) (251) (169) (A9) ;(11001111) (317) (207) (CF) ;(00101110) (56) (46) (2E) ;(00101111) (57) (47) (2F) ; -;656;(00010001) (21) (17) (11) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(00000001) (1) (1) (01) ;(11111110) (376) (254) (FE) ;(11111110) (376) (254) (FE) ;(11101101) (355) (237) (ED) ;(01111000) (170) (120) (78) ; -;664;(00101111) (57) (47) (2F) ;(11100110) (346) (230) (E6) ;(00011111) (37) (31) (1F) ;(00101000) (50) (40) (28) ;(00001110) (16) (14) (0E) ;(01100111) (147) (103) (67) ;(01111101) (175) (125) (7D) ;(00010100) (24) (20) (14) ; -;672;(11000000) (300) (192) (C0) ;(11010110) (326) (214) (D6) ;(00001000) (10) (8) (08) ;(11001011) (313) (203) (CB) ;(00111100) (74) (60) (3C) ;(00110000) (60) (48) (30) ;(11111010) (372) (250) (FA) ;(01010011) (123) (83) (53) ; -;680;(01011111) (137) (95) (5F) ;(00100000) (40) (32) (20) ;(11110100) (364) (244) (F4) ;(00101101) (55) (45) (2D) ;(11001011) (313) (203) (CB) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(11100110) (346) (230) (E6) ; -;688;(01111010) (172) (122) (7A) ;(00111100) (74) (60) (3C) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ;(00011001) (31) (25) (19) ; -;696;(11001000) (310) (200) (C8) ;(01111011) (173) (123) (7B) ;(01011010) (132) (90) (5A) ;(01010111) (127) (87) (57) ;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ; -;704;(10001110) (216) (142) (8E) ;(00000010) (2) (2) (02) ;(11000000) (300) (192) (C0) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ; -;712;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(00100011) (43) (35) (23) ;(00110101) (65) (53) (35) ;(00101011) (53) (43) (2B) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00110110) (66) (54) (36) ; -;720;(11111111) (377) (255) (FF) ;(01111101) (175) (125) (7D) ;(00100001) (41) (33) (21) ;(00000100) (4) (4) (04) ;(01011100) (134) (92) (5C) ;(10111101) (275) (189) (BD) ;(00100000) (40) (32) (20) ;(11101110) (356) (238) (EE) ; -;728;(11001101) (315) (205) (CD) ;(00011110) (36) (30) (1E) ;(00000011) (3) (3) (03) ;(11010000) (320) (208) (D0) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(01011100) (134) (92) (5C) ;(10111110) (276) (190) (BE) ; -;736;(00101000) (50) (40) (28) ;(00101110) (56) (46) (2E) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(00000100) (4) (4) (04) ;(01011100) (134) (92) (5C) ;(10111110) (276) (190) (BE) ;(00101000) (50) (40) (28) ; -;744;(00100111) (47) (39) (27) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11101011) (353) (235) (EB) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ; -;752;(11001000) (310) (200) (C8) ;(01011111) (137) (95) (5F) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00000101) (5) (5) (05) ;(00100011) (43) (35) (23) ;(00111010) (72) (58) (3A) ; -;760;(00001001) (11) (9) (09) ;(01011100) (134) (92) (5C) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(00000111) (7) (7) (07) ;(11111101) (375) (253) (FD) ; -;768;(01010110) (126) (86) (56) ;(00000001) (1) (1) (01) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(00110011) (63) (51) (33) ;(00000011) (3) (3) (03) ;(11100001) (341) (225) (E1) ;(01110111) (167) (119) (77) ; -;776;(00110010) (62) (50) (32) ;(00001000) (10) (8) (08) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11101110) (356) (238) (EE) ;(11001001) (311) (201) (C9) ; -;784;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00000101) (5) (5) (05) ;(00100011) (43) (35) (23) ;(00110101) (65) (53) (35) ;(11000000) (300) (192) (C0) ;(00111010) (72) (58) (3A) ;(00001010) (12) (10) (0A) ; -;792;(01011100) (134) (92) (5C) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(00011000) (30) (24) (18) ;(11101010) (352) (234) (EA) ;(01000010) (102) (66) (42) ;(00010110) (26) (22) (16) ; -;800;(00000000) (0) (0) (00) ;(01111011) (173) (123) (7B) ;(11111110) (376) (254) (FE) ;(00100111) (47) (39) (27) ;(11010000) (320) (208) (D0) ;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(00100000) (40) (32) (20) ; -;808;(00000011) (3) (3) (03) ;(11001011) (313) (203) (CB) ;(01111000) (170) (120) (78) ;(11000000) (300) (192) (C0) ;(00100001) (41) (33) (21) ;(00000101) (5) (5) (05) ;(00000010) (2) (2) (02) ;(00011001) (31) (25) (19) ; -;816;(01111110) (176) (126) (7E) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ;(01111011) (173) (123) (7B) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(00111000) (70) (56) (38) ;(00101111) (57) (47) (2F) ; -;824;(00001101) (15) (13) (0D) ;(11111010) (372) (250) (FA) ;(01001111) (117) (79) (4F) ;(00000011) (3) (3) (03) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(11000011) (303) (195) (C3) ;(10101010) (252) (170) (AA) ; -;832;(00000100) (4) (4) (04) ;(00100001) (41) (33) (21) ;(11101011) (353) (235) (EB) ;(00000001) (1) (1) (01) ;(00000100) (4) (4) (04) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(00100001) (41) (33) (21) ; -;840;(00000101) (5) (5) (05) ;(00000010) (2) (2) (02) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(01111110) (176) (126) (7E) ;(11001001) (311) (201) (C9) ;(00100001) (41) (33) (21) ; -;848;(00101001) (51) (41) (29) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(01000000) (100) (64) (40) ;(00101000) (50) (40) (28) ;(11110100) (364) (244) (F4) ;(11001011) (313) (203) (CB) ;(01011010) (132) (90) (5A) ; -;856;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01011110) (136) (94) (5E) ;(11000000) (300) (192) (C0) ;(00000100) (4) (4) (04) ; -;864;(11000000) (300) (192) (C0) ;(11000110) (306) (198) (C6) ;(00100000) (40) (32) (20) ;(11001001) (311) (201) (C9) ;(11000110) (306) (198) (C6) ;(10100101) (245) (165) (A5) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ; -;872;(00110000) (60) (48) (30) ;(11011000) (330) (216) (D8) ;(00001101) (15) (13) (0D) ;(11111010) (372) (250) (FA) ;(10011101) (235) (157) (9D) ;(00000011) (3) (3) (03) ;(00100000) (40) (32) (20) ;(00011001) (31) (25) (19) ; -;880;(00100001) (41) (33) (21) ;(01010100) (124) (84) (54) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(01101000) (150) (104) (68) ;(00101000) (50) (40) (28) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ; -;888;(00111000) (70) (56) (38) ;(00110000) (60) (48) (30) ;(00000111) (7) (7) (07) ;(11010110) (326) (214) (D6) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11001000) (310) (200) (C8) ;(11000110) (306) (198) (C6) ; -;896;(00001000) (10) (8) (08) ;(11001001) (311) (201) (C9) ;(11010110) (326) (214) (D6) ;(00110110) (66) (54) (36) ;(00000100) (4) (4) (04) ;(11001000) (310) (200) (C8) ;(11000110) (306) (198) (C6) ;(11111110) (376) (254) (FE) ; -;904;(11001001) (311) (201) (C9) ;(00100001) (41) (33) (21) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(11111110) (376) (254) (FE) ;(00111001) (71) (57) (39) ;(00101000) (50) (40) (28) ;(10111010) (272) (186) (BA) ; -;912;(11111110) (376) (254) (FE) ;(00110000) (60) (48) (30) ;(00101000) (50) (40) (28) ;(10110110) (266) (182) (B6) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(11000110) (306) (198) (C6) ;(10000000) (200) (128) (80) ; -;920;(00000100) (4) (4) (04) ;(11001000) (310) (200) (C8) ;(11101110) (356) (238) (EE) ;(00001111) (17) (15) (0F) ;(11001001) (311) (201) (C9) ;(00000100) (4) (4) (04) ;(11001000) (310) (200) (C8) ;(11001011) (313) (203) (CB) ; -;928;(01101000) (150) (104) (68) ;(00100001) (41) (33) (21) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(00100000) (40) (32) (20) ;(10100100) (244) (164) (A4) ;(11010110) (326) (214) (D6) ;(00010000) (20) (16) (10) ; -;936;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00111110) (76) (62) (3E) ; -;944;(01011111) (137) (95) (5F) ;(11001001) (311) (201) (C9) ;(00111110) (76) (62) (3E) ;(01000000) (100) (64) (40) ;(11001001) (311) (201) (C9) ;(11110011) (363) (243) (F3) ;(01111101) (175) (125) (7D) ;(11001011) (313) (203) (CB) ; -;952;(00111101) (75) (61) (3D) ;(11001011) (313) (203) (CB) ;(00111101) (75) (61) (3D) ;(00101111) (57) (47) (2F) ;(11100110) (346) (230) (E6) ;(00000011) (3) (3) (03) ;(01001111) (117) (79) (4F) ;(00000110) (6) (6) (06) ; -;960;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(00100001) (41) (33) (21) ;(11010001) (321) (209) (D1) ;(00000011) (3) (3) (03) ;(11011101) (335) (221) (DD) ;(00001001) (11) (9) (09) ;(00111010) (72) (58) (3A) ; -;968;(01001000) (110) (72) (48) ;(01011100) (134) (92) (5C) ;(11100110) (346) (230) (E6) ;(00111000) (70) (56) (38) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(11110110) (366) (246) (F6) ; -;976;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00001100) (14) (12) (0C) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ; -;984;(11111101) (375) (253) (FD) ;(00001110) (16) (14) (0E) ;(00111111) (77) (63) (3F) ;(00000101) (5) (5) (05) ;(11000010) (302) (194) (C2) ;(11010110) (326) (214) (D6) ;(00000011) (3) (3) (03) ;(11101110) (356) (238) (EE) ; -;992;(00010000) (20) (16) (10) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(01000100) (104) (68) (44) ;(01001111) (117) (79) (4F) ;(11001011) (313) (203) (CB) ;(01100111) (147) (103) (67) ;(00100000) (40) (32) (20) ; -;1000;(00001001) (11) (9) (09) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(01111001) (171) (121) (79) ;(01001101) (115) (77) (4D) ;(00011011) (33) (27) (1B) ; -;1008;(11011101) (335) (221) (DD) ;(11101001) (351) (233) (E9) ;(01001101) (115) (77) (4D) ;(00001100) (14) (12) (0C) ;(11011101) (335) (221) (DD) ;(11101001) (351) (233) (E9) ;(11111011) (373) (251) (FB) ;(11001001) (311) (201) (C9) ; -;1016;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00100111) (47) (39) (27) ;(11000000) (300) (192) (C0) ;(00000011) (3) (3) (03) ;(00110100) (64) (52) (34) ;(11101100) (354) (236) (EC) ;(01101100) (154) (108) (6C) ; -;1024;(10011000) (230) (152) (98) ;(00011111) (37) (31) (1F) ;(11110101) (365) (245) (F5) ;(00000100) (4) (4) (04) ;(10100001) (241) (161) (A1) ;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ;(00100001) (41) (33) (21) ; -;1032;(10010010) (222) (146) (92) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ; -;1040;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(01111000) (170) (120) (78) ;(00010111) (27) (23) (17) ;(10011111) (237) (159) (9F) ;(10111001) (271) (185) (B9) ;(00100000) (40) (32) (20) ;(01010100) (124) (84) (54) ; -;1048;(00100011) (43) (35) (23) ;(10111110) (276) (190) (BE) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01111000) (170) (120) (78) ;(11000110) (306) (198) (C6) ;(00111100) (74) (60) (3C) ;(11110010) (362) (242) (F2) ; -;1056;(00100101) (45) (37) (25) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(01101100) (154) (108) (6C) ;(00000100) (4) (4) (04) ;(00000110) (6) (6) (06) ;(11111010) (372) (250) (FA) ;(00000100) (4) (4) (04) ; -;1064;(11010110) (326) (214) (D6) ;(00001100) (14) (12) (0C) ;(00110000) (60) (48) (30) ;(11111011) (373) (251) (FB) ;(11000110) (306) (198) (C6) ;(00001100) (14) (12) (0C) ;(11000101) (305) (197) (C5) ;(00100001) (41) (33) (21) ; -;1072;(01101110) (156) (110) (6E) ;(00000100) (4) (4) (04) ;(11001101) (315) (205) (CD) ;(00000110) (6) (6) (06) ;(00110100) (64) (52) (34) ;(11001101) (315) (205) (CD) ;(10110100) (264) (180) (B4) ;(00110011) (63) (51) (33) ; -;1080;(11101111) (357) (239) (EF) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ;(11110001) (361) (241) (F1) ;(10000110) (206) (134) (86) ;(01110111) (167) (119) (77) ;(11101111) (357) (239) (EF) ;(11000000) (300) (192) (C0) ; -;1088;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ;(11111110) (376) (254) (FE) ;(00001011) (13) (11) (0B) ; -;1096;(00110000) (60) (48) (30) ;(00100010) (42) (34) (22) ;(11101111) (357) (239) (EF) ;(11100000) (340) (224) (E0) ;(00000100) (4) (4) (04) ;(11100000) (340) (224) (E0) ;(00110100) (64) (52) (34) ;(10000000) (200) (128) (80) ; -;1104;(01000011) (103) (67) (43) ;(01010101) (125) (85) (55) ;(10011111) (237) (159) (9F) ;(10000000) (200) (128) (80) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00110100) (64) (52) (34) ;(00110101) (65) (53) (35) ; -;1112;(01110001) (161) (113) (71) ;(00000011) (3) (3) (03) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ; -;1120;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(11100001) (341) (225) (E1) ;(01010000) (120) (80) (50) ;(01011001) (131) (89) (59) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(11001000) (310) (200) (C8) ; -;1128;(00011011) (33) (27) (1B) ;(11000011) (303) (195) (C3) ;(10110101) (265) (181) (B5) ;(00000011) (3) (3) (03) ;(11001111) (317) (207) (CF) ;(00001010) (12) (10) (0A) ;(10001001) (211) (137) (89) ;(00000010) (2) (2) (02) ; -;1136;(11010000) (320) (208) (D0) ;(00010010) (22) (18) (12) ;(10000110) (206) (134) (86) ;(10001001) (211) (137) (89) ;(00001010) (12) (10) (0A) ;(10010111) (227) (151) (97) ;(01100000) (140) (96) (60) ;(01110101) (165) (117) (75) ; -;1144;(10001001) (211) (137) (89) ;(00010010) (22) (18) (12) ;(11010101) (325) (213) (D5) ;(00010111) (27) (23) (17) ;(00011111) (37) (31) (1F) ;(10001001) (211) (137) (89) ;(00011011) (33) (27) (1B) ;(10010000) (220) (144) (90) ; -;1152;(01000001) (101) (65) (41) ;(00000010) (2) (2) (02) ;(10001001) (211) (137) (89) ;(00100100) (44) (36) (24) ;(11010000) (320) (208) (D0) ;(01010011) (123) (83) (53) ;(11001010) (312) (202) (CA) ;(10001001) (211) (137) (89) ; -;1160;(00101110) (56) (46) (2E) ;(10011101) (235) (157) (9D) ;(00110110) (66) (54) (36) ;(10110001) (261) (177) (B1) ;(10001001) (211) (137) (89) ;(00111000) (70) (56) (38) ;(11111111) (377) (255) (FF) ;(01001001) (111) (73) (49) ; -;1168;(00111110) (76) (62) (3E) ;(10001001) (211) (137) (89) ;(01000011) (103) (67) (43) ;(11111111) (377) (255) (FF) ;(01101010) (152) (106) (6A) ;(01110011) (163) (115) (73) ;(10001001) (211) (137) (89) ;(01001111) (117) (79) (4F) ; -;1176;(10100111) (247) (167) (A7) ;(00000000) (0) (0) (00) ;(01010100) (124) (84) (54) ;(10001001) (211) (137) (89) ;(01011100) (134) (92) (5C) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;1184;(10001001) (211) (137) (89) ;(01101001) (151) (105) (69) ;(00010100) (24) (20) (14) ;(11110110) (366) (246) (F6) ;(00100100) (44) (36) (24) ;(10001001) (211) (137) (89) ;(01110110) (166) (118) (76) ;(11110001) (361) (241) (F1) ; -;1192;(00010000) (20) (16) (10) ;(00000101) (5) (5) (05) ;(11000110) (306) (198) (C6) ;(01001111) (117) (79) (4F) ;(11111110) (376) (254) (FE) ;(10100101) (245) (165) (A5) ;(11011000) (330) (216) (D8) ;(11110001) (361) (241) (F1) ; -;1200;(11100001) (341) (225) (E1) ;(10101111) (257) (175) (AF) ;(01101111) (157) (111) (6F) ;(01110111) (167) (119) (77) ;(00101110) (56) (46) (2E) ;(00000100) (4) (4) (04) ;(01110111) (167) (119) (77) ;(11001001) (311) (201) (C9) ; -;1208;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11001000) (310) (200) (C8) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(11000000) (300) (192) (C0) ;(11001111) (317) (207) (CF) ; -;1216;(00001011) (13) (11) (0B) ;(00000000) (0) (0) (00) ;(00100001) (41) (33) (21) ;(00111111) (77) (63) (3F) ;(00000101) (5) (5) (05) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ;(10000000) (200) (128) (80) ; -;1224;(00011111) (37) (31) (1F) ;(11001011) (313) (203) (CB) ;(01111111) (177) (127) (7F) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(00100001) (41) (33) (21) ;(10011000) (230) (152) (98) ;(00001100) (14) (12) (0C) ; -;1232;(00001000) (10) (8) (08) ;(00010011) (23) (19) (13) ;(11011101) (335) (221) (DD) ;(00101011) (53) (43) (2B) ;(11110011) (363) (243) (F3) ;(00111110) (76) (62) (3E) ;(00000010) (2) (2) (02) ;(01000111) (107) (71) (47) ; -;1240;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(11101110) (356) (238) (EE) ;(00001111) (17) (15) (0F) ;(00000110) (6) (6) (06) ;(10100100) (244) (164) (A4) ; -;1248;(00101101) (55) (45) (2D) ;(00100000) (40) (32) (20) ;(11110101) (365) (245) (F5) ;(00000101) (5) (5) (05) ;(00100101) (45) (37) (25) ;(11110010) (362) (242) (F2) ;(11011000) (330) (216) (D8) ;(00000100) (4) (4) (04) ; -;1256;(00000110) (6) (6) (06) ;(00101111) (57) (47) (2F) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ; -;1264;(00000110) (6) (6) (06) ;(00110111) (67) (55) (37) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00000001) (1) (1) (01) ;(00001110) (16) (14) (0E) ; -;1272;(00111011) (73) (59) (3B) ;(00001000) (10) (8) (08) ;(01101111) (157) (111) (6F) ;(11000011) (303) (195) (C3) ;(00000111) (7) (7) (07) ;(00000101) (5) (5) (05) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ; -;1280;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ;(11011101) (335) (221) (DD) ;(01101110) (156) (110) (6E) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(10101101) (255) (173) (AD) ;(01100111) (147) (103) (67) ; -;1288;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(00110111) (67) (55) (37) ;(11000011) (303) (195) (C3) ;(00100101) (45) (37) (25) ;(00000101) (5) (5) (05) ;(01101100) (154) (108) (6C) ;(00011000) (30) (24) (18) ; -;1296;(11110100) (364) (244) (F4) ;(01111001) (171) (121) (79) ;(11001011) (313) (203) (CB) ;(01111000) (170) (120) (78) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(00110000) (60) (48) (30) ;(00000100) (4) (4) (04) ; -;1304;(00000110) (6) (6) (06) ;(01000010) (102) (66) (42) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00000110) (6) (6) (06) ;(00111110) (76) (62) (3E) ; -;1312;(00100000) (40) (32) (20) ;(11101111) (357) (239) (EF) ;(00000101) (5) (5) (05) ;(10101111) (257) (175) (AF) ;(00111100) (74) (60) (3C) ;(11001011) (313) (203) (CB) ;(00010101) (25) (21) (15) ;(11000010) (302) (194) (C2) ; -;1320;(00010100) (24) (20) (14) ;(00000101) (5) (5) (05) ;(00011011) (33) (27) (1B) ;(11011101) (335) (221) (DD) ;(00100011) (43) (35) (23) ;(00000110) (6) (6) (06) ;(00110001) (61) (49) (31) ;(00111110) (76) (62) (3E) ; -;1328;(01111111) (177) (127) (7F) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ;(00011111) (37) (31) (1F) ;(11010000) (320) (208) (D0) ;(01111010) (172) (122) (7A) ;(00111100) (74) (60) (3C) ;(11000010) (302) (194) (C2) ; -;1336;(11111110) (376) (254) (FE) ;(00000100) (4) (4) (04) ;(00000110) (6) (6) (06) ;(00111011) (73) (59) (3B) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ; -;1344;(00111010) (72) (58) (3A) ;(01001000) (110) (72) (48) ;(01011100) (134) (92) (5C) ;(11100110) (346) (230) (E6) ;(00111000) (70) (56) (38) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ; -;1352;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00111110) (76) (62) (3E) ;(01111111) (177) (127) (7F) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ;(00011111) (37) (31) (1F) ;(11111011) (373) (251) (FB) ; -;1360;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00001100) (14) (12) (0C) ;(11110001) (361) (241) (F1) ;(11001001) (311) (201) (C9) ;(00010100) (24) (20) (14) ;(00001000) (10) (8) (08) ; -;1368;(00010101) (25) (21) (15) ;(11110011) (363) (243) (F3) ;(00111110) (76) (62) (3E) ;(00001111) (17) (15) (0F) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00111111) (77) (63) (3F) ; -;1376;(00000101) (5) (5) (05) ;(11100101) (345) (229) (E5) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ;(00011111) (37) (31) (1F) ;(11100110) (346) (230) (E6) ;(00100000) (40) (32) (20) ;(11110110) (366) (246) (F6) ; -;1384;(00000010) (2) (2) (02) ;(01001111) (117) (79) (4F) ;(10111111) (277) (191) (BF) ;(11000000) (300) (192) (C0) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00000101) (5) (5) (05) ;(00110000) (60) (48) (30) ; -;1392;(11111010) (372) (250) (FA) ;(00100001) (41) (33) (21) ;(00010101) (25) (21) (15) ;(00000100) (4) (4) (04) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(00101011) (53) (43) (2B) ;(01111100) (174) (124) (7C) ; -;1400;(10110101) (265) (181) (B5) ;(00100000) (40) (32) (20) ;(11111001) (371) (249) (F9) ;(11001101) (315) (205) (CD) ;(11100011) (343) (227) (E3) ;(00000101) (5) (5) (05) ;(00110000) (60) (48) (30) ;(11101011) (353) (235) (EB) ; -;1408;(00000110) (6) (6) (06) ;(10011100) (234) (156) (9C) ;(11001101) (315) (205) (CD) ;(11100011) (343) (227) (E3) ;(00000101) (5) (5) (05) ;(00110000) (60) (48) (30) ;(11100100) (344) (228) (E4) ;(00111110) (76) (62) (3E) ; -;1416;(11000110) (306) (198) (C6) ;(10111000) (270) (184) (B8) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00100100) (44) (36) (24) ;(00100000) (40) (32) (20) ;(11110001) (361) (241) (F1) ;(00000110) (6) (6) (06) ; -;1424;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00000101) (5) (5) (05) ;(00110000) (60) (48) (30) ;(11010101) (325) (213) (D5) ;(01111000) (170) (120) (78) ;(11111110) (376) (254) (FE) ; -;1432;(11010100) (324) (212) (D4) ;(00110000) (60) (48) (30) ;(11110100) (364) (244) (F4) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00000101) (5) (5) (05) ;(11010000) (320) (208) (D0) ;(01111001) (171) (121) (79) ; -;1440;(11101110) (356) (238) (EE) ;(00000011) (3) (3) (03) ;(01001111) (117) (79) (4F) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(00000110) (6) (6) (06) ;(10110000) (260) (176) (B0) ;(00011000) (30) (24) (18) ; -;1448;(00011111) (37) (31) (1F) ;(00001000) (10) (8) (08) ;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(11011101) (335) (221) (DD) ;(01110101) (165) (117) (75) ; -;1456;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(00001111) (17) (15) (0F) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ;(10101101) (255) (173) (AD) ;(11000000) (300) (192) (C0) ;(01111001) (171) (121) (79) ; -;1464;(00011111) (37) (31) (1F) ;(01001111) (117) (79) (4F) ;(00010011) (23) (19) (13) ;(00011000) (30) (24) (18) ;(00000111) (7) (7) (07) ;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;1472;(10101101) (255) (173) (AD) ;(11000000) (300) (192) (C0) ;(11011101) (335) (221) (DD) ;(00100011) (43) (35) (23) ;(00011011) (33) (27) (1B) ;(00001000) (10) (8) (08) ;(00000110) (6) (6) (06) ;(10110010) (262) (178) (B2) ; -;1480;(00101110) (56) (46) (2E) ;(00000001) (1) (1) (01) ;(11001101) (315) (205) (CD) ;(11100011) (343) (227) (E3) ;(00000101) (5) (5) (05) ;(11010000) (320) (208) (D0) ;(00111110) (76) (62) (3E) ;(11001011) (313) (203) (CB) ; -;1488;(10111000) (270) (184) (B8) ;(11001011) (313) (203) (CB) ;(00010101) (25) (21) (15) ;(00000110) (6) (6) (06) ;(10110000) (260) (176) (B0) ;(11010010) (322) (210) (D2) ;(11001010) (312) (202) (CA) ;(00000101) (5) (5) (05) ; -;1496;(01111100) (174) (124) (7C) ;(10101101) (255) (173) (AD) ;(01100111) (147) (103) (67) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(00100000) (40) (32) (20) ;(11001010) (312) (202) (CA) ;(01111100) (174) (124) (7C) ; -;1504;(11111110) (376) (254) (FE) ;(00000001) (1) (1) (01) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00000101) (5) (5) (05) ;(11010000) (320) (208) (D0) ;(00111110) (76) (62) (3E) ; -;1512;(00010110) (26) (22) (16) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11111101) (375) (253) (FD) ;(10100111) (247) (167) (A7) ;(00000100) (4) (4) (04) ;(11001000) (310) (200) (C8) ;(00111110) (76) (62) (3E) ; -;1520;(01111111) (177) (127) (7F) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ;(00011111) (37) (31) (1F) ;(11010000) (320) (208) (D0) ;(10101001) (251) (169) (A9) ;(11100110) (346) (230) (E6) ;(00100000) (40) (32) (20) ; -;1528;(00101000) (50) (40) (28) ;(11110011) (363) (243) (F3) ;(01111001) (171) (121) (79) ;(00101111) (57) (47) (2F) ;(01001111) (117) (79) (4F) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(11110110) (366) (246) (F6) ; -;1536;(00001000) (10) (8) (08) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ;(11110001) (361) (241) (F1) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ; -;1544;(01011100) (134) (92) (5C) ;(11010110) (326) (214) (D6) ;(11100000) (340) (224) (E0) ;(00110010) (62) (50) (32) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10001100) (214) (140) (8C) ; -;1552;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00111100) (74) (60) (3C) ;(00000001) (1) (1) (01) ;(00010001) (21) (17) (11) ; -;1560;(00000000) (0) (0) (00) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(00001110) (16) (14) (0E) ; -;1568;(00100010) (42) (34) (22) ;(11110111) (367) (247) (F7) ;(11010101) (325) (213) (D5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00000110) (6) (6) (06) ;(00001011) (13) (11) (0B) ;(00111110) (76) (62) (3E) ; -;1576;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(00010011) (23) (19) (13) ;(00010000) (20) (16) (10) ;(11111100) (374) (252) (FC) ;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00000001) (1) (1) (01) ; -;1584;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(00100001) (41) (33) (21) ;(11110110) (366) (246) (F6) ;(11111111) (377) (255) (FF) ;(00001011) (13) (11) (0B) ; -;1592;(00001001) (11) (9) (09) ;(00000011) (3) (3) (03) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ; -;1600;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00001110) (16) (14) (0E) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ; -;1608;(00000001) (1) (1) (01) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ;(11100001) (341) (225) (E1) ;(00100011) (43) (35) (23) ;(11101011) (353) (235) (EB) ; -;1616;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(11100100) (344) (228) (E4) ;(00100000) (40) (32) (20) ;(01001001) (111) (73) (49) ;(00111010) (72) (58) (3A) ; -;1624;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ; -;1632;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101000) (50) (40) (28) ;(11001011) (313) (203) (CB) ;(11111001) (371) (249) (F9) ;(00110000) (60) (48) (30) ;(00001011) (13) (11) (0B) ;(00100001) (41) (33) (21) ; -;1640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(00111101) (75) (61) (3D) ;(00101000) (50) (40) (28) ;(00010101) (25) (21) (15) ; -;1648;(11001111) (317) (207) (CF) ;(00000001) (1) (1) (01) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00000100) (4) (4) (04) ; -;1656;(00101000) (50) (40) (28) ;(00011000) (30) (24) (18) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11011101) (335) (221) (DD) ;(01110111) (167) (119) (77) ;(00001011) (13) (11) (0B) ;(00100011) (43) (35) (23) ; -;1664;(01111110) (176) (126) (7E) ;(11011101) (335) (221) (DD) ;(01110111) (167) (119) (77) ;(00001100) (14) (12) (0C) ;(00100011) (43) (35) (23) ;(11011101) (335) (221) (DD) ;(01110001) (161) (113) (71) ;(00001110) (16) (14) (0E) ; -;1672;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(11001011) (313) (203) (CB) ;(01110001) (161) (113) (71) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(00111100) (74) (60) (3C) ;(11011101) (335) (221) (DD) ; -;1680;(01110111) (167) (119) (77) ;(00000000) (0) (0) (00) ;(11101011) (353) (235) (EB) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00100000) (40) (32) (20) ;(11011010) (332) (218) (DA) ; -;1688;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11101011) (353) (235) (EB) ;(11000011) (303) (195) (C3) ;(01011010) (132) (90) (5A) ;(00000111) (7) (7) (07) ; -;1696;(11111110) (376) (254) (FE) ;(10101010) (252) (170) (AA) ;(00100000) (40) (32) (20) ;(00011111) (37) (31) (1F) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ; -;1704;(00000011) (3) (3) (03) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ; -;1712;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00001011) (13) (11) (0B) ;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00001100) (14) (12) (0C) ;(00011011) (33) (27) (1B) ; -;1720;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11011101) (335) (221) (DD) ;(01110101) (165) (117) (75) ;(00001101) (15) (13) (0D) ;(11011101) (335) (221) (DD) ;(01110100) (164) (116) (74) ; -;1728;(00001110) (16) (14) (0E) ;(00011000) (30) (24) (18) ;(01001101) (115) (77) (4D) ;(11111110) (376) (254) (FE) ;(10101111) (257) (175) (AF) ;(00100000) (40) (32) (20) ;(01001111) (117) (79) (4F) ;(00111010) (72) (58) (3A) ; -;1736;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ; -;1744;(11001101) (315) (205) (CD) ;(01001000) (110) (72) (48) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00001100) (14) (12) (0C) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ; -;1752;(10100111) (247) (167) (A7) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11100110) (346) (230) (E6) ;(00011100) (34) (28) (1C) ;(00011000) (30) (24) (18) ; -;1760;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ; -;1768;(00001100) (14) (12) (0C) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;1776;(11001101) (315) (205) (CD) ;(11100110) (346) (230) (E6) ;(00011100) (34) (28) (1C) ;(00011000) (30) (24) (18) ;(00000100) (4) (4) (04) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ; -;1784;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(11011101) (335) (221) (DD) ; -;1792;(01110001) (161) (113) (71) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01110000) (160) (112) (70) ;(00001100) (14) (12) (0C) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ; -;1800;(11011101) (335) (221) (DD) ;(01110001) (161) (113) (71) ;(00001101) (15) (13) (0D) ;(11011101) (335) (221) (DD) ;(01110000) (160) (112) (70) ;(00001110) (16) (14) (0E) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ; -;1808;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(00011000) (30) (24) (18) ;(01000100) (104) (68) (44) ;(11111110) (376) (254) (FE) ;(11001010) (312) (202) (CA) ; -;1816;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00001110) (16) (14) (0E) ; -;1824;(10000000) (200) (128) (80) ;(00011000) (30) (24) (18) ;(00010111) (27) (23) (17) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11000010) (302) (194) (C2) ; -;1832;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ; -;1840;(00011011) (33) (27) (1B) ;(11001101) (315) (205) (CD) ;(10110111) (267) (183) (B7) ;(00111100) (74) (60) (3C) ;(11011101) (335) (221) (DD) ;(01110001) (161) (113) (71) ;(00001101) (15) (13) (0D) ;(11011101) (335) (221) (DD) ; -;1848;(01110000) (160) (112) (70) ;(00001110) (16) (14) (0E) ;(11011101) (335) (221) (DD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ; -;1856;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(00110111) (67) (55) (37) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;1864;(11011101) (335) (221) (DD) ;(01110101) (165) (117) (75) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01110100) (164) (116) (74) ;(00001100) (14) (12) (0C) ;(00101010) (52) (42) (2A) ;(01001011) (113) (75) (4B) ; -;1872;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11011101) (335) (221) (DD) ;(01110101) (165) (117) (75) ;(00001111) (17) (15) (0F) ;(11011101) (335) (221) (DD) ;(01110100) (164) (116) (74) ; -;1880;(00010000) (20) (16) (10) ;(11101011) (353) (235) (EB) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11001010) (312) (202) (CA) ;(01110000) (160) (112) (70) ; -;1888;(00001001) (11) (9) (09) ;(11100101) (345) (229) (E5) ;(00000001) (1) (1) (01) ;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(00001001) (11) (9) (09) ;(11011101) (335) (221) (DD) ; -;1896;(11100101) (345) (229) (E5) ;(00010001) (21) (17) (11) ;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(10101111) (257) (175) (AF) ;(00110111) (67) (55) (37) ;(11001101) (315) (205) (CD) ;(01010110) (126) (86) (56) ; -;1904;(00000101) (5) (5) (05) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00110000) (60) (48) (30) ;(11110010) (362) (242) (F2) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ; -;1912;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(01010010) (122) (82) (52) ;(00000011) (3) (3) (03) ;(00001110) (16) (14) (0E) ;(10000000) (200) (128) (80) ; -;1920;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(10111110) (276) (190) (BE) ;(11101111) (357) (239) (EF) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ; -;1928;(00001110) (16) (14) (0E) ;(11110110) (366) (246) (F6) ;(11111110) (376) (254) (FE) ;(00000100) (4) (4) (04) ;(00110000) (60) (48) (30) ;(11011001) (331) (217) (D9) ;(00010001) (21) (17) (11) ;(11000000) (300) (192) (C0) ; -;1936;(00001001) (11) (9) (09) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(11000001) (301) (193) (C1) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ; -;1944;(11010001) (321) (209) (D1) ;(00100001) (41) (33) (21) ;(11110000) (360) (240) (F0) ;(11111111) (377) (255) (FF) ;(00011001) (31) (25) (19) ;(00000110) (6) (6) (06) ;(00001010) (12) (10) (0A) ;(01111110) (176) (126) (7E) ; -;1952;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(01111001) (171) (121) (79) ;(10000000) (200) (128) (80) ;(01001111) (117) (79) (4F) ;(00010011) (23) (19) (13) ;(00011010) (32) (26) (1A) ; -;1960;(10111110) (276) (190) (BE) ;(00100011) (43) (35) (23) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00001100) (14) (12) (0C) ;(11010111) (327) (215) (D7) ;(00010000) (20) (16) (10) ;(11110110) (366) (246) (F6) ; -;1968;(11001011) (313) (203) (CB) ;(01111001) (171) (121) (79) ;(00100000) (40) (32) (20) ;(10110011) (263) (179) (B3) ;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ;(11010111) (327) (215) (D7) ;(11100001) (341) (225) (E1) ; -;1976;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ;(00111010) (72) (58) (3A) ; -;1984;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(00111101) (75) (61) (3D) ;(11001010) (312) (202) (CA) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ; -;1992;(11001010) (312) (202) (CA) ;(10110110) (266) (182) (B6) ;(00001000) (10) (8) (08) ;(11100101) (345) (229) (E5) ;(11011101) (335) (221) (DD) ;(01101110) (156) (110) (6E) ;(11111010) (372) (250) (FA) ;(11011101) (335) (221) (DD) ; -;2000;(01100110) (146) (102) (66) ;(11111011) (373) (251) (FB) ;(11011101) (335) (221) (DD) ;(01011110) (136) (94) (5E) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01010110) (126) (86) (56) ;(00001100) (14) (12) (0C) ; -;2008;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00111000) (70) (56) (38) ;(00100110) (46) (38) (26) ; -;2016;(00101000) (50) (40) (28) ;(00000111) (7) (7) (07) ;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ;(00100000) (40) (32) (20) ; -;2024;(00011101) (35) (29) (1D) ;(11100001) (341) (225) (E1) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11011101) (335) (221) (DD) ;(01101110) (156) (110) (6E) ; -;2032;(00001101) (15) (13) (0D) ;(11011101) (335) (221) (DD) ;(01100110) (146) (102) (66) ;(00001110) (16) (14) (0E) ;(11100101) (345) (229) (E5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00111010) (72) (58) (3A) ; -;2040;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ;(00110111) (67) (55) (37) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(10100111) (247) (167) (A7) ; -;2048;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(01010110) (126) (86) (56) ;(00000101) (5) (5) (05) ;(11011000) (330) (216) (D8) ;(11001111) (317) (207) (CF) ;(00011010) (32) (26) (1A) ; -;2056;(11011101) (335) (221) (DD) ;(01011110) (136) (94) (5E) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01010110) (126) (86) (56) ;(00001100) (14) (12) (0C) ;(11100101) (345) (229) (E5) ;(01111100) (174) (124) (7C) ; -;2064;(10110101) (265) (181) (B5) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(00010011) (23) (19) (13) ;(00010011) (23) (19) (13) ;(00010011) (23) (19) (13) ;(11101011) (353) (235) (EB) ;(00011000) (30) (24) (18) ; -;2072;(00001100) (14) (12) (0C) ;(11011101) (335) (221) (DD) ;(01101110) (156) (110) (6E) ;(11111010) (372) (250) (FA) ;(11011101) (335) (221) (DD) ;(01100110) (146) (102) (66) ;(11111011) (373) (251) (FB) ;(11101011) (353) (235) (EB) ; -;2080;(00110111) (67) (55) (37) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00111000) (70) (56) (38) ;(00001001) (11) (9) (09) ;(00010001) (21) (17) (11) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ; -;2088;(00011001) (31) (25) (19) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11001101) (315) (205) (CD) ;(00000101) (5) (5) (05) ;(00011111) (37) (31) (1F) ;(11100001) (341) (225) (E1) ;(11011101) (335) (221) (DD) ; -;2096;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00111110) (76) (62) (3E) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00101000) (50) (40) (28) ; -;2104;(00010011) (23) (19) (13) ;(00101011) (53) (43) (2B) ;(01000110) (106) (70) (46) ;(00101011) (53) (43) (2B) ;(01001110) (116) (78) (4E) ;(00101011) (53) (43) (2B) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ; -;2112;(00000011) (3) (3) (03) ;(11011101) (335) (221) (DD) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ; -;2120;(11011101) (335) (221) (DD) ;(00101010) (52) (42) (2A) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;2128;(11011101) (335) (221) (DD) ;(01001110) (116) (78) (4E) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01000110) (106) (70) (46) ;(00001100) (14) (12) (0C) ;(11000101) (305) (197) (C5) ;(00000011) (3) (3) (03) ; -;2136;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(11111101) (375) (253) (FD) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ; -;2144;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(11110001) (361) (241) (F1) ;(01110111) (167) (119) (77) ;(11010001) (321) (209) (D1) ;(00100011) (43) (35) (23) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ; -;2152;(01110010) (162) (114) (72) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00110111) (67) (55) (37) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ; -;2160;(11000011) (303) (195) (C3) ;(00000010) (2) (2) (02) ;(00001000) (10) (8) (08) ;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;2168;(11011101) (335) (221) (DD) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11011101) (335) (221) (DD) ;(01001110) (116) (78) (4E) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ; -;2176;(01000110) (106) (70) (46) ;(00001100) (14) (12) (0C) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(11100101) (345) (229) (E5) ; -;2184;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(11011101) (335) (221) (DD) ;(00101010) (52) (42) (2A) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ; -;2192;(00100011) (43) (35) (23) ;(11011101) (335) (221) (DD) ;(01001110) (116) (78) (4E) ;(00001111) (17) (15) (0F) ;(11011101) (335) (221) (DD) ;(01000110) (106) (70) (46) ;(00010000) (20) (16) (10) ;(00001001) (11) (9) (09) ; -;2200;(00100010) (42) (34) (22) ;(01001011) (113) (75) (4B) ;(01011100) (134) (92) (5C) ;(11011101) (335) (221) (DD) ;(01100110) (146) (102) (66) ;(00001110) (16) (14) (0E) ;(01111100) (174) (124) (7C) ;(11100110) (346) (230) (E6) ; -;2208;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00001010) (12) (10) (0A) ;(11011101) (335) (221) (DD) ;(01101110) (156) (110) (6E) ;(00001101) (15) (13) (0D) ;(00100010) (42) (34) (22) ;(01000010) (102) (66) (42) ; -;2216;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ;(11010001) (321) (209) (D1) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ; -;2224;(00110111) (67) (55) (37) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11000011) (303) (195) (C3) ;(00000010) (2) (2) (02) ;(00001000) (10) (8) (08) ;(11011101) (335) (221) (DD) ;(01001110) (116) (78) (4E) ; -;2232;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ;(01000110) (106) (70) (46) ;(00001100) (14) (12) (0C) ;(11000101) (305) (197) (C5) ;(00000011) (3) (3) (03) ;(11110111) (367) (247) (F7) ;(00110110) (66) (54) (36) ; -;2240;(10000000) (200) (128) (80) ;(11101011) (353) (235) (EB) ;(11010001) (321) (209) (D1) ;(11100101) (345) (229) (E5) ;(11100101) (345) (229) (E5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00110111) (67) (55) (37) ; -;2248;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(00000010) (2) (2) (02) ;(00001000) (10) (8) (08) ;(11100001) (341) (225) (E1) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ; -;2256;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00011001) (31) (25) (19) ;(00011010) (32) (26) (1A) ; -;2264;(00010011) (23) (19) (13) ;(10111110) (276) (190) (BE) ;(00100011) (43) (35) (23) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00011010) (32) (26) (1A) ;(10111110) (276) (190) (BE) ;(00011011) (33) (27) (1B) ; -;2272;(00101011) (53) (43) (2B) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(11100101) (345) (229) (E5) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ; -;2280;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ;(11101100) (354) (236) (EC) ;(11001101) (315) (205) (CD) ;(00101100) (54) (44) (2C) ;(00001001) (11) (9) (09) ;(00011000) (30) (24) (18) ;(11100010) (342) (226) (E2) ; -;2288;(01111110) (176) (126) (7E) ;(01001111) (117) (79) (4F) ;(11111110) (376) (254) (FE) ;(10000000) (200) (128) (80) ;(11001000) (310) (200) (C8) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01001011) (113) (75) (4B) ; -;2296;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(10000000) (200) (128) (80) ;(00101000) (50) (40) (28) ;(00100101) (45) (37) (25) ;(10111001) (271) (185) (B9) ;(00101000) (50) (40) (28) ; -;2304;(00001000) (10) (8) (08) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(11101011) (353) (235) (EB) ;(00011000) (30) (24) (18) ; -;2312;(11110000) (360) (240) (F0) ;(11100110) (346) (230) (E6) ;(11100000) (340) (224) (E0) ;(11111110) (376) (254) (FE) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(11010001) (321) (209) (D1) ; -;2320;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(00100011) (43) (35) (23) ;(00010011) (23) (19) (13) ;(00011010) (32) (26) (1A) ;(10111110) (276) (190) (BE) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ; -;2328;(00010111) (27) (23) (17) ;(00110000) (60) (48) (30) ;(11110111) (367) (247) (F7) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ; -;2336;(11100000) (340) (224) (E0) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11010001) (321) (209) (D1) ;(11101011) (353) (235) (EB) ;(00111100) (74) (60) (3C) ;(00110111) (67) (55) (37) ;(11001101) (315) (205) (CD) ; -;2344;(00101100) (54) (44) (2C) ;(00001001) (11) (9) (09) ;(00011000) (30) (24) (18) ;(11000100) (304) (196) (C4) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00001000) (10) (8) (08) ;(00100010) (42) (34) (22) ; -;2352;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(11101000) (350) (232) (E8) ; -;2360;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(11010101) (325) (213) (D5) ; -;2368;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01010011) (123) (83) (53) ; -;2376;(01011100) (134) (92) (5C) ;(11100011) (343) (227) (E3) ;(11000101) (305) (197) (C5) ;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00000111) (7) (7) (07) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ; -;2384;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ; -;2392;(00100011) (43) (35) (23) ;(11000001) (301) (193) (C1) ;(11010001) (321) (209) (D1) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ; -;2400;(01011011) (133) (91) (5B) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11000101) (305) (197) (C5) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ; -;2408;(11100001) (341) (225) (E1) ;(11000001) (301) (193) (C1) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ; -;2416;(11100101) (345) (229) (E5) ;(00111110) (76) (62) (3E) ;(11111101) (375) (253) (FD) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ; -;2424;(10100001) (241) (161) (A1) ;(00001001) (11) (9) (09) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ; -;2432;(11101110) (356) (238) (EE) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00111100) (74) (60) (3C) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ;(00010001) (21) (17) (11) ;(00010001) (21) (17) (11) ; -;2440;(00000000) (0) (0) (00) ;(10101111) (257) (175) (AF) ;(11001101) (315) (205) (CD) ;(11000010) (302) (194) (C2) ;(00000100) (4) (4) (04) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00000110) (6) (6) (06) ; -;2448;(00110010) (62) (50) (32) ;(01110110) (166) (118) (76) ;(00010000) (20) (16) (10) ;(11111101) (375) (253) (FD) ;(11011101) (335) (221) (DD) ;(01011110) (136) (94) (5E) ;(00001011) (13) (11) (0B) ;(11011101) (335) (221) (DD) ; -;2456;(01010110) (126) (86) (56) ;(00001100) (14) (12) (0C) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(11000011) (303) (195) (C3) ;(11000010) (302) (194) (C2) ; -;2464;(00000100) (4) (4) (04) ;(10000000) (200) (128) (80) ;(01010011) (123) (83) (53) ;(01110100) (164) (116) (74) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ; -;2472;(01110100) (164) (116) (74) ;(01100001) (141) (97) (61) ;(01110000) (160) (112) (70) ;(01100101) (145) (101) (65) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(01110100) (164) (116) (74) ;(01101000) (150) (104) (68) ; -;2480;(01100101) (145) (101) (65) ;(01101110) (156) (110) (6E) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01110011) (163) (115) (73) ;(01110011) (163) (115) (73) ; -;2488;(00100000) (40) (32) (20) ;(01100001) (141) (97) (61) ;(01101110) (156) (110) (6E) ;(01111001) (171) (121) (79) ;(00100000) (40) (32) (20) ;(01101011) (153) (107) (6B) ;(01100101) (145) (101) (65) ;(01111001) (171) (121) (79) ; -;2496;(10101110) (256) (174) (AE) ;(00001101) (15) (13) (0D) ;(01010000) (120) (80) (50) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(01100111) (147) (103) (67) ;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ; -;2504;(01101101) (155) (109) (6D) ;(00111010) (72) (58) (3A) ;(10100000) (240) (160) (A0) ;(00001101) (15) (13) (0D) ;(01001110) (116) (78) (4E) ;(01110101) (165) (117) (75) ;(01101101) (155) (109) (6D) ;(01100010) (142) (98) (62) ; -;2512;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ;(01111001) (171) (121) (79) ; -;2520;(00111010) (72) (58) (3A) ;(10100000) (240) (160) (A0) ;(00001101) (15) (13) (0D) ;(01000011) (103) (67) (43) ;(01101000) (150) (104) (68) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ; -;2528;(01100011) (143) (99) (63) ;(01110100) (164) (116) (74) ;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01110010) (162) (114) (72) ; -;2536;(01100001) (141) (97) (61) ;(01111001) (171) (121) (79) ;(00111010) (72) (58) (3A) ;(10100000) (240) (160) (A0) ;(00001101) (15) (13) (0D) ;(01000010) (102) (66) (42) ;(01111001) (171) (121) (79) ;(01110100) (164) (116) (74) ; -;2544;(01100101) (145) (101) (65) ;(01110011) (163) (115) (73) ;(00111010) (72) (58) (3A) ;(10100000) (240) (160) (A0) ;(11001101) (315) (205) (CD) ;(00000011) (3) (3) (03) ;(00001011) (13) (11) (0B) ;(11111110) (376) (254) (FE) ; -;2552;(00100000) (40) (32) (20) ;(11010010) (322) (210) (D2) ;(11011001) (331) (217) (D9) ;(00001010) (12) (10) (0A) ;(11111110) (376) (254) (FE) ;(00000110) (6) (6) (06) ;(00111000) (70) (56) (38) ;(01101001) (151) (105) (69) ; -;2560;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(00110000) (60) (48) (30) ;(01100101) (145) (101) (65) ;(00100001) (41) (33) (21) ;(00001011) (13) (11) (0B) ;(00001010) (12) (10) (0A) ;(01011111) (137) (95) (5F) ; -;2568;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(01011110) (136) (94) (5E) ;(00011001) (31) (25) (19) ;(11100101) (345) (229) (E5) ;(11000011) (303) (195) (C3) ;(00000011) (3) (3) (03) ; -;2576;(00001011) (13) (11) (0B) ;(01001110) (116) (78) (4E) ;(01010111) (127) (87) (57) ;(00010000) (20) (16) (10) ;(00101001) (51) (41) (29) ;(01010100) (124) (84) (54) ;(01010011) (123) (83) (53) ;(01010010) (122) (82) (52) ; -;2584;(00110111) (67) (55) (37) ;(01010000) (120) (80) (50) ;(01001111) (117) (79) (4F) ;(01011111) (137) (95) (5F) ;(01011110) (136) (94) (5E) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(01011011) (133) (91) (5B) ; -;2592;(01011010) (132) (90) (5A) ;(01010100) (124) (84) (54) ;(01010011) (123) (83) (53) ;(00001100) (14) (12) (0C) ;(00111110) (76) (62) (3E) ;(00100010) (42) (34) (22) ;(10111001) (271) (185) (B9) ;(00100000) (40) (32) (20) ; -;2600;(00010001) (21) (17) (11) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(00001001) (11) (9) (09) ;(00000100) (4) (4) (04) ; -;2608;(00001110) (16) (14) (0E) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(00011001) (31) (25) (19) ;(10111000) (270) (184) (B8) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(00000101) (5) (5) (05) ; -;2616;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(11000011) (303) (195) (C3) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(00111010) (72) (58) (3A) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ; -;2624;(11110101) (365) (245) (F5) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(01010111) (127) (87) (57) ;(00000001) (1) (1) (01) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(11001101) (315) (205) (CD) ; -;2632;(11011001) (331) (217) (D9) ;(00001010) (12) (10) (0A) ;(11110001) (361) (241) (F1) ;(00110010) (62) (50) (32) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ; -;2640;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(11000010) (302) (194) (C2) ;(11001101) (315) (205) (CD) ;(00001110) (16) (14) (0E) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ; -;2648;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00001100) (14) (12) (0C) ;(00000101) (5) (5) (05) ;(11000011) (303) (195) (C3) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ; -;2656;(00000011) (3) (3) (03) ;(00001011) (13) (11) (0B) ;(01111001) (171) (121) (79) ;(00111101) (75) (61) (3D) ;(00111101) (75) (61) (3D) ;(11100110) (346) (230) (E6) ;(00010000) (20) (16) (10) ;(00011000) (30) (24) (18) ; -;2664;(01011010) (132) (90) (5A) ;(00111110) (76) (62) (3E) ;(00111111) (77) (63) (3F) ;(00011000) (30) (24) (18) ;(01101100) (154) (108) (6C) ;(00010001) (21) (17) (11) ;(10000111) (207) (135) (87) ;(00001010) (12) (10) (0A) ; -;2672;(00110010) (62) (50) (32) ;(00001111) (17) (15) (0F) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00001011) (13) (11) (0B) ;(00010001) (21) (17) (11) ;(01101101) (155) (109) (6D) ;(00001010) (12) (10) (0A) ; -;2680;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(00010001) (21) (17) (11) ;(10000111) (207) (135) (87) ;(00001010) (12) (10) (0A) ;(00110010) (62) (50) (32) ;(00001110) (16) (14) (0E) ;(01011100) (134) (92) (5C) ; -;2688;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(11001001) (311) (201) (C9) ;(00010001) (21) (17) (11) ; -;2696;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00001010) (12) (10) (0A) ;(00101010) (52) (42) (2A) ;(00001110) (16) (14) (0E) ;(01011100) (134) (92) (5C) ; -;2704;(01010111) (127) (87) (57) ;(01111101) (175) (125) (7D) ;(11111110) (376) (254) (FE) ;(00010110) (26) (22) (16) ;(11011010) (332) (218) (DA) ;(00010001) (21) (17) (11) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ; -;2712;(00101001) (51) (41) (29) ;(01000100) (104) (68) (44) ;(01001010) (112) (74) (4A) ;(00111110) (76) (62) (3E) ;(00011111) (37) (31) (1F) ;(10010001) (221) (145) (91) ;(00111000) (70) (56) (38) ;(00001100) (14) (12) (0C) ; -;2720;(11000110) (306) (198) (C6) ;(00000010) (2) (2) (02) ;(01001111) (117) (79) (4F) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ; -;2728;(00010110) (26) (22) (16) ;(00111110) (76) (62) (3E) ;(00010110) (26) (22) (16) ;(10010000) (220) (144) (90) ;(11011010) (332) (218) (DA) ;(10011111) (237) (159) (9F) ;(00011110) (36) (30) (1E) ;(00111100) (74) (60) (3C) ; -;2736;(01000111) (107) (71) (47) ;(00000100) (4) (4) (04) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(11000010) (302) (194) (C2) ;(01010101) (125) (85) (55) ; -;2744;(00001100) (14) (12) (0C) ;(11111101) (375) (253) (FD) ;(10111110) (276) (190) (BE) ;(00110001) (61) (49) (31) ;(11011010) (332) (218) (DA) ;(10000110) (206) (134) (86) ;(00001100) (14) (12) (0C) ;(11000011) (303) (195) (C3) ; -;2752;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(01111100) (174) (124) (7C) ;(11001101) (315) (205) (CD) ;(00000011) (3) (3) (03) ;(00001011) (13) (11) (0B) ;(10000001) (201) (129) (81) ;(00111101) (75) (61) (3D) ; -;2760;(11100110) (346) (230) (E6) ;(00011111) (37) (31) (1F) ;(11001000) (310) (200) (C8) ;(01010111) (127) (87) (57) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11000110) (306) (198) (C6) ; -;2768;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00001100) (14) (12) (0C) ;(00010101) (25) (21) (15) ;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ; -;2776;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00100100) (44) (36) (24) ;(00001011) (13) (11) (0B) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ; -;2784;(00100000) (40) (32) (20) ;(00011010) (32) (26) (1A) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(00100000) (40) (32) (20) ;(00001000) (10) (8) (08) ; -;2792;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(10001000) (210) (136) (88) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(10000100) (204) (132) (84) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ; -;2800;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(10001010) (212) (138) (8A) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(10000010) (202) (130) (82) ;(01011100) (134) (92) (5C) ; -;2808;(00100010) (42) (34) (22) ;(10000110) (206) (134) (86) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(01110001) (161) (113) (71) ;(01000101) (105) (69) (45) ;(00100010) (42) (34) (22) ; -;2816;(10000000) (200) (128) (80) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ; -;2824;(00010100) (24) (20) (14) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10001000) (210) (136) (88) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(10000100) (204) (132) (84) ;(01011100) (134) (92) (5C) ; -;2832;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(11001000) (310) (200) (C8) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10001010) (212) (138) (8A) ; -;2840;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(10000110) (206) (134) (86) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(01000101) (105) (69) (45) ; -;2848;(00101010) (52) (42) (2A) ;(10000000) (200) (128) (80) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ;(10000000) (200) (128) (80) ;(00111000) (70) (56) (38) ;(00111101) (75) (61) (3D) ; -;2856;(11111110) (376) (254) (FE) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00100110) (46) (38) (26) ;(01000111) (107) (71) (47) ;(11001101) (315) (205) (CD) ;(00111000) (70) (56) (38) ;(00001011) (13) (11) (0B) ; -;2864;(11001101) (315) (205) (CD) ;(00000011) (3) (3) (03) ;(00001011) (13) (11) (0B) ;(00010001) (21) (17) (11) ;(10010010) (222) (146) (92) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(01000111) (107) (71) (47) ; -;2872;(00100001) (41) (33) (21) ;(10010010) (222) (146) (92) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00111110) (76) (62) (3E) ;(00001011) (13) (11) (0B) ;(11001011) (313) (203) (CB) ;(00011000) (30) (24) (18) ; -;2880;(10011111) (237) (159) (9F) ;(11100110) (346) (230) (E6) ;(00001111) (17) (15) (0F) ;(01001111) (117) (79) (4F) ;(11001011) (313) (203) (CB) ;(00011000) (30) (24) (18) ;(10011111) (237) (159) (9F) ;(11100110) (346) (230) (E6) ; -;2888;(11110000) (360) (240) (F0) ;(10110001) (261) (177) (B1) ;(00001110) (16) (14) (0E) ;(00000100) (4) (4) (04) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ; -;2896;(11111011) (373) (251) (FB) ;(11001001) (311) (201) (C9) ;(11010110) (326) (214) (D6) ;(10100101) (245) (165) (A5) ;(00110000) (60) (48) (30) ;(00001001) (11) (9) (09) ;(11000110) (306) (198) (C6) ;(00010101) (25) (21) (15) ; -;2904;(11000101) (305) (197) (C5) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01111011) (173) (123) (7B) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00001011) (13) (11) (0B) ;(11001101) (315) (205) (CD) ; -;2912;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(11000011) (303) (195) (C3) ;(00000011) (3) (3) (03) ;(00001011) (13) (11) (0B) ;(11000101) (305) (197) (C5) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ; -;2920;(00110110) (66) (54) (36) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10000110) (206) (134) (86) ; -;2928;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(11000110) (306) (198) (C6) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ; -;2936;(01101111) (157) (111) (6F) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00001001) (11) (9) (09) ;(11000001) (301) (193) (C1) ;(11101011) (353) (235) (EB) ;(01111001) (171) (121) (79) ; -;2944;(00111101) (75) (61) (3D) ;(00111110) (76) (62) (3E) ;(00100001) (41) (33) (21) ;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ;(00000101) (5) (5) (05) ;(01001111) (117) (79) (4F) ;(11111101) (375) (253) (FD) ; -;2952;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11001101) (315) (205) (CD) ; -;2960;(00001110) (16) (14) (0E) ;(11010001) (321) (209) (D1) ;(01111001) (171) (121) (79) ;(10111001) (271) (185) (B9) ;(11010101) (325) (213) (D5) ;(11001100) (314) (204) (CC) ;(01010101) (125) (85) (55) ;(00001100) (14) (12) (0C) ; -;2968;(11010001) (321) (209) (D1) ;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(00111010) (72) (58) (3A) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(00000110) (6) (6) (06) ;(11111111) (377) (255) (FF) ; -;2976;(00011111) (37) (31) (1F) ;(00111000) (70) (56) (38) ;(00000001) (1) (1) (01) ;(00000100) (4) (4) (04) ;(00011111) (37) (31) (1F) ;(00011111) (37) (31) (1F) ;(10011111) (237) (159) (9F) ;(01001111) (117) (79) (4F) ; -;2984;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(10100111) (247) (167) (A7) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(00101000) (50) (40) (28) ; -;2992;(00000101) (5) (5) (05) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(11001110) (316) (206) (CE) ;(00110111) (67) (55) (37) ;(11101011) (353) (235) (EB) ;(00001000) (10) (8) (08) ; -;3000;(00011010) (32) (26) (1A) ;(10100000) (240) (160) (A0) ;(10101110) (256) (174) (AE) ;(10101001) (251) (169) (A9) ;(00010010) (22) (18) (12) ;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00010011) (23) (19) (13) ; -;3008;(00010100) (24) (20) (14) ;(00100011) (43) (35) (23) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11110010) (362) (242) (F2) ;(11101011) (353) (235) (EB) ;(00100101) (45) (37) (25) ;(11111101) (375) (253) (FD) ; -;3016;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ;(11001100) (314) (204) (CC) ;(11011011) (333) (219) (DB) ;(00001011) (13) (11) (0B) ;(11100001) (341) (225) (E1) ;(11000001) (301) (193) (C1) ; -;3024;(00001101) (15) (13) (0D) ;(00100011) (43) (35) (23) ;(11001001) (311) (201) (C9) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(10000011) (203) (131) (83) ;(01011111) (137) (95) (5F) ; -;3032;(00001000) (10) (8) (08) ;(00011000) (30) (24) (18) ;(11100110) (346) (230) (E6) ;(01111100) (174) (124) (7C) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(11100110) (346) (230) (E6) ; -;3040;(00000011) (3) (3) (03) ;(11110110) (366) (246) (F6) ;(01011000) (130) (88) (58) ;(01100111) (147) (103) (67) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ; -;3048;(01111110) (176) (126) (7E) ;(10101011) (253) (171) (AB) ;(10100010) (242) (162) (A2) ;(10101011) (253) (171) (AB) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ;(01110110) (166) (118) (76) ; -;3056;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(11100110) (346) (230) (E6) ;(11000111) (307) (199) (C7) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ; -;3064;(11101110) (356) (238) (EE) ;(00111000) (70) (56) (38) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ;(01100110) (146) (102) (66) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ; -;3072;(11100110) (346) (230) (E6) ;(11111000) (370) (248) (F8) ;(11001011) (313) (203) (CB) ;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11101110) (356) (238) (EE) ;(00000111) (7) (7) (07) ; -;3080;(01110111) (167) (119) (77) ;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(11100011) (343) (227) (E3) ;(00011000) (30) (24) (18) ;(00000100) (4) (4) (04) ; -;3088;(00010001) (21) (17) (11) ;(10010101) (225) (149) (95) ;(00000000) (0) (0) (00) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(01000001) (101) (65) (41) ;(00001100) (14) (12) (0C) ;(00111000) (70) (56) (38) ; -;3096;(00001001) (11) (9) (09) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01000110) (106) (70) (46) ;(11001100) (314) (204) (CC) ; -;3104;(00111011) (73) (59) (3B) ;(00001100) (14) (12) (0C) ;(00011010) (32) (26) (1A) ;(11100110) (346) (230) (E6) ;(01111111) (177) (127) (7F) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00001100) (14) (12) (0C) ; -;3112;(00011010) (32) (26) (1A) ;(00010011) (23) (19) (13) ;(10000111) (207) (135) (87) ;(00110000) (60) (48) (30) ;(11110101) (365) (245) (F5) ;(11010001) (321) (209) (D1) ;(11111110) (376) (254) (FE) ;(01001000) (110) (72) (48) ; -;3120;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(11111110) (376) (254) (FE) ;(10000010) (202) (130) (82) ;(11011000) (330) (216) (D8) ;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ; -;3128;(11011000) (330) (216) (D8) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ;(11010111) (327) (215) (D7) ;(11011001) (331) (217) (D9) ;(11010001) (321) (209) (D1) ; -;3136;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11101011) (353) (235) (EB) ;(00111100) (74) (60) (3C) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(00101000) (50) (40) (28) ; -;3144;(11111011) (373) (251) (FB) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ;(11101011) (353) (235) (EB) ;(11110001) (361) (241) (F1) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ; -;3152;(11011000) (330) (216) (D8) ;(00011010) (32) (26) (1A) ;(11010110) (326) (214) (D6) ;(01000001) (101) (65) (41) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;3160;(01001110) (116) (78) (4E) ;(11000000) (300) (192) (C0) ;(00010001) (21) (17) (11) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(11010101) (325) (213) (D5) ;(01111000) (170) (120) (78) ;(11111101) (375) (253) (FD) ; -;3168;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(00001101) (15) (13) (0D) ;(11111101) (375) (253) (FD) ;(10111110) (276) (190) (BE) ; -;3176;(00110001) (61) (49) (31) ;(00111000) (70) (56) (38) ;(00011011) (33) (27) (1B) ;(11000000) (300) (192) (C0) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01100110) (146) (102) (66) ; -;3184;(00101000) (50) (40) (28) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(01011110) (136) (94) (5E) ;(00101101) (55) (45) (2D) ;(00011101) (35) (29) (1D) ;(00101000) (50) (40) (28) ;(01011010) (132) (90) (5A) ; -;3192;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11101101) (355) (237) (ED) ;(01111011) (173) (123) (7B) ;(00111111) (77) (63) (3F) ; -;3200;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10100110) (246) (166) (A6) ;(11001001) (311) (201) (C9) ;(11001111) (317) (207) (CF) ;(00000100) (4) (4) (04) ; -;3208;(11111101) (375) (253) (FD) ;(00110101) (65) (53) (35) ;(01010010) (122) (82) (52) ;(00100000) (40) (32) (20) ;(01000101) (105) (69) (45) ;(00111110) (76) (62) (3E) ;(00011000) (30) (24) (18) ;(10010000) (220) (144) (90) ; -;3216;(00110010) (62) (50) (32) ;(10001100) (214) (140) (8C) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00111010) (72) (58) (3A) ; -;3224;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(11110101) (365) (245) (F5) ;(00111110) (76) (62) (3E) ;(11111101) (375) (253) (FD) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ; -;3232;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ;(11111000) (370) (248) (F8) ;(00001100) (14) (12) (0C) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(11111101) (375) (253) (FD) ; -;3240;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11101110) (356) (238) (EE) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(11011110) (336) (222) (DE) ; -;3248;(11001011) (313) (203) (CB) ;(10101110) (256) (174) (AE) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(11100111) (347) (231) (E7) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ; -;3256;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(01000101) (105) (69) (45) ;(11111110) (376) (254) (FE) ;(11100010) (342) (226) (E2) ;(00101000) (50) (40) (28) ;(01000001) (101) (65) (41) ;(11110110) (366) (246) (F6) ; -;3264;(00100000) (40) (32) (20) ;(11111110) (376) (254) (FE) ;(01101110) (156) (110) (6E) ;(00101000) (50) (40) (28) ;(00111011) (73) (59) (3B) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ; -;3272;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11110001) (361) (241) (F1) ;(00110010) (62) (50) (32) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ; -;3280;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11111101) (375) (253) (FD) ;(01000110) (106) (70) (46) ;(00110001) (61) (49) (31) ; -;3288;(00000100) (4) (4) (04) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00001110) (16) (14) (0E) ;(01111100) (174) (124) (7C) ; -;3296;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(11100110) (346) (230) (E6) ;(00000011) (3) (3) (03) ;(11110110) (366) (246) (F6) ;(01011000) (130) (88) (58) ;(01100111) (147) (103) (67) ; -;3304;(00010001) (21) (17) (11) ;(11100000) (340) (224) (E0) ;(01011010) (132) (90) (5A) ;(00011010) (32) (26) (1A) ;(01001110) (116) (78) (4E) ;(00000110) (6) (6) (06) ;(00100000) (40) (32) (20) ;(11101011) (353) (235) (EB) ; -;3312;(00010010) (22) (18) (12) ;(01110001) (161) (113) (71) ;(00010011) (23) (19) (13) ;(00100011) (43) (35) (23) ;(00010000) (20) (16) (10) ;(11111010) (372) (250) (FA) ;(11000001) (301) (193) (C1) ;(11001001) (311) (201) (C9) ; -;3320;(10000000) (200) (128) (80) ;(01110011) (163) (115) (73) ;(01100011) (143) (99) (63) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(01101100) (154) (108) (6C) ;(01101100) (154) (108) (6C) ;(10111111) (277) (191) (BF) ; -;3328;(11001111) (317) (207) (CF) ;(00001100) (14) (12) (0C) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(10000000) (200) (128) (80) ;(11111101) (375) (253) (FD) ;(10000110) (206) (134) (86) ; -;3336;(00110001) (61) (49) (31) ;(11010110) (326) (214) (D6) ;(00011001) (31) (25) (19) ;(11010000) (320) (208) (D0) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(11000101) (305) (197) (C5) ;(01000111) (107) (71) (47) ; -;3344;(00101010) (52) (42) (2A) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ; -;3352;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ;(01111000) (170) (120) (78) ;(11110101) (365) (245) (F5) ;(00100001) (41) (33) (21) ;(01101011) (153) (107) (6B) ;(01011100) (134) (92) (5C) ; -;3360;(01000110) (106) (70) (46) ;(01111000) (170) (120) (78) ;(00111100) (74) (60) (3C) ;(01110111) (167) (119) (77) ;(00100001) (41) (33) (21) ;(10001001) (211) (137) (89) ;(01011100) (134) (92) (5C) ;(10111110) (276) (190) (BE) ; -;3368;(00111000) (70) (56) (38) ;(00000011) (3) (3) (03) ;(00110100) (64) (52) (34) ;(00000110) (6) (6) (06) ;(00010111) (27) (23) (17) ;(11001101) (315) (205) (CD) ;(00000000) (0) (0) (00) ;(00001110) (16) (14) (0E) ; -;3376;(11110001) (361) (241) (F1) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11101000) (350) (232) (E8) ;(11100001) (341) (225) (E1) ;(11111101) (375) (253) (FD) ;(01110101) (165) (117) (75) ;(01010111) (127) (87) (57) ; -;3384;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10001000) (210) (136) (88) ;(01011100) (134) (92) (5C) ; -;3392;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10000110) (206) (134) (86) ;(11001101) (315) (205) (CD) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(11111101) (375) (253) (FD) ; -;3400;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11000110) (306) (198) (C6) ;(11000001) (301) (193) (C1) ;(11001001) (311) (201) (C9) ;(10101111) (257) (175) (AF) ;(00101010) (52) (42) (2A) ;(10001101) (215) (141) (8D) ; -;3408;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(01100111) (147) (103) (67) ; -;3416;(11111101) (375) (253) (FD) ;(01101110) (156) (110) (6E) ;(00001110) (16) (14) (0E) ;(00100010) (42) (34) (22) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(10010001) (221) (145) (91) ; -;3424;(01011100) (134) (92) (5C) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(01111110) (176) (126) (7E) ;(00001111) (17) (15) (0F) ;(10101110) (256) (174) (AE) ;(11100110) (346) (230) (E6) ;(01010101) (125) (85) (55) ; -;3432;(10101110) (256) (174) (AE) ;(01110111) (167) (119) (77) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10101111) (257) (175) (AF) ;(00001101) (15) (13) (0D) ;(00100001) (41) (33) (21) ;(00111100) (74) (60) (3C) ; -;3440;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10101110) (256) (174) (AE) ;(11001011) (313) (203) (CB) ;(11000110) (306) (198) (C6) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ; -;3448;(11111101) (375) (253) (FD) ;(01000110) (106) (70) (46) ;(00110001) (61) (49) (31) ;(11001101) (315) (205) (CD) ;(01000100) (104) (68) (44) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(11000000) (300) (192) (C0) ; -;3456;(01011010) (132) (90) (5A) ;(00111010) (72) (58) (3A) ;(10001101) (215) (141) (8D) ;(01011100) (134) (92) (5C) ;(00000101) (5) (5) (05) ;(00011000) (30) (24) (18) ;(00000111) (7) (7) (07) ;(00001110) (16) (14) (0E) ; -;3464;(00100000) (40) (32) (20) ;(00101011) (53) (43) (2B) ;(01110111) (167) (119) (77) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11111011) (373) (251) (FB) ;(00010000) (20) (16) (10) ;(11110111) (367) (247) (F7) ; -;3472;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00110001) (61) (49) (31) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(11111101) (375) (253) (FD) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ; -;3480;(00010110) (26) (22) (16) ;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(10100111) (247) (167) (A7) ; -;3488;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(00100011) (43) (35) (23) ;(00010001) (21) (17) (11) ;(10101000) (250) (168) (A8) ;(00010000) (20) (16) (10) ;(00111111) (77) (63) (3F) ; -;3496;(00111000) (70) (56) (38) ;(11110110) (366) (246) (F6) ;(00000001) (1) (1) (01) ;(00100001) (41) (33) (21) ;(00010111) (27) (23) (17) ;(00011000) (30) (24) (18) ;(00101010) (52) (42) (2A) ;(00100001) (41) (33) (21) ; -;3504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100010) (42) (34) (22) ;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ; -;3512;(10000110) (206) (134) (86) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00001101) (15) (13) (0D) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ; -;3520;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ;(00000110) (6) (6) (06) ;(00011000) (30) (24) (18) ;(11001101) (315) (205) (CD) ;(01000100) (104) (68) (44) ; -;3528;(00001110) (16) (14) (0E) ;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(01110011) (163) (115) (73) ; -;3536;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(01010010) (122) (82) (52) ;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00100001) (41) (33) (21) ; -;3544;(00011000) (30) (24) (18) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(01011011) (133) (91) (5B) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01001110) (116) (78) (4E) ; -;3552;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(01111000) (170) (120) (78) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(00101000) (50) (40) (28) ; -;3560;(00000101) (5) (5) (05) ;(11111101) (375) (253) (FD) ;(10000110) (206) (134) (86) ;(00110001) (61) (49) (31) ;(11010110) (326) (214) (D6) ;(00011000) (30) (24) (18) ;(11000101) (305) (197) (C5) ;(01000111) (107) (71) (47) ; -;3568;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00001110) (16) (14) (0E) ;(11000001) (301) (193) (C1) ;(00111110) (76) (62) (3E) ;(00100001) (41) (33) (21) ;(10010001) (221) (145) (91) ;(01011111) (137) (95) (5F) ; -;3576;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(11000011) (303) (195) (C3) ;(11011100) (334) (220) (DC) ;(00001010) (12) (10) (0A) ;(00000110) (6) (6) (06) ;(00010111) (27) (23) (17) ; -;3584;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00001110) (16) (14) (0E) ;(00001110) (16) (14) (0E) ;(00001000) (10) (8) (08) ;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(01111000) (170) (120) (78) ; -;3592;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(01111000) (170) (120) (78) ;(00100000) (40) (32) (20) ;(00001100) (14) (12) (0C) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(11100000) (340) (224) (E0) ; -;3600;(11111000) (370) (248) (F8) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(00000001) (1) (1) (01) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00111101) (75) (61) (3D) ;(11101101) (355) (237) (ED) ; -;3608;(10110000) (260) (176) (B0) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(11100000) (340) (224) (E0) ;(11111111) (377) (255) (FF) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(01000111) (107) (71) (47) ; -;3616;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(01001111) (117) (79) (4F) ;(01111000) (170) (120) (78) ;(00000110) (6) (6) (06) ; -;3624;(00000000) (0) (0) (00) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00000110) (6) (6) (06) ;(00000111) (7) (7) (07) ;(00001001) (11) (9) (09) ;(11100110) (346) (230) (E6) ;(11111000) (370) (248) (F8) ; -;3632;(00100000) (40) (32) (20) ;(11011011) (333) (219) (DB) ;(11100001) (341) (225) (E1) ;(00100100) (44) (36) (24) ;(11000001) (301) (193) (C1) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11001101) (315) (205) (CD) ; -;3640;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(11100000) (340) (224) (E0) ;(11111111) (377) (255) (FF) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ; -;3648;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00000110) (6) (6) (06) ;(00000001) (1) (1) (01) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00001110) (16) (14) (0E) ; -;3656;(00001110) (16) (14) (0E) ;(00001000) (10) (8) (08) ;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(01111000) (170) (120) (78) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(00001111) (17) (15) (0F) ; -;3664;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(01001111) (117) (79) (4F) ;(01111000) (170) (120) (78) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001101) (15) (13) (0D) ;(01010100) (124) (84) (54) ; -;3672;(01011101) (135) (93) (5D) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00010011) (23) (19) (13) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00010001) (21) (17) (11) ;(00000001) (1) (1) (01) ; -;3680;(00000111) (7) (7) (07) ;(00011001) (31) (25) (19) ;(00111101) (75) (61) (3D) ;(11100110) (346) (230) (E6) ;(11111000) (370) (248) (F8) ;(01000111) (107) (71) (47) ;(00100000) (40) (32) (20) ;(11100101) (345) (229) (E5) ; -;3688;(11100001) (341) (225) (E1) ;(00100100) (44) (36) (24) ;(11000001) (301) (193) (C1) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11011100) (334) (220) (DC) ;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ; -;3696;(00001110) (16) (14) (0E) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(00010011) (23) (19) (13) ;(00111010) (72) (58) (3A) ;(10001101) (215) (141) (8D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ; -;3704;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01000110) (106) (70) (46) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(00111010) (72) (58) (3A) ;(01001000) (110) (72) (48) ;(01011100) (134) (92) (5C) ; -;3712;(01110111) (167) (119) (77) ;(00001011) (13) (11) (0B) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11000001) (301) (193) (C1) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(11001001) (311) (201) (C9) ; -;3720;(01111100) (174) (124) (7C) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00111101) (75) (61) (3D) ;(11110110) (366) (246) (F6) ;(01010000) (120) (80) (50) ;(01100111) (147) (103) (67) ; -;3728;(11101011) (353) (235) (EB) ;(01100001) (141) (97) (61) ;(01101000) (150) (104) (68) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ; -;3736;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11001001) (311) (201) (C9) ;(00111110) (76) (62) (3E) ;(00011000) (30) (24) (18) ;(10010000) (220) (144) (90) ;(01010111) (127) (87) (57) ;(00001111) (17) (15) (0F) ; -;3744;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(11100110) (346) (230) (E6) ;(11100000) (340) (224) (E0) ;(01101111) (157) (111) (6F) ;(01111010) (172) (122) (7A) ;(11100110) (346) (230) (E6) ;(00011000) (30) (24) (18) ; -;3752;(11110110) (366) (246) (F6) ;(01000000) (100) (64) (40) ;(01100111) (147) (103) (67) ;(11001001) (311) (201) (C9) ;(11110011) (363) (243) (F3) ;(00000110) (6) (6) (06) ;(10110000) (260) (176) (B0) ;(00100001) (41) (33) (21) ; -;3760;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11100101) (345) (229) (E5) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00001110) (16) (14) (0E) ;(11000001) (301) (193) (C1) ; -;3768;(11100001) (341) (225) (E1) ;(00100100) (44) (36) (24) ;(01111100) (174) (124) (7C) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(00100000) (40) (32) (20) ;(00001010) (12) (10) (0A) ;(01111101) (175) (125) (7D) ; -;3776;(11000110) (306) (198) (C6) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(00111111) (77) (63) (3F) ;(10011111) (237) (159) (9F) ;(11100110) (346) (230) (E6) ;(11111000) (370) (248) (F8) ;(10000100) (204) (132) (84) ; -;3784;(01100111) (147) (103) (67) ;(00010000) (20) (16) (10) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(00001101) (15) (13) (0D) ;(11110011) (363) (243) (F3) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ; -;3792;(01011011) (133) (91) (5B) ;(00000110) (6) (6) (06) ;(00001000) (10) (8) (08) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00001110) (16) (14) (0E) ;(11000001) (301) (193) (C1) ; -;3800;(00010000) (20) (16) (10) ;(11111001) (371) (249) (F9) ;(00111110) (76) (62) (3E) ;(00000100) (4) (4) (04) ;(11010011) (323) (211) (D3) ;(11111011) (373) (251) (FB) ;(11111011) (373) (251) (FB) ;(00100001) (41) (33) (21) ; -;3808;(00000000) (0) (0) (00) ;(01011011) (133) (91) (5B) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00010110) (26) (22) (16) ;(10101111) (257) (175) (AF) ;(01000111) (107) (71) (47) ;(01110111) (167) (119) (77) ; -;3816;(00100011) (43) (35) (23) ;(00010000) (20) (16) (10) ;(11111100) (374) (252) (FC) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(10001110) (216) (142) (8E) ;(00001110) (16) (14) (0E) ; -;3824;(00100001) (41) (33) (21) ;(11000011) (303) (195) (C3) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(01111000) (170) (120) (78) ;(11111110) (376) (254) (FE) ;(00000011) (3) (3) (03) ;(10011111) (237) (159) (9F) ; -;3832;(11100110) (346) (230) (E6) ;(00000010) (2) (2) (02) ;(11010011) (323) (211) (D3) ;(11111011) (373) (251) (FB) ;(01010111) (127) (87) (57) ;(11001101) (315) (205) (CD) ;(01010100) (124) (84) (54) ;(00011111) (37) (31) (1F) ; -;3840;(00111000) (70) (56) (38) ;(00001010) (12) (10) (0A) ;(00111110) (76) (62) (3E) ;(00000100) (4) (4) (04) ;(11010011) (323) (211) (D3) ;(11111011) (373) (251) (FB) ;(11111011) (373) (251) (FB) ;(11001101) (315) (205) (CD) ; -;3848;(11011111) (337) (223) (DF) ;(00001110) (16) (14) (0E) ;(11001111) (317) (207) (CF) ;(00001100) (14) (12) (0C) ;(11011011) (333) (219) (DB) ;(11111011) (373) (251) (FB) ;(10000111) (207) (135) (87) ;(11111000) (370) (248) (F8) ; -;3856;(00110000) (60) (48) (30) ;(11101011) (353) (235) (EB) ;(00001110) (16) (14) (0E) ;(00100000) (40) (32) (20) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(00000110) (6) (6) (06) ;(00001000) (10) (8) (08) ; -;3864;(11001011) (313) (203) (CB) ;(00010010) (22) (18) (12) ;(11001011) (313) (203) (CB) ;(00010011) (23) (19) (13) ;(11001011) (313) (203) (CB) ;(00011010) (32) (26) (1A) ;(11011011) (333) (219) (DB) ;(11111011) (373) (251) (FB) ; -;3872;(00011111) (37) (31) (1F) ;(00110000) (60) (48) (30) ;(11111011) (373) (251) (FB) ;(01111010) (172) (122) (7A) ;(11010011) (323) (211) (D3) ;(11111011) (373) (251) (FB) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; -;3880;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11101001) (351) (233) (E9) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ; -;3888;(00100001) (41) (33) (21) ;(01111111) (177) (127) (7F) ;(00010000) (20) (16) (10) ;(11100101) (345) (229) (E5) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ; -;3896;(11001101) (315) (205) (CD) ;(11010100) (324) (212) (D4) ;(00010101) (25) (21) (15) ;(11110101) (365) (245) (F5) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(01011110) (136) (94) (5E) ; -;3904;(11111111) (377) (255) (FF) ;(00100001) (41) (33) (21) ;(11001000) (310) (200) (C8) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(10110101) (265) (181) (B5) ;(00000011) (3) (3) (03) ;(11110001) (361) (241) (F1) ; -;3912;(00100001) (41) (33) (21) ;(00111000) (70) (56) (38) ;(00001111) (17) (15) (0F) ;(11100101) (345) (229) (E5) ;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(00110000) (60) (48) (30) ;(00110001) (61) (49) (31) ; -;3920;(11111110) (376) (254) (FE) ;(00000111) (7) (7) (07) ;(00111000) (70) (56) (38) ;(00101101) (55) (45) (2D) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00111010) (72) (58) (3A) ; -;3928;(00000001) (1) (1) (01) ;(00000010) (2) (2) (02) ;(00000000) (0) (0) (00) ;(01010111) (127) (87) (57) ;(11111110) (376) (254) (FE) ;(00010110) (26) (22) (16) ;(00111000) (70) (56) (38) ;(00001100) (14) (12) (0C) ; -;3936;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01111110) (176) (126) (7E) ;(11001010) (312) (202) (CA) ;(00011110) (36) (30) (1E) ;(00010000) (20) (16) (10) ; -;3944;(11001101) (315) (205) (CD) ;(11010100) (324) (212) (D4) ;(00010101) (25) (21) (15) ;(01011111) (137) (95) (5F) ;(11001101) (315) (205) (CD) ;(11010100) (324) (212) (D4) ;(00010101) (25) (21) (15) ;(11010101) (325) (213) (D5) ; -;3952;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000111) (7) (7) (07) ;(10000110) (206) (134) (86) ;(11001101) (315) (205) (CD) ; -;3960;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(11000001) (301) (193) (C1) ;(00100011) (43) (35) (23) ;(01110000) (160) (112) (70) ;(00100011) (43) (35) (23) ;(01110001) (161) (113) (71) ;(00011000) (30) (24) (18) ; -;3968;(00001010) (12) (10) (0A) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000111) (7) (7) (07) ;(10000110) (206) (134) (86) ;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ; -;3976;(11001101) (315) (205) (CD) ;(01010010) (122) (82) (52) ;(00010110) (26) (22) (16) ;(00010010) (22) (18) (12) ;(00010011) (23) (19) (13) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(01011011) (133) (91) (5B) ; -;3984;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(01011111) (137) (95) (5F) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00100001) (41) (33) (21) ;(10011001) (231) (153) (99) ;(00001111) (17) (15) (0F) ; -;3992;(00011001) (31) (25) (19) ;(01011110) (136) (94) (5E) ;(00011001) (31) (25) (19) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ; -;4000;(00001001) (11) (9) (09) ;(01100110) (146) (102) (66) ;(01101010) (152) (106) (6A) ;(01010000) (120) (80) (50) ;(10110101) (265) (181) (B5) ;(01110000) (160) (112) (70) ;(01111110) (176) (126) (7E) ;(11001111) (317) (207) (CF) ; -;4008;(11010100) (324) (212) (D4) ;(00101010) (52) (42) (2A) ;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ; -;4016;(11000010) (302) (194) (C2) ;(10010111) (227) (151) (97) ;(00010000) (20) (16) (10) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ; -;4024;(00010110) (26) (22) (16) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(11001010) (312) (202) (CA) ;(10010111) (227) (151) (97) ;(00010000) (20) (16) (10) ;(11100101) (345) (229) (E5) ;(00100011) (43) (35) (23) ; -;4032;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(00100001) (41) (33) (21) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(01000100) (104) (68) (44) ; -;4040;(01001101) (115) (77) (4D) ;(11001101) (315) (205) (CD) ;(00000101) (5) (5) (05) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(10010111) (227) (151) (97) ;(00010000) (20) (16) (10) ;(00101010) (52) (42) (2A) ; -;4048;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(11100011) (343) (227) (E3) ;(11100101) (345) (229) (E5) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ; -;4056;(00010110) (26) (22) (16) ;(11100001) (341) (225) (E1) ;(00101011) (53) (43) (2B) ;(11111101) (375) (253) (FD) ;(00110101) (65) (53) (35) ;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(01100000) (140) (96) (60) ; -;4064;(00011000) (30) (24) (18) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(00001111) (17) (15) (0F) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ; -;4072;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ; -;4080;(00010101) (25) (21) (15) ;(00010110) (26) (22) (16) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ;(00100000) (40) (32) (20) ; -;4088;(00001000) (10) (8) (08) ;(00100001) (41) (33) (21) ;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00001111) (17) (15) (0F) ;(00011001) (31) (25) (19) ;(00011000) (30) (24) (18) ; -;4096;(01101101) (155) (109) (6D) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00011000) (30) (24) (18) ;(00011101) (35) (29) (1D) ;(11001101) (315) (205) (CD) ; -;4104;(00110001) (61) (49) (31) ;(00010000) (20) (16) (10) ;(00011000) (30) (24) (18) ;(00000101) (5) (5) (05) ;(11000011) (303) (195) (C3) ;(10100111) (247) (167) (A7) ;(00111100) (74) (60) (3C) ;(11001000) (310) (200) (C8) ; -;4112;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00110001) (61) (49) (31) ;(00010000) (20) (16) (10) ; -;4120;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11000011) (303) (195) (C3) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(11010100) (324) (212) (D4) ; -;4128;(00010101) (25) (21) (15) ;(11001101) (315) (205) (CD) ;(11010100) (324) (212) (D4) ;(00010101) (25) (21) (15) ;(11100001) (341) (225) (E1) ;(11100001) (341) (225) (E1) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ; -;4136;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(11000000) (300) (192) (C0) ;(11111001) (371) (249) (F9) ; -;4144;(11001001) (311) (201) (C9) ;(00110111) (67) (55) (37) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ;(00010001) (21) (17) (11) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00011001) (31) (25) (19) ; -;4152;(00100011) (43) (35) (23) ;(11000001) (301) (193) (C1) ;(11011000) (330) (216) (D8) ;(11000101) (305) (197) (C5) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ; -;4160;(00100011) (43) (35) (23) ;(00011010) (32) (26) (1A) ;(11100110) (346) (230) (E6) ;(11110000) (360) (240) (F0) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00001001) (11) (9) (09) ; -;4168;(00100011) (43) (35) (23) ;(00011010) (32) (26) (1A) ;(11010110) (326) (214) (D6) ;(00010111) (27) (23) (17) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ; -;4176;(00100011) (43) (35) (23) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00001001) (11) (9) (09) ;(11101011) (353) (235) (EB) ;(00111000) (70) (56) (38) ;(11100110) (346) (230) (E6) ; -;4184;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ;(11000000) (300) (192) (C0) ;(00101010) (52) (42) (2A) ;(01001001) (111) (73) (49) ; -;4192;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ;(00010110) (26) (22) (16) ; -;4200;(00100001) (41) (33) (21) ;(01001010) (112) (74) (4A) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00011100) (34) (28) (1C) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ; -;4208;(00010111) (27) (23) (17) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(11000011) (303) (195) (C3) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;4216;(00110111) (67) (55) (37) ;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ;(10101000) (250) (168) (A8) ;(11000011) (303) (195) (C3) ;(10000001) (201) (129) (81) ;(00001111) (17) (15) (0F) ;(11111101) (375) (253) (FD) ; -;4224;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01100110) (146) (102) (66) ;(00101000) (50) (40) (28) ;(10100001) (241) (161) (A1) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ; -;4232;(11111111) (377) (255) (FF) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(01011110) (136) (94) (5E) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(10010000) (220) (144) (90) ; -;4240;(00011010) (32) (26) (1A) ;(11001101) (315) (205) (CD) ;(10110101) (265) (181) (B5) ;(00000011) (3) (3) (03) ;(11000011) (303) (195) (C3) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(11100101) (345) (229) (E5) ; -;4248;(11001101) (315) (205) (CD) ;(10010000) (220) (144) (90) ;(00010001) (21) (17) (11) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ;(00100010) (42) (34) (22) ; -;4256;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000111) (7) (7) (07) ;(00000000) (0) (0) (00) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ; -;4264;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01011110) (136) (94) (5E) ;(11000100) (304) (196) (C4) ;(00011101) (35) (29) (1D) ;(00010001) (21) (17) (11) ;(10100111) (247) (167) (A7) ; -;4272;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01101110) (156) (110) (6E) ;(11001000) (310) (200) (C8) ;(00111010) (72) (58) (3A) ;(00001000) (10) (8) (08) ;(01011100) (134) (92) (5C) ; -;4280;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10101110) (256) (174) (AE) ;(11110101) (365) (245) (F5) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ; -;4288;(01101110) (156) (110) (6E) ;(11000100) (304) (196) (C4) ;(01101110) (156) (110) (6E) ;(00001101) (15) (13) (0D) ;(11110001) (361) (241) (F1) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; -;4296;(01010010) (122) (82) (52) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00101101) (55) (45) (2D) ;(11111110) (376) (254) (FE) ;(00000110) (6) (6) (06) ;(00110000) (60) (48) (30) ; -;4304;(00001010) (12) (10) (0A) ;(01000111) (107) (71) (47) ;(11100110) (346) (230) (E6) ;(00000001) (1) (1) (01) ;(01001111) (117) (79) (4F) ;(01111000) (170) (120) (78) ;(00011111) (37) (31) (1F) ;(11000110) (306) (198) (C6) ; -;4312;(00010010) (22) (18) (12) ;(00011000) (30) (24) (18) ;(00101010) (52) (42) (2A) ;(00100000) (40) (32) (20) ;(00001001) (11) (9) (09) ;(00100001) (41) (33) (21) ;(01101010) (152) (106) (6A) ;(01011100) (134) (92) (5C) ; -;4320;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(10101110) (256) (174) (AE) ;(01110111) (167) (119) (77) ;(00011000) (30) (24) (18) ;(00001110) (16) (14) (0E) ;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ; -;4328;(11011000) (330) (216) (D8) ;(11010110) (326) (214) (D6) ;(00001101) (15) (13) (0D) ;(00100001) (41) (33) (21) ;(01000001) (101) (65) (41) ;(01011100) (134) (92) (5C) ;(10111110) (276) (190) (BE) ;(01110111) (167) (119) (77) ; -;4336;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11011110) (336) (222) (DE) ; -;4344;(10111111) (277) (191) (BF) ;(11001001) (311) (201) (C9) ;(01000111) (107) (71) (47) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(01001111) (117) (79) (4F) ;(00111110) (76) (62) (3E) ;(00010000) (20) (16) (10) ; -;4352;(11001011) (313) (203) (CB) ;(01011000) (130) (88) (58) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00111100) (74) (60) (3C) ;(11111101) (375) (253) (FD) ;(01110001) (161) (113) (71) ;(11010011) (323) (211) (D3) ; -;4360;(00010001) (21) (17) (11) ;(00001101) (15) (13) (0D) ;(00010001) (21) (17) (11) ;(00011000) (30) (24) (18) ;(00000110) (6) (6) (06) ;(00111010) (72) (58) (3A) ;(00001101) (15) (13) (0D) ;(01011100) (134) (92) (5C) ; -;4368;(00010001) (21) (17) (11) ;(10101000) (250) (168) (A8) ;(00010000) (20) (16) (10) ;(00101010) (52) (42) (2A) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;4376;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ; -;4384;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10011110) (236) (158) (9E) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10101110) (256) (174) (AE) ; -;4392;(00101010) (52) (42) (2A) ;(10001010) (212) (138) (8A) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ; -;4400;(00100001) (41) (33) (21) ;(01100111) (147) (103) (67) ;(00010001) (21) (17) (11) ;(11100101) (345) (229) (E5) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ; -;4408;(00101010) (52) (42) (2A) ;(10000010) (202) (130) (82) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00110111) (67) (55) (37) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ;(00010001) (21) (17) (11) ; -;4416;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(01111101) (175) (125) (7D) ;(00011000) (30) (24) (18) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ; -;4424;(00101010) (52) (42) (2A) ;(10001010) (212) (138) (8A) ;(01011100) (134) (92) (5C) ;(11100011) (343) (227) (E3) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ; -;4432;(00111010) (72) (58) (3A) ;(10001011) (213) (139) (8B) ;(01011100) (134) (92) (5C) ;(10010010) (222) (146) (92) ;(00111000) (70) (56) (38) ;(00100110) (46) (38) (26) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ; -;4440;(01111011) (173) (123) (7B) ;(11111101) (375) (253) (FD) ;(10010110) (226) (150) (96) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00011110) (36) (30) (1E) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ; -;4448;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(11010001) (321) (209) (D1) ;(00011000) (30) (24) (18) ;(11101001) (351) (233) (E9) ;(00010110) (26) (22) (16) ; -;4456;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(01011110) (136) (94) (5E) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(10010000) (220) (144) (90) ;(00011010) (32) (26) (1A) ;(11001101) (315) (205) (CD) ; -;4464;(10110101) (265) (181) (B5) ;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ; -;4472;(10001010) (212) (138) (8A) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00000010) (2) (2) (02) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ; -;4480;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11000001) (301) (193) (C1) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(11100001) (341) (225) (E1) ; -;4488;(00100010) (42) (34) (22) ;(10000010) (202) (130) (82) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(11001001) (311) (201) (C9) ; -;4496;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01011001) (131) (89) (59) ; -;4504;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ;(11001000) (310) (200) (C8) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ; -;4512;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(11011000) (330) (216) (D8) ;(00101010) (52) (42) (2A) ;(01100011) (143) (99) (63) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(01111110) (176) (126) (7E) ; -;4520;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ;(00000001) (1) (1) (01) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ; -;4528;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11110001) (361) (241) (F1) ;(11001001) (311) (201) (C9) ;(11110011) (363) (243) (F3) ; -;4536;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(10110010) (262) (178) (B2) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ; -;4544;(01001011) (113) (75) (4B) ;(10110100) (264) (180) (B4) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(00111000) (70) (56) (38) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ; -;4552;(01111011) (173) (123) (7B) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(01000111) (107) (71) (47) ;(00111110) (76) (62) (3E) ;(00000111) (7) (7) (07) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ; -;4560;(00111110) (76) (62) (3E) ;(00111111) (77) (63) (3F) ;(11101101) (355) (237) (ED) ;(01000111) (107) (71) (47) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;4568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(00110110) (66) (54) (36) ;(00000010) (2) (2) (02) ;(00101011) (53) (43) (2B) ;(10111100) (274) (188) (BC) ; -;4576;(00100000) (40) (32) (20) ;(11111010) (372) (250) (FA) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00011001) (31) (25) (19) ;(00100011) (43) (35) (23) ;(00110000) (60) (48) (30) ; -;4584;(00000110) (6) (6) (06) ;(00110101) (65) (53) (35) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(00110101) (65) (53) (35) ;(00101000) (50) (40) (28) ;(11110011) (363) (243) (F3) ;(00101011) (53) (43) (2B) ; -;4592;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(10110100) (264) (180) (B4) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(00111000) (70) (56) (38) ; -;4600;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01111011) (173) (123) (7B) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(00000100) (4) (4) (04) ;(00101000) (50) (40) (28) ;(00011001) (31) (25) (19) ; -;4608;(00100010) (42) (34) (22) ;(10110100) (264) (180) (B4) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(10101111) (257) (175) (AF) ;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(10101000) (250) (168) (A8) ; -;4616;(00000000) (0) (0) (00) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11101011) (353) (235) (EB) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01111011) (173) (123) (7B) ; -;4624;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(00000001) (1) (1) (01) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(00111000) (70) (56) (38) ; -;4632;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(10110010) (262) (178) (B2) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(00100010) (42) (34) (22) ; -;4640;(00110110) (66) (54) (36) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(10110010) (262) (178) (B2) ;(01011100) (134) (92) (5C) ;(00110110) (66) (54) (36) ;(00111110) (76) (62) (3E) ;(00101011) (53) (43) (2B) ; -;4648;(11111001) (371) (249) (F9) ;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01010110) (126) (86) (56) ; -;4656;(11111101) (375) (253) (FD) ;(00100001) (41) (33) (21) ;(00111010) (72) (58) (3A) ;(01011100) (134) (92) (5C) ;(11111011) (373) (251) (FB) ;(00111010) (72) (58) (3A) ;(01010000) (120) (80) (50) ;(01011100) (134) (92) (5C) ; -;4664;(10100111) (247) (167) (A7) ;(00111110) (76) (62) (3E) ;(00100001) (41) (33) (21) ;(11000010) (302) (194) (C2) ;(00010011) (23) (19) (13) ;(00010011) (23) (19) (13) ;(00011000) (30) (24) (18) ;(00001101) (15) (13) (0D) ; -;4672;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ;(01000001) (101) (65) (41) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11001011) (313) (203) (CB) ; -;4680;(10101111) (257) (175) (AF) ;(11001011) (313) (203) (CB) ;(11111001) (371) (249) (F9) ;(11001001) (311) (201) (C9) ;(00000000) (0) (0) (00) ;(00100001) (41) (33) (21) ;(10110110) (266) (182) (B6) ;(01011100) (134) (92) (5C) ; -;4688;(00100010) (42) (34) (22) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(10101111) (257) (175) (AF) ;(00010101) (25) (21) (15) ;(00000001) (1) (1) (01) ;(00010101) (25) (21) (15) ; -;4696;(00000000) (0) (0) (00) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11101011) (353) (235) (EB) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ;(01010111) (127) (87) (57) ; -;4704;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01001011) (113) (75) (4B) ;(01011100) (134) (92) (5C) ; -;4712;(00110110) (66) (54) (36) ;(10000000) (200) (128) (80) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00111110) (76) (62) (3E) ;(00111000) (70) (56) (38) ; -;4720;(00110010) (62) (50) (32) ;(10001101) (215) (141) (8D) ;(01011100) (134) (92) (5C) ;(00110010) (62) (50) (32) ;(01001000) (110) (72) (48) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(00100011) (43) (35) (23) ; -;4728;(00000101) (5) (5) (05) ;(00100010) (42) (34) (22) ;(00001001) (11) (9) (09) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110101) (65) (53) (35) ;(11000110) (306) (198) (C6) ;(11111101) (375) (253) (FD) ; -;4736;(00110101) (65) (53) (35) ;(11001010) (312) (202) (CA) ;(00100001) (41) (33) (21) ;(11000110) (306) (198) (C6) ;(00010101) (25) (21) (15) ;(00010001) (21) (17) (11) ;(00010000) (20) (16) (10) ;(01011100) (134) (92) (5C) ; -;4744;(00001110) (16) (14) (0E) ;(00001110) (16) (14) (0E) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11001101) (315) (205) (CD) ;(11011111) (337) (223) (DF) ;(00001110) (16) (14) (0E) ;(11111101) (375) (253) (FD) ; -;4752;(00110110) (66) (54) (36) ;(00110001) (61) (49) (31) ;(00000010) (2) (2) (02) ;(11001101) (315) (205) (CD) ;(01101011) (153) (107) (6B) ;(00001101) (15) (13) (0D) ;(00010001) (21) (17) (11) ;(00111000) (70) (56) (38) ; -;4760;(00010101) (25) (21) (15) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11101110) (356) (238) (EE) ; -;4768;(00011000) (30) (24) (18) ;(00000111) (7) (7) (07) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00110001) (61) (49) (31) ;(00000010) (2) (2) (02) ;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ; -;4776;(00010111) (27) (23) (17) ;(11001101) (315) (205) (CD) ;(10110000) (260) (176) (B0) ;(00010110) (26) (22) (16) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ; -;4784;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(00010111) (27) (23) (17) ;(00011011) (33) (27) (1B) ;(11111101) (375) (253) (FD) ; -;4792;(11001011) (313) (203) (CB) ;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ; -;4800;(01100110) (146) (102) (66) ;(00101000) (50) (40) (28) ;(01000000) (100) (64) (40) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10100111) (247) (167) (A7) ; -;4808;(00010001) (21) (17) (11) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(00011000) (30) (24) (18) ;(11011101) (335) (221) (DD) ;(11111101) (375) (253) (FD) ; -;4816;(00110110) (66) (54) (36) ;(00000111) (7) (7) (07) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00011001) (31) (25) (19) ; -;4824;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(11000010) (302) (194) (C2) ;(01011101) (135) (93) (5D) ;(00010101) (25) (21) (15) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ; -;4832;(00101000) (50) (40) (28) ;(11000000) (300) (192) (C0) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01000110) (106) (70) (46) ;(11000100) (304) (196) (C4) ;(10101111) (257) (175) (AF) ; -;4840;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00001101) (15) (13) (0D) ;(00111110) (76) (62) (3E) ;(00011001) (31) (25) (19) ;(11111101) (375) (253) (FD) ;(10010110) (226) (150) (96) ; -;4848;(01001111) (117) (79) (4F) ;(00110010) (62) (50) (32) ;(10001100) (214) (140) (8C) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11111110) (376) (254) (FE) ; -;4856;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00001010) (12) (10) (0A) ;(00000001) (1) (1) (01) ; -;4864;(11001101) (315) (205) (CD) ;(10001010) (212) (138) (8A) ;(00011011) (33) (27) (1B) ;(01110110) (166) (118) (76) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10101110) (256) (174) (AE) ; -;4872;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01001110) (116) (78) (4E) ;(11000100) (304) (196) (C4) ;(11001101) (315) (205) (CD) ;(00001110) (16) (14) (0E) ;(00111010) (72) (58) (3A) ; -;4880;(00111010) (72) (58) (3A) ;(01011100) (134) (92) (5C) ;(00111100) (74) (60) (3C) ;(11110101) (365) (245) (F5) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ; -;4888;(01110100) (164) (116) (74) ;(00110111) (67) (55) (37) ;(11111101) (375) (253) (FD) ;(01110100) (164) (116) (74) ;(00100110) (46) (38) (26) ;(00100010) (42) (34) (22) ;(00001011) (13) (11) (0B) ;(01011100) (134) (92) (5C) ; -;4896;(00100001) (41) (33) (21) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00100010) (42) (34) (22) ;(00010110) (26) (22) (16) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10110000) (260) (176) (B0) ; -;4904;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(10101110) (256) (174) (AE) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00001101) (15) (13) (0D) ; -;4912;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11101110) (356) (238) (EE) ;(11110001) (361) (241) (F1) ;(01000111) (107) (71) (47) ;(11111110) (376) (254) (FE) ;(00001010) (12) (10) (0A) ; -;4920;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11000110) (306) (198) (C6) ;(00000111) (7) (7) (07) ;(11001101) (315) (205) (CD) ;(11101111) (357) (239) (EF) ;(00010101) (25) (21) (15) ;(11000011) (303) (195) (C3) ; -;4928;(10010100) (224) (148) (94) ;(00111100) (74) (60) (3C) ;(01111000) (170) (120) (78) ;(00010001) (21) (17) (11) ;(10010001) (221) (145) (91) ;(00010011) (23) (19) (13) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ; -;4936;(00001100) (14) (12) (0C) ;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ;(00110110) (66) (54) (36) ;(00010101) (25) (21) (15) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ; -;4944;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00011010) (32) (26) (1A) ;(00111110) (76) (62) (3E) ; -;4952;(00111010) (72) (58) (3A) ;(11010111) (327) (215) (D7) ;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(00001101) (15) (13) (0D) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ; -;4960;(00011011) (33) (27) (1B) ;(00011010) (32) (26) (1A) ;(11001101) (315) (205) (CD) ;(10010111) (227) (151) (97) ;(00010000) (20) (16) (10) ;(00111010) (72) (58) (3A) ;(00111010) (72) (58) (3A) ;(01011100) (134) (92) (5C) ; -;4968;(00111100) (74) (60) (3C) ;(00101000) (50) (40) (28) ;(00011011) (33) (27) (1B) ;(11111110) (376) (254) (FE) ;(00001001) (11) (9) (09) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ; -;4976;(00010101) (25) (21) (15) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(00001101) (15) (13) (0D) ;(00000001) (1) (1) (01) ;(00000011) (3) (3) (03) ; -;4984;(00000000) (0) (0) (00) ;(00010001) (21) (17) (11) ;(01110000) (160) (112) (70) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(01000100) (104) (68) (44) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ; -;4992;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(00001001) (11) (9) (09) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ; -;5000;(00001010) (12) (10) (0A) ;(11111111) (377) (255) (FF) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10011110) (236) (158) (9E) ;(11000011) (303) (195) (C3) ;(10101100) (254) (172) (AC) ; -;5008;(00010010) (22) (18) (12) ;(10000000) (200) (128) (80) ;(01001111) (117) (79) (4F) ;(11001011) (313) (203) (CB) ;(01001110) (116) (78) (4E) ;(01000101) (105) (69) (45) ;(01011000) (130) (88) (58) ;(01010100) (124) (84) (54) ; -;5016;(00100000) (40) (32) (20) ;(01110111) (167) (119) (77) ;(01101001) (151) (105) (69) ;(01110100) (164) (116) (74) ;(01101000) (150) (104) (68) ;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ; -;5024;(00100000) (40) (32) (20) ;(01000110) (106) (70) (46) ;(01001111) (117) (79) (4F) ;(11010010) (322) (210) (D2) ;(01010110) (126) (86) (56) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01101001) (151) (105) (69) ; -;5032;(01100001) (141) (97) (61) ;(01100010) (142) (98) (62) ;(01101100) (154) (108) (6C) ;(01100101) (145) (101) (65) ;(00100000) (40) (32) (20) ;(01101110) (156) (110) (6E) ;(01101111) (157) (111) (6F) ;(01110100) (164) (116) (74) ; -;5040;(00100000) (40) (32) (20) ;(01100110) (146) (102) (66) ;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(01101110) (156) (110) (6E) ;(11100100) (344) (228) (E4) ;(01010011) (123) (83) (53) ;(01110101) (165) (117) (75) ; -;5048;(01100010) (142) (98) (62) ;(01110011) (163) (115) (73) ;(01100011) (143) (99) (63) ;(01110010) (162) (114) (72) ;(01101001) (151) (105) (69) ;(01110000) (160) (112) (70) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ; -;5056;(01110111) (167) (119) (77) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(01101110) (156) (110) (6E) ;(11100111) (347) (231) (E7) ;(01001111) (117) (79) (4F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ; -;5064;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(01100110) (146) (102) (66) ;(00100000) (40) (32) (20) ;(01101101) (155) (109) (6D) ;(01100101) (145) (101) (65) ;(01101101) (155) (109) (6D) ;(01101111) (157) (111) (6F) ; -;5072;(01110010) (162) (114) (72) ;(11111001) (371) (249) (F9) ;(01001111) (117) (79) (4F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(01100110) (146) (102) (66) ; -;5080;(00100000) (40) (32) (20) ;(01110011) (163) (115) (73) ;(01100011) (143) (99) (63) ;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01100101) (145) (101) (65) ;(11101110) (356) (238) (EE) ;(01001110) (116) (78) (4E) ; -;5088;(01110101) (165) (117) (75) ;(01101101) (155) (109) (6D) ;(01100010) (142) (98) (62) ;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ;(01110100) (164) (116) (74) ;(01101111) (157) (111) (6F) ; -;5096;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(01100010) (142) (98) (62) ;(01101001) (151) (105) (69) ;(11100111) (347) (231) (E7) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01010100) (124) (84) (54) ; -;5104;(01010101) (125) (85) (55) ;(01010010) (122) (82) (52) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(01110111) (167) (119) (77) ;(01101001) (151) (105) (69) ;(01110100) (164) (116) (74) ;(01101000) (150) (104) (68) ; -;5112;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01000111) (107) (71) (47) ;(01001111) (117) (79) (4F) ;(01010011) (123) (83) (53) ;(01010101) (125) (85) (55) ; -;5120;(11000010) (302) (194) (C2) ;(01000101) (105) (69) (45) ;(01101110) (156) (110) (6E) ;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(01100110) (146) (102) (66) ;(00100000) (40) (32) (20) ; -;5128;(01100110) (146) (102) (66) ;(01101001) (151) (105) (69) ;(01101100) (154) (108) (6C) ;(11100101) (345) (229) (E5) ;(01010011) (123) (83) (53) ;(01010100) (124) (84) (54) ;(01001111) (117) (79) (4F) ;(01010000) (120) (80) (50) ; -;5136;(00100000) (40) (32) (20) ;(01110011) (163) (115) (73) ;(01110100) (164) (116) (74) ;(01100001) (141) (97) (61) ;(01110100) (164) (116) (74) ;(01100101) (145) (101) (65) ;(01101101) (155) (109) (6D) ;(01100101) (145) (101) (65) ; -;5144;(01101110) (156) (110) (6E) ;(11110100) (364) (244) (F4) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ;(01110110) (166) (118) (76) ;(01100001) (141) (97) (61) ;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ; -;5152;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01100111) (147) (103) (67) ;(01110101) (165) (117) (75) ;(01101101) (155) (109) (6D) ;(01100101) (145) (101) (65) ; -;5160;(01101110) (156) (110) (6E) ;(11110100) (364) (244) (F4) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ;(01110100) (164) (116) (74) ;(01100101) (145) (101) (65) ;(01100111) (147) (103) (67) ;(01100101) (145) (101) (65) ; -;5168;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ;(01100110) (146) (102) (66) ; -;5176;(00100000) (40) (32) (20) ;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ;(01101110) (156) (110) (6E) ;(01100111) (147) (103) (67) ;(11100101) (345) (229) (E5) ;(01001110) (116) (78) (4E) ;(01101111) (157) (111) (6F) ; -;5184;(01101110) (156) (110) (6E) ;(01110011) (163) (115) (73) ;(01100101) (145) (101) (65) ;(01101110) (156) (110) (6E) ;(01110011) (163) (115) (73) ;(01100101) (145) (101) (65) ;(00100000) (40) (32) (20) ;(01101001) (151) (105) (69) ; -;5192;(01101110) (156) (110) (6E) ;(00100000) (40) (32) (20) ;(01000010) (102) (66) (42) ;(01000001) (101) (65) (41) ;(01010011) (123) (83) (53) ;(01001001) (111) (73) (49) ;(11000011) (303) (195) (C3) ;(01000010) (102) (66) (42) ; -;5200;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01000001) (101) (65) (41) ;(01001011) (113) (75) (4B) ;(00100000) (40) (32) (20) ;(00101101) (55) (45) (2D) ;(00100000) (40) (32) (20) ;(01000011) (103) (67) (43) ; -;5208;(01001111) (117) (79) (4F) ;(01001110) (116) (78) (4E) ;(01010100) (124) (84) (54) ;(00100000) (40) (32) (20) ;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01110000) (160) (112) (70) ;(01100101) (145) (101) (65) ; -;5216;(01100001) (141) (97) (61) ;(01110100) (164) (116) (74) ;(11110011) (363) (243) (F3) ;(01001111) (117) (79) (4F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01101111) (157) (111) (6F) ; -;5224;(01100110) (146) (102) (66) ;(00100000) (40) (32) (20) ;(01000100) (104) (68) (44) ;(01000001) (101) (65) (41) ;(01010100) (124) (84) (54) ;(11000001) (301) (193) (C1) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ; -;5232;(01110110) (166) (118) (76) ;(01100001) (141) (97) (61) ;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01100110) (146) (102) (66) ;(01101001) (151) (105) (69) ; -;5240;(01101100) (154) (108) (6C) ;(01100101) (145) (101) (65) ;(00100000) (40) (32) (20) ;(01101110) (156) (110) (6E) ;(01100001) (141) (97) (61) ;(01101101) (155) (109) (6D) ;(11100101) (345) (229) (E5) ;(01001110) (116) (78) (4E) ; -;5248;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(01101111) (157) (111) (6F) ;(01101101) (155) (109) (6D) ;(00100000) (40) (32) (20) ;(01100110) (146) (102) (66) ; -;5256;(01101111) (157) (111) (6F) ;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ;(01101110) (156) (110) (6E) ;(11100101) (345) (229) (E5) ;(01010011) (123) (83) (53) ; -;5264;(01010100) (124) (84) (54) ;(01001111) (117) (79) (4F) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01101001) (151) (105) (69) ;(01101110) (156) (110) (6E) ;(00100000) (40) (32) (20) ;(01001001) (111) (73) (49) ; -;5272;(01001110) (116) (78) (4E) ;(01010000) (120) (80) (50) ;(01010101) (125) (85) (55) ;(11010100) (324) (212) (D4) ;(01000110) (106) (70) (46) ;(01001111) (117) (79) (4F) ;(01010010) (122) (82) (52) ;(00100000) (40) (32) (20) ; -;5280;(01110111) (167) (119) (77) ;(01101001) (151) (105) (69) ;(01110100) (164) (116) (74) ;(01101000) (150) (104) (68) ;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ; -;5288;(01001110) (116) (78) (4E) ;(01000101) (105) (69) (45) ;(01011000) (130) (88) (58) ;(11010100) (324) (212) (D4) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ;(01110110) (166) (118) (76) ;(01100001) (141) (97) (61) ; -;5296;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01001001) (111) (73) (49) ;(00101111) (57) (47) (2F) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ; -;5304;(01100100) (144) (100) (64) ;(01100101) (145) (101) (65) ;(01110110) (166) (118) (76) ;(01101001) (151) (105) (69) ;(01100011) (143) (99) (63) ;(11100101) (345) (229) (E5) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ; -;5312;(01110110) (166) (118) (76) ;(01100001) (141) (97) (61) ;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01100011) (143) (99) (63) ;(01101111) (157) (111) (6F) ; -;5320;(01101100) (154) (108) (6C) ;(01101111) (157) (111) (6F) ;(01110101) (165) (117) (75) ;(11110010) (362) (242) (F2) ;(01000010) (102) (66) (42) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01000001) (101) (65) (41) ; -;5328;(01001011) (113) (75) (4B) ;(00100000) (40) (32) (20) ;(01101001) (151) (105) (69) ;(01101110) (156) (110) (6E) ;(01110100) (164) (116) (74) ;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; -;5336;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(01100111) (147) (103) (67) ;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(01000001) (101) (65) (41) ; -;5344;(01001101) (115) (77) (4D) ;(01010100) (124) (84) (54) ;(01001111) (117) (79) (4F) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01101110) (156) (110) (6E) ;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ; -;5352;(01100111) (147) (103) (67) ;(01101111) (157) (111) (6F) ;(01101111) (157) (111) (6F) ;(11100100) (344) (228) (E4) ;(01010011) (123) (83) (53) ;(01110100) (164) (116) (74) ;(01100001) (141) (97) (61) ;(01110100) (164) (116) (74) ; -;5360;(01100101) (145) (101) (65) ;(01101101) (155) (109) (6D) ;(01100101) (145) (101) (65) ;(01101110) (156) (110) (6E) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01101100) (154) (108) (6C) ;(01101111) (157) (111) (6F) ; -;5368;(01110011) (163) (115) (73) ;(11110100) (364) (244) (F4) ;(01001001) (111) (73) (49) ;(01101110) (156) (110) (6E) ;(01110110) (166) (118) (76) ;(01100001) (141) (97) (61) ;(01101100) (154) (108) (6C) ;(01101001) (151) (105) (69) ; -;5376;(01100100) (144) (100) (64) ;(00100000) (40) (32) (20) ;(01110011) (163) (115) (73) ;(01110100) (164) (116) (74) ;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01100001) (141) (97) (61) ;(11101101) (355) (237) (ED) ; -;5384;(01000110) (106) (70) (46) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(01110111) (167) (119) (77) ;(01101001) (151) (105) (69) ;(01110100) (164) (116) (74) ;(01101000) (150) (104) (68) ;(01101111) (157) (111) (6F) ; -;5392;(01110101) (165) (117) (75) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01000100) (104) (68) (44) ;(01000101) (105) (69) (45) ;(11000110) (306) (198) (C6) ;(01010000) (120) (80) (50) ;(01100001) (141) (97) (61) ; -;5400;(01110010) (162) (114) (72) ;(01100001) (141) (97) (61) ;(01101101) (155) (109) (6D) ;(01100101) (145) (101) (65) ;(01110100) (164) (116) (74) ;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(00100000) (40) (32) (20) ; -;5408;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(11110010) (362) (242) (F2) ;(01010100) (124) (84) (54) ;(01100001) (141) (97) (61) ;(01110000) (160) (112) (70) ; -;5416;(01100101) (145) (101) (65) ;(00100000) (40) (32) (20) ;(01101100) (154) (108) (6C) ;(01101111) (157) (111) (6F) ;(01100001) (141) (97) (61) ;(01100100) (144) (100) (64) ;(01101001) (151) (105) (69) ;(01101110) (156) (110) (6E) ; -;5424;(01100111) (147) (103) (67) ;(00100000) (40) (32) (20) ;(01100101) (145) (101) (65) ;(01110010) (162) (114) (72) ;(01110010) (162) (114) (72) ;(01101111) (157) (111) (6F) ;(11110010) (362) (242) (F2) ;(00101100) (54) (44) (2C) ; -;5432;(10100000) (240) (160) (A0) ;(01111111) (177) (127) (7F) ;(00100000) (40) (32) (20) ;(00110001) (61) (49) (31) ;(00111001) (71) (57) (39) ;(00111000) (70) (56) (38) ;(00110010) (62) (50) (32) ;(00100000) (40) (32) (20) ; -;5440;(01010011) (123) (83) (53) ;(01101001) (151) (105) (69) ;(01101110) (156) (110) (6E) ;(01100011) (143) (99) (63) ;(01101100) (154) (108) (6C) ;(01100001) (141) (97) (61) ;(01101001) (151) (105) (69) ;(01110010) (162) (114) (72) ; -;5448;(00100000) (40) (32) (20) ;(01010010) (122) (82) (52) ;(01100101) (145) (101) (65) ;(01110011) (163) (115) (73) ;(01100101) (145) (101) (65) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01100011) (143) (99) (63) ; -;5456;(01101000) (150) (104) (68) ;(00100000) (40) (32) (20) ;(01001100) (114) (76) (4C) ;(01110100) (164) (116) (74) ;(11100100) (344) (228) (E4) ;(00111110) (76) (62) (3E) ;(00010000) (20) (16) (10) ;(00000001) (1) (1) (01) ; -;5464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000011) (303) (195) (C3) ;(00010011) (23) (19) (13) ;(00010011) (23) (19) (13) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01001001) (111) (73) (49) ; -;5472;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(01010101) (125) (85) (55) ;(00010101) (25) (21) (15) ; -;5480;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00110111) (67) (55) (37) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11100101) (345) (229) (E5) ; -;5488;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ; -;5496;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(01111001) (171) (121) (79) ;(00111101) (75) (61) (3D) ; -;5504;(10110000) (260) (176) (B0) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(11000101) (305) (197) (C5) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ; -;5512;(00101011) (53) (43) (2B) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ; -;5520;(00010110) (26) (22) (16) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(11000001) (301) (193) (C1) ;(11000101) (305) (197) (C5) ;(00010011) (23) (19) (13) ; -;5528;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(00101010) (52) (42) (2A) ; -;5536;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(11000001) (301) (193) (C1) ;(01110000) (160) (112) (70) ;(00101011) (53) (43) (2B) ;(01110001) (161) (113) (71) ;(00101011) (53) (43) (2B) ; -;5544;(01110011) (163) (115) (73) ;(00101011) (53) (43) (2B) ;(01110010) (162) (114) (72) ;(11110001) (361) (241) (F1) ;(11000011) (303) (195) (C3) ;(10100010) (242) (162) (A2) ;(00010010) (22) (18) (12) ;(11110100) (364) (244) (F4) ; -;5552;(00001001) (11) (9) (09) ;(10101000) (250) (168) (A8) ;(00010000) (20) (16) (10) ;(01001011) (113) (75) (4B) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(11000100) (304) (196) (C4) ;(00010101) (25) (21) (15) ; -;5560;(01010011) (123) (83) (53) ;(10000001) (201) (129) (81) ;(00001111) (17) (15) (0F) ;(11000100) (304) (196) (C4) ;(00010101) (25) (21) (15) ;(01010010) (122) (82) (52) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ; -;5568;(11000100) (304) (196) (C4) ;(00010101) (25) (21) (15) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(11001111) (317) (207) (CF) ;(00010010) (22) (18) (12) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ; -;5576;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001011) (13) (11) (0B) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ; -;5584;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01101110) (156) (110) (6E) ; -;5592;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11011110) (336) (222) (DE) ;(11001101) (315) (205) (CD) ;(11100110) (346) (230) (E6) ; -;5600;(00010101) (25) (21) (15) ;(11011000) (330) (216) (D8) ;(00101000) (50) (40) (28) ;(11111010) (372) (250) (FA) ;(11001111) (317) (207) (CF) ;(00000111) (7) (7) (07) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ; -;5608;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ;(00011110) (36) (30) (1E) ; -;5616;(00110000) (60) (48) (30) ;(10000011) (203) (131) (83) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(01011110) (136) (94) (5E) ; -;5624;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(00101100) (54) (44) (2C) ;(00010110) (26) (22) (16) ;(11100001) (341) (225) (E1) ;(11011001) (331) (217) (D9) ; -;5632;(11001001) (311) (201) (C9) ;(10000111) (207) (135) (87) ;(11000110) (306) (198) (C6) ;(00010110) (26) (22) (16) ;(01101111) (157) (111) (6F) ;(00100110) (46) (38) (26) ;(01011100) (134) (92) (5C) ;(01011110) (136) (94) (5E) ; -;5640;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00010111) (27) (23) (17) ; -;5648;(00011011) (33) (27) (1B) ;(00101010) (52) (42) (2A) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(00011001) (31) (25) (19) ;(00100010) (42) (34) (22) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ; -;5656;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(10100110) (246) (166) (A6) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;5664;(01001110) (116) (78) (4E) ;(00100001) (41) (33) (21) ;(00101101) (55) (45) (2D) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(11011100) (334) (220) (DC) ;(00010110) (26) (22) (16) ;(11010000) (320) (208) (D0) ; -;5672;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(01011110) (136) (94) (5E) ;(00011001) (31) (25) (19) ;(11101001) (351) (233) (E9) ;(01001011) (113) (75) (4B) ;(00000110) (6) (6) (06) ;(01010011) (123) (83) (53) ; -;5680;(00010010) (22) (18) (12) ;(01010000) (120) (80) (50) ;(00011011) (33) (27) (1B) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11000110) (306) (198) (C6) ; -;5688;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10101110) (256) (174) (AE) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(11100110) (346) (230) (E6) ; -;5696;(00011000) (30) (24) (18) ;(00000100) (4) (4) (04) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10000110) (206) (134) (86) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;5704;(00000001) (1) (1) (01) ;(10001110) (216) (142) (8E) ;(11000011) (303) (195) (C3) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;5712;(11001110) (316) (206) (CE) ;(11001001) (311) (201) (C9) ;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(00000101) (5) (5) (05) ; -;5720;(00011111) (37) (31) (1F) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(01100100) (144) (100) (64) ;(00010110) (26) (22) (16) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ; -;5728;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ;(01001011) (113) (75) (4B) ; -;5736;(01011100) (134) (92) (5C) ;(00111110) (76) (62) (3E) ;(00001110) (16) (14) (0E) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(11100011) (343) (227) (E3) ;(10100111) (247) (167) (A7) ; -;5744;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00011001) (31) (25) (19) ;(11100011) (343) (227) (E3) ;(00110000) (60) (48) (30) ;(00001001) (11) (9) (09) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ; -;5752;(00001001) (11) (9) (09) ;(11101011) (353) (235) (EB) ;(01110010) (162) (114) (72) ;(00101011) (53) (43) (2B) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(11010001) (321) (209) (D1) ;(00100011) (43) (35) (23) ; -;5760;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11101000) (350) (232) (E8) ;(11101011) (353) (235) (EB) ;(11010001) (321) (209) (D1) ;(11110001) (361) (241) (F1) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ; -;5768;(01010010) (122) (82) (52) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(00000011) (3) (3) (03) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11001001) (311) (201) (C9) ;(00000000) (0) (0) (00) ; -;5776;(00000000) (0) (0) (00) ;(11101011) (353) (235) (EB) ;(00010001) (21) (17) (11) ;(10001111) (217) (143) (8F) ;(00010110) (26) (22) (16) ;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(11000000) (300) (192) (C0) ; -;5784;(00100000) (40) (32) (20) ;(11110111) (367) (247) (F7) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01100011) (143) (99) (63) ; -;5792;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(11000001) (301) (193) (C1) ; -;5800;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(11000001) (301) (193) (C1) ;(11101011) (353) (235) (EB) ;(00100011) (43) (35) (23) ;(11001001) (311) (201) (C9) ; -;5808;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00110110) (66) (54) (36) ;(00001101) (15) (13) (0D) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ; -;5816;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(10000000) (200) (128) (80) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ; -;5824;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01100011) (143) (99) (63) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01100011) (143) (99) (63) ;(01011100) (134) (92) (5C) ; -;5832;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ;(10010010) (222) (146) (92) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ; -;5840;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00101011) (53) (43) (2B) ;(00000000) (0) (0) (00) ;(00101010) (52) (42) (2A) ; -;5848;(10110000) (260) (176) (B0) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(11001000) (310) (200) (C8) ;(10111001) (271) (185) (B9) ; -;5856;(00100011) (43) (35) (23) ;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00011110) (36) (30) (1E) ;(00010111) (27) (23) (17) ; -;5864;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00111100) (74) (60) (3C) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010001) (21) (17) (11) ;(11100010) (342) (226) (E2) ; -;5872;(10100011) (243) (163) (A3) ;(11101011) (353) (235) (EB) ;(00011001) (31) (25) (19) ;(00111000) (70) (56) (38) ;(00000111) (7) (7) (07) ;(00000001) (1) (1) (01) ;(11010100) (324) (212) (D4) ;(00010101) (25) (21) (15) ; -;5880;(00001001) (11) (9) (09) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11101011) (353) (235) (EB) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01110000) (160) (112) (70) ; -;5888;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(00001001) (11) (9) (09) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;5896;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(11011110) (336) (222) (DE) ;(00111100) (74) (60) (3C) ;(11001101) (315) (205) (CD) ;(11011100) (334) (220) (DC) ; -;5904;(00010110) (26) (22) (16) ;(01001110) (116) (78) (4E) ;(00011000) (30) (24) (18) ;(00000010) (2) (2) (02) ;(00001001) (11) (9) (09) ;(11101001) (351) (233) (E9) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;5912;(00111000) (70) (56) (38) ;(11111010) (372) (250) (FA) ;(00011000) (30) (24) (18) ;(00001001) (11) (9) (09) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ; -;5920;(00011110) (36) (30) (1E) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00010111) (27) (23) (17) ;(11000110) (306) (198) (C6) ; -;5928;(00000011) (3) (3) (03) ;(00000111) (7) (7) (07) ;(00100001) (41) (33) (21) ;(00010000) (20) (16) (10) ;(01011100) (134) (92) (5C) ;(01001111) (117) (79) (4F) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;5936;(00001001) (11) (9) (09) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(00101011) (53) (43) (2B) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00000001) (1) (1) (01) ; -;5944;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(00011110) (36) (30) (1E) ;(00010111) (27) (23) (17) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00010110) (26) (22) (16) ; -;5952;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(00001001) (11) (9) (09) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;5960;(01111110) (176) (126) (7E) ;(11101011) (353) (235) (EB) ;(11111110) (376) (254) (FE) ;(01001011) (113) (75) (4B) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(11111110) (376) (254) (FE) ;(01010011) (123) (83) (53) ; -;5968;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11001111) (317) (207) (CF) ;(11001101) (315) (205) (CD) ;(01011101) (135) (93) (5D) ; -;5976;(00010111) (27) (23) (17) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ; -;5984;(00101011) (53) (43) (2B) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00001110) (16) (14) (0E) ;(11000101) (305) (197) (C5) ; -;5992;(00011010) (32) (26) (1A) ;(11100110) (346) (230) (E6) ;(11011111) (337) (223) (DF) ;(01001111) (117) (79) (4F) ;(00100001) (41) (33) (21) ;(01111010) (172) (122) (7A) ;(00010111) (27) (23) (17) ;(11001101) (315) (205) (CD) ; -;6000;(11011100) (334) (220) (DC) ;(00010110) (26) (22) (16) ;(00110000) (60) (48) (30) ;(11110001) (361) (241) (F1) ;(01001110) (116) (78) (4E) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ; -;6008;(11000001) (301) (193) (C1) ;(11101001) (351) (233) (E9) ;(01001011) (113) (75) (4B) ;(00000110) (6) (6) (06) ;(01010011) (123) (83) (53) ;(00001000) (10) (8) (08) ;(01010000) (120) (80) (50) ;(00001010) (12) (10) (0A) ; -;6016;(00000000) (0) (0) (00) ;(00011110) (36) (30) (1E) ;(00000001) (1) (1) (01) ;(00011000) (30) (24) (18) ;(00000110) (6) (6) (06) ;(00011110) (36) (30) (1E) ;(00000110) (6) (6) (06) ;(00011000) (30) (24) (18) ; -;6024;(00000010) (2) (2) (02) ;(00011110) (36) (30) (1E) ;(00010000) (20) (16) (10) ;(00001011) (13) (11) (0B) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00100000) (40) (32) (20) ;(11010101) (325) (213) (D5) ; -;6032;(01010111) (127) (87) (57) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(00011000) (30) (24) (18) ;(10010000) (220) (144) (90) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ;(00111111) (77) (63) (3F) ; -;6040;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000010) (2) (2) (02) ;(00010000) (20) (16) (10) ;(11001101) (315) (205) (CD) ;(10101111) (257) (175) (AF) ;(00001101) (15) (13) (0D) ; -;6048;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(11000110) (306) (198) (C6) ;(11111101) (375) (253) (FD) ;(01000110) (106) (70) (46) ;(00110001) (61) (49) (31) ;(11001101) (315) (205) (CD) ; -;6056;(01000100) (104) (68) (44) ;(00001110) (16) (14) (0E) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10000110) (206) (134) (86) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;6064;(00110000) (60) (48) (30) ;(11000110) (306) (198) (C6) ;(00101010) (52) (42) (2A) ;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01101100) (154) (108) (6C) ; -;6072;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00011001) (31) (25) (19) ;(00111000) (70) (56) (38) ;(00100010) (42) (34) (22) ;(11010101) (325) (213) (D5) ; -;6080;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00010001) (21) (17) (11) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ; -;6088;(01010010) (122) (82) (52) ;(11100011) (343) (227) (E3) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ; -;6096;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(00001001) (11) (9) (09) ;(00111000) (70) (56) (38) ;(00001110) (16) (14) (0E) ;(11101011) (353) (235) (EB) ;(01010110) (126) (86) (56) ; -;6104;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(00101011) (53) (43) (2B) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(01101100) (154) (108) (6C) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ; -;6112;(11101101) (355) (237) (ED) ;(00100010) (42) (34) (22) ;(01101100) (154) (108) (6C) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01101100) (154) (108) (6C) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ; -;6120;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(00110011) (63) (51) (33) ;(00011000) (30) (24) (18) ; -;6128;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10100110) (246) (166) (A6) ;(11001001) (311) (201) (C9) ;(00111110) (76) (62) (3E) ;(00000011) (3) (3) (03) ;(00011000) (30) (24) (18) ; -;6136;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(00000010) (2) (2) (02) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00000010) (2) (2) (02) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ; -;6144;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11011111) (337) (223) (DF) ;(11001101) (315) (205) (CD) ;(01110000) (160) (112) (70) ; -;6152;(00100000) (40) (32) (20) ;(00111000) (70) (56) (38) ;(00010100) (24) (20) (14) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00111011) (73) (59) (3B) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ; -;6160;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ; -;6168;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(11100110) (346) (230) (E6) ;(00011100) (34) (28) (1C) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ; -;6176;(11011110) (336) (222) (DE) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001101) (315) (205) (CD) ;(10110111) (267) (183) (B7) ;(00111100) (74) (60) (3C) ; -;6184;(01111000) (170) (120) (78) ;(11100110) (346) (230) (E6) ;(00111111) (77) (63) (3F) ;(01100111) (147) (103) (67) ;(01101001) (151) (105) (69) ;(00100010) (42) (34) (22) ;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ; -;6192;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00011110) (36) (30) (1E) ;(00000001) (1) (1) (01) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00011000) (30) (24) (18) ; -;6200;(11010111) (327) (215) (D7) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(01100110) (146) (102) (66) ;(00101000) (50) (40) (28) ;(11110110) (366) (246) (F6) ;(00111010) (72) (58) (3A) ; -;6208;(01101011) (153) (107) (6B) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(10010110) (226) (150) (96) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ;(11101110) (356) (238) (EE) ;(10101011) (253) (171) (AB) ; -;6216;(11001000) (310) (200) (C8) ;(11100101) (345) (229) (E5) ;(11010101) (325) (213) (D5) ;(00100001) (41) (33) (21) ;(01101100) (154) (108) (6C) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00001111) (17) (15) (0F) ; -;6224;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ;(11100000) (340) (224) (E0) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01001001) (111) (73) (49) ; -;6232;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00011001) (31) (25) (19) ;(00010110) (26) (22) (16) ;(00111110) (76) (62) (3E) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ; -;6240;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(00010011) (23) (19) (13) ;(11111101) (375) (253) (FD) ;(01110011) (163) (115) (73) ;(00101101) (55) (45) (2D) ; -;6248;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(01000000) (100) (64) (40) ;(11000001) (301) (193) (C1) ;(11010000) (320) (208) (D0) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ; -;6256;(00011010) (32) (26) (1A) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10000110) (206) (134) (86) ; -;6264;(01111010) (172) (122) (7A) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ;(11010111) (327) (215) (D7) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;6272;(11000110) (306) (198) (C6) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(10010110) (226) (150) (96) ;(11001101) (315) (205) (CD) ; -;6280;(00110110) (66) (54) (36) ;(00111001) (71) (57) (39) ;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(01100000) (140) (96) (60) ; -;6288;(01101001) (151) (105) (69) ;(11000011) (303) (195) (C3) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00101010) (52) (42) (2A) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ; -;6296;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ;(00111110) (76) (62) (3E) ;(00111111) (77) (63) (3F) ;(11001101) (315) (205) (CD) ;(11000001) (301) (193) (C1) ; -;6304;(00011000) (30) (24) (18) ;(11001101) (315) (205) (CD) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ;(11101011) (353) (235) (EB) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(10110110) (266) (182) (B6) ; -;6312;(00011000) (30) (24) (18) ;(00100011) (43) (35) (23) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ; -;6320;(00110111) (67) (55) (37) ;(00011001) (31) (25) (19) ;(00011000) (30) (24) (18) ;(11100000) (340) (224) (E0) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ; -;6328;(11000000) (300) (192) (C0) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ; -;6336;(11001001) (311) (201) (C9) ;(11011001) (331) (217) (D9) ;(00101010) (52) (42) (2A) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(11001011) (313) (203) (CB) ;(10111100) (274) (188) (BC) ; -;6344;(11001011) (313) (203) (CB) ;(11111101) (375) (253) (FD) ;(00100010) (42) (34) (22) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ; -;6352;(01010110) (126) (86) (56) ;(11010101) (325) (213) (D5) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00001001) (11) (9) (09) ;(11100001) (341) (225) (E1) ; -;6360;(11111101) (375) (253) (FD) ;(01110100) (164) (116) (74) ;(01010111) (127) (87) (57) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ; -;6368;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11000000) (300) (192) (C0) ; -;6376;(00111010) (72) (58) (3A) ;(01000001) (101) (65) (41) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(00000111) (7) (7) (07) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11000110) (306) (198) (C6) ; -;6384;(01000011) (103) (67) (43) ;(00011000) (30) (24) (18) ;(00010110) (26) (22) (16) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10011110) (236) (158) (9E) ; -;6392;(00111110) (76) (62) (3E) ;(01001011) (113) (75) (4B) ;(11001011) (313) (203) (CB) ;(01010110) (126) (86) (56) ;(00101000) (50) (40) (28) ;(00001011) (13) (11) (0B) ;(11001011) (313) (203) (CB) ;(11011110) (336) (222) (DE) ; -;6400;(00111100) (74) (60) (3C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01011110) (136) (94) (5E) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ; -;6408;(01000011) (103) (67) (43) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11000001) (301) (193) (C1) ;(00011000) (30) (24) (18) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(01011110) (136) (94) (5E) ; -;6416;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(11100101) (345) (229) (E5) ;(11101011) (353) (235) (EB) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ; -;6424;(11001101) (315) (205) (CD) ;(10010101) (225) (149) (95) ;(00010110) (26) (22) (16) ;(11100001) (341) (225) (E1) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ; -;6432;(11000000) (300) (192) (C0) ;(01110010) (162) (114) (72) ;(00101011) (53) (43) (2B) ;(01110011) (163) (115) (73) ;(11001001) (311) (201) (C9) ;(01111011) (173) (123) (7B) ;(10100111) (247) (167) (A7) ;(11111000) (370) (248) (F8) ; -;6440;(00011000) (30) (24) (18) ;(00001101) (15) (13) (0D) ;(10101111) (257) (175) (AF) ;(00001001) (11) (9) (09) ;(00111100) (74) (60) (3C) ;(00111000) (70) (56) (38) ;(11111100) (374) (252) (FC) ;(11101101) (355) (237) (ED) ; -;6448;(01000010) (102) (66) (42) ;(00111101) (75) (61) (3D) ;(00101000) (50) (40) (28) ;(11110001) (361) (241) (F1) ;(11000011) (303) (195) (C3) ;(11101111) (357) (239) (EF) ;(00010101) (25) (21) (15) ;(11001101) (315) (205) (CD) ; -;6456;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00111000) (70) (56) (38) ;(00101100) (54) (44) (2C) ; -;6464;(11001101) (315) (205) (CD) ;(00110110) (66) (54) (36) ;(00111001) (71) (57) (39) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(11001011) (313) (203) (CB) ;(00101000) (50) (40) (28) ;(00100100) (44) (36) (24) ; -;6472;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ; -;6480;(00100000) (40) (32) (20) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01010110) (126) (86) (56) ;(00101000) (50) (40) (28) ;(00010100) (24) (20) (14) ; -;6488;(00011000) (30) (24) (18) ;(00001110) (16) (14) (0E) ;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(00001010) (12) (10) (0A) ;(11110101) (365) (245) (F5) ;(00111010) (72) (58) (3A) ; -;6496;(01101010) (152) (106) (6A) ;(01011100) (134) (92) (5C) ;(11101110) (356) (238) (EE) ;(00000100) (4) (4) (04) ;(00110010) (62) (50) (32) ;(01101010) (152) (106) (6A) ;(01011100) (134) (92) (5C) ;(11110001) (361) (241) (F1) ; -;6504;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11010110) (326) (214) (D6) ;(11010111) (327) (215) (D7) ;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ; -;6512;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(01010100) (124) (84) (54) ;(01011101) (135) (93) (5D) ;(11000001) (301) (193) (C1) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00011001) (31) (25) (19) ; -;6520;(11010000) (320) (208) (D0) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(00011000) (30) (24) (18) ;(11110100) (364) (244) (F4) ; -;6528;(01111110) (176) (126) (7E) ;(10111000) (270) (184) (B8) ;(11000000) (300) (192) (C0) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(00101011) (53) (43) (2B) ;(10111001) (271) (185) (B9) ;(11001001) (311) (201) (C9) ; -;6536;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ; -;6544;(00010101) (25) (21) (15) ;(11001000) (310) (200) (C8) ;(11100111) (347) (231) (E7) ;(10111011) (273) (187) (BB) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(10100111) (247) (167) (A7) ;(11001001) (311) (201) (C9) ; -;6552;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(10110110) (266) (182) (B6) ;(00011000) (30) (24) (18) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ; -;6560;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00001101) (15) (13) (0D) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(00101000) (50) (40) (28) ; -;6568;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(11001011) (313) (203) (CB) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11001011) (313) (203) (CB) ;(01000001) (101) (65) (41) ;(00101000) (50) (40) (28) ; -;6576;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(11100011) (343) (227) (E3) ;(00010101) (25) (21) (15) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ; -;6584;(11100101) (345) (229) (E5) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(01000000) (100) (64) (40) ;(00111000) (70) (56) (38) ;(00010111) (27) (23) (17) ;(11001011) (313) (203) (CB) ;(01101111) (157) (111) (6F) ; -;6592;(00101000) (50) (40) (28) ;(00010100) (24) (20) (14) ;(10000111) (207) (135) (87) ;(11111010) (372) (250) (FA) ;(11000111) (307) (199) (C7) ;(00011001) (31) (25) (19) ;(00111111) (77) (63) (3F) ;(00000001) (1) (1) (01) ; -;6600;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(00001110) (16) (14) (0E) ;(00010010) (22) (18) (12) ;(00010111) (27) (23) (17) ;(00100011) (43) (35) (23) ; -;6608;(01111110) (176) (126) (7E) ;(00110000) (60) (48) (30) ;(11111011) (373) (251) (FB) ;(00011000) (30) (24) (18) ;(00000110) (6) (6) (06) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ; -;6616;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(00100011) (43) (35) (23) ;(00001001) (11) (9) (09) ;(11010001) (321) (209) (D1) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;6624;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11011101) (335) (221) (DD) ;(00011001) (31) (25) (19) ; -;6632;(11000101) (305) (197) (C5) ;(01111000) (170) (120) (78) ;(00101111) (57) (47) (2F) ;(01000111) (107) (71) (47) ;(01111001) (171) (121) (79) ;(00101111) (57) (47) (2F) ;(01001111) (117) (79) (4F) ;(00000011) (3) (3) (03) ; -;6640;(11001101) (315) (205) (CD) ;(01100100) (144) (100) (64) ;(00010110) (26) (22) (16) ;(11101011) (353) (235) (EB) ;(11100001) (341) (225) (E1) ;(00011001) (31) (25) (19) ;(11010101) (325) (213) (D5) ;(11101101) (355) (237) (ED) ; -;6648;(10110000) (260) (176) (B0) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ; -;6656;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11100111) (347) (231) (E7) ;(00100001) (41) (33) (21) ;(10010010) (222) (146) (92) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ; -;6664;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00101101) (55) (45) (2D) ;(11001101) (315) (205) (CD) ;(10100010) (242) (162) (A2) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ; -;6672;(00000100) (4) (4) (04) ;(00100001) (41) (33) (21) ;(11110000) (360) (240) (F0) ;(11011000) (330) (216) (D8) ;(00001001) (11) (9) (09) ;(11011010) (332) (218) (DA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;6680;(11000011) (303) (195) (C3) ;(11000101) (305) (197) (C5) ;(00010110) (26) (22) (16) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(10101111) (257) (175) (AF) ;(11001011) (313) (203) (CB) ;(01111000) (170) (120) (78) ; -;6688;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(00011110) (36) (30) (1E) ;(11111111) (377) (255) (FF) ;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ; -;6696;(11010101) (325) (213) (D5) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(11100101) (345) (229) (E5) ;(11101011) (353) (235) (EB) ;(00011110) (36) (30) (1E) ;(00100000) (40) (32) (20) ; -;6704;(00000001) (1) (1) (01) ;(00011000) (30) (24) (18) ;(11111100) (374) (252) (FC) ;(11001101) (315) (205) (CD) ;(00101010) (52) (42) (2A) ;(00011001) (31) (25) (19) ;(00000001) (1) (1) (01) ;(10011100) (234) (156) (9C) ; -;6712;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(00101010) (52) (42) (2A) ;(00011001) (31) (25) (19) ;(00001110) (16) (14) (0E) ;(11110110) (366) (246) (F6) ;(11001101) (315) (205) (CD) ;(00101010) (52) (42) (2A) ; -;6720;(00011001) (31) (25) (19) ;(01111101) (175) (125) (7D) ;(11001101) (315) (205) (CD) ;(11101111) (357) (239) (EF) ;(00010101) (25) (21) (15) ;(11100001) (341) (225) (E1) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ; -;6728;(10110001) (261) (177) (B1) ;(11001011) (313) (203) (CB) ;(10111100) (274) (188) (BC) ;(10111111) (277) (191) (BF) ;(11000100) (304) (196) (C4) ;(10101111) (257) (175) (AF) ;(10110100) (264) (180) (B4) ;(10010011) (223) (147) (93) ; -;6736;(10010001) (221) (145) (91) ;(10010010) (222) (146) (92) ;(10010101) (225) (149) (95) ;(10011000) (230) (152) (98) ;(10011000) (230) (152) (98) ;(10011000) (230) (152) (98) ;(10011000) (230) (152) (98) ;(10011000) (230) (152) (98) ; -;6744;(10011000) (230) (152) (98) ;(10011000) (230) (152) (98) ;(01111111) (177) (127) (7F) ;(10000001) (201) (129) (81) ;(00101110) (56) (46) (2E) ;(01101100) (154) (108) (6C) ;(01101110) (156) (110) (6E) ;(01110000) (160) (112) (70) ; -;6752;(01001000) (110) (72) (48) ;(10010100) (224) (148) (94) ;(01010110) (126) (86) (56) ;(00111111) (77) (63) (3F) ;(01000001) (101) (65) (41) ;(00101011) (53) (43) (2B) ;(00010111) (27) (23) (17) ;(00011111) (37) (31) (1F) ; -;6760;(00110111) (67) (55) (37) ;(01110111) (167) (119) (77) ;(01000100) (104) (68) (44) ;(00001111) (17) (15) (0F) ;(01011001) (131) (89) (59) ;(00101011) (53) (43) (2B) ;(01000011) (103) (67) (43) ;(00101101) (55) (45) (2D) ; -;6768;(01010001) (121) (81) (51) ;(00111010) (72) (58) (3A) ;(01101101) (155) (109) (6D) ;(01000010) (102) (66) (42) ;(00001101) (15) (13) (0D) ;(01001001) (111) (73) (49) ;(01011100) (134) (92) (5C) ;(01000100) (104) (68) (44) ; -;6776;(00010101) (25) (21) (15) ;(01011101) (135) (93) (5D) ;(00000001) (1) (1) (01) ;(00111101) (75) (61) (3D) ;(00000010) (2) (2) (02) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(01100111) (147) (103) (67) ; -;6784;(00011110) (36) (30) (1E) ;(00000110) (6) (6) (06) ;(11001011) (313) (203) (CB) ;(00000101) (5) (5) (05) ;(11110000) (360) (240) (F0) ;(00011100) (34) (28) (1C) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;6792;(11101101) (355) (237) (ED) ;(00011110) (36) (30) (1E) ;(00000000) (0) (0) (00) ;(00100100) (44) (36) (24) ;(00111001) (71) (57) (39) ;(00000000) (0) (0) (00) ;(00100011) (43) (35) (23) ;(00011111) (37) (31) (1F) ; -;6800;(00000100) (4) (4) (04) ;(00111101) (75) (61) (3D) ;(00000110) (6) (6) (06) ;(11001100) (314) (204) (CC) ;(00000110) (6) (6) (06) ;(00000101) (5) (5) (05) ;(00000011) (3) (3) (03) ;(00011101) (35) (29) (1D) ; -;6808;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(10101011) (253) (171) (AB) ;(00011101) (35) (29) (1D) ;(00000101) (5) (5) (05) ;(11001101) (315) (205) (CD) ;(00011111) (37) (31) (1F) ;(00000101) (5) (5) (05) ; -;6816;(10001001) (211) (137) (89) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ;(00000010) (2) (2) (02) ;(00101100) (54) (44) (2C) ;(00000101) (5) (5) (05) ;(10100111) (247) (167) (A7) ;(00111001) (71) (57) (39) ; -;6824;(00000000) (0) (0) (00) ;(10110111) (267) (183) (B7) ;(00010001) (21) (17) (11) ;(00000011) (3) (3) (03) ;(10100001) (241) (161) (A1) ;(00011110) (36) (30) (1E) ;(00000101) (5) (5) (05) ;(11111001) (371) (249) (F9) ; -;6832;(00010111) (27) (23) (17) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00011110) (36) (30) (1E) ;(00000011) (3) (3) (03) ;(01001111) (117) (79) (4F) ;(00011110) (36) (30) (1E) ; -;6840;(00000000) (0) (0) (00) ;(01011111) (137) (95) (5F) ;(00011110) (36) (30) (1E) ;(00000011) (3) (3) (03) ;(10101100) (254) (172) (AC) ;(00011110) (36) (30) (1E) ;(00000000) (0) (0) (00) ;(01101011) (153) (107) (6B) ; -;6848;(00001101) (15) (13) (0D) ;(00001001) (11) (9) (09) ;(00000000) (0) (0) (00) ;(11011100) (334) (220) (DC) ;(00100010) (42) (34) (22) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00111010) (72) (58) (3A) ; -;6856;(00011111) (37) (31) (1F) ;(00000101) (5) (5) (05) ;(11101101) (355) (237) (ED) ;(00011101) (35) (29) (1D) ;(00000101) (5) (5) (05) ;(00100111) (47) (39) (27) ;(00011110) (36) (30) (1E) ;(00000011) (3) (3) (03) ; -;6864;(01000010) (102) (66) (42) ;(00011110) (36) (30) (1E) ;(00001001) (11) (9) (09) ;(00000101) (5) (5) (05) ;(10000010) (202) (130) (82) ;(00100011) (43) (35) (23) ;(00000000) (0) (0) (00) ;(10101100) (254) (172) (AC) ; -;6872;(00001110) (16) (14) (0E) ;(00000101) (5) (5) (05) ;(11001001) (311) (201) (C9) ;(00011111) (37) (31) (1F) ;(00000101) (5) (5) (05) ;(11110101) (365) (245) (F5) ;(00010111) (27) (23) (17) ;(00001011) (13) (11) (0B) ; -;6880;(00001011) (13) (11) (0B) ;(00001011) (13) (11) (0B) ;(00001011) (13) (11) (0B) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(11111000) (370) (248) (F8) ;(00000011) (3) (3) (03) ;(00001001) (11) (9) (09) ; -;6888;(00000101) (5) (5) (05) ;(00100000) (40) (32) (20) ;(00100011) (43) (35) (23) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ; -;6896;(00000111) (7) (7) (07) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(01111010) (172) (122) (7A) ;(00011110) (36) (30) (1E) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(10010100) (224) (148) (94) ; -;6904;(00100010) (42) (34) (22) ;(00000101) (5) (5) (05) ;(01100000) (140) (96) (60) ;(00011111) (37) (31) (1F) ;(00000110) (6) (6) (06) ;(00101100) (54) (44) (2C) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ; -;6912;(00110110) (66) (54) (36) ;(00010111) (27) (23) (17) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11100101) (345) (229) (E5) ;(00010110) (26) (22) (16) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ; -;6920;(10010011) (223) (147) (93) ;(00010111) (27) (23) (17) ;(00001010) (12) (10) (0A) ;(00101100) (54) (44) (2C) ;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ;(10010011) (223) (147) (93) ;(00010111) (27) (23) (17) ; -;6928;(00001010) (12) (10) (0A) ;(00000000) (0) (0) (00) ;(10010011) (223) (147) (93) ;(00010111) (27) (23) (17) ;(00000000) (0) (0) (00) ;(10010011) (223) (147) (93) ;(00010111) (27) (23) (17) ;(11111101) (375) (253) (FD) ; -;6936;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10111110) (276) (190) (BE) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00011001) (31) (25) (19) ;(10101111) (257) (175) (AF) ;(00110010) (62) (50) (32) ; -;6944;(01000111) (107) (71) (47) ;(01011100) (134) (92) (5C) ;(00111101) (75) (61) (3D) ;(00110010) (62) (50) (32) ;(00111010) (72) (58) (3A) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00000001) (1) (1) (01) ; -;6952;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(00001101) (15) (13) (0D) ;(11111010) (372) (250) (FA) ; -;6960;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11011111) (337) (223) (DF) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ; -;6968;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(00101000) (50) (40) (28) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(01110110) (166) (118) (76) ;(00011011) (33) (27) (1B) ; -;6976;(11100101) (345) (229) (E5) ;(01001111) (117) (79) (4F) ;(11100111) (347) (231) (E7) ;(01111001) (171) (121) (79) ;(11010110) (326) (214) (D6) ;(11001110) (316) (206) (CE) ;(11011010) (332) (218) (DA) ;(10001010) (212) (138) (8A) ; -;6984;(00011100) (34) (28) (1C) ;(01001111) (117) (79) (4F) ;(00100001) (41) (33) (21) ;(01001000) (110) (72) (48) ;(00011010) (32) (26) (1A) ;(00001001) (11) (9) (09) ;(01001110) (116) (78) (4E) ;(00001001) (11) (9) (09) ; -;6992;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(00101010) (52) (42) (2A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ; -;7000;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(00000001) (1) (1) (01) ;(01010010) (122) (82) (52) ;(00011011) (33) (27) (1B) ;(11000101) (305) (197) (C5) ;(01001111) (117) (79) (4F) ;(11111110) (376) (254) (FE) ; -;7008;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00001100) (14) (12) (0C) ;(00100001) (41) (33) (21) ;(00000001) (1) (1) (01) ;(00011100) (34) (28) (1C) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;7016;(00001001) (11) (9) (09) ;(01001110) (116) (78) (4E) ;(00001001) (11) (9) (09) ;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(00000101) (5) (5) (05) ;(11001001) (311) (201) (C9) ;(11011111) (337) (223) (DF) ; -;7024;(10111001) (271) (185) (B9) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(01010100) (124) (84) (54) ; -;7032;(00011111) (37) (31) (1F) ;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00010100) (24) (20) (14) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00001010) (12) (10) (0A) ; -;7040;(01111110) (176) (126) (7E) ;(00100000) (40) (32) (20) ;(01110001) (161) (113) (71) ;(00101010) (52) (42) (2A) ;(01000010) (102) (66) (42) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(01111100) (174) (124) (7C) ; -;7048;(00101000) (50) (40) (28) ;(00010100) (24) (20) (14) ;(00100001) (41) (33) (21) ;(11111110) (376) (254) (FE) ;(11111111) (377) (255) (FF) ;(00100010) (42) (34) (22) ;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ; -;7056;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ; -;7064;(00011011) (33) (27) (1B) ;(00111010) (72) (58) (3A) ;(01000100) (104) (68) (44) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00110011) (63) (51) (33) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ; -;7072;(00011001) (31) (25) (19) ;(00111010) (72) (58) (3A) ;(01000100) (104) (68) (44) ;(01011100) (134) (92) (5C) ;(00101000) (50) (40) (28) ;(00011001) (31) (25) (19) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ; -;7080;(01000011) (103) (67) (43) ;(01000111) (107) (71) (47) ;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(11000000) (300) (192) (C0) ;(01111000) (170) (120) (78) ;(00101000) (50) (40) (28) ;(00001111) (17) (15) (0F) ; -;7088;(11001111) (317) (207) (CF) ;(11111111) (377) (255) (FF) ;(11000001) (301) (193) (C1) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11001000) (310) (200) (C8) ;(00101010) (52) (42) (2A) ; -;7096;(01010101) (125) (85) (55) ;(01011100) (134) (92) (5C) ;(00111110) (76) (62) (3E) ;(11000000) (300) (192) (C0) ;(10100110) (246) (166) (A6) ;(11000000) (300) (192) (C0) ;(10101111) (257) (175) (AF) ;(11111110) (376) (254) (FE) ; -;7104;(00000001) (1) (1) (01) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ; -;7112;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(11101011) (353) (235) (EB) ;(00011001) (31) (25) (19) ; -;7120;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01010101) (125) (85) (55) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ; -;7128;(01010111) (127) (87) (57) ;(00011110) (36) (30) (1E) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00001010) (12) (10) (0A) ;(11111111) (377) (255) (FF) ;(00010101) (25) (21) (15) ; -;7136;(11111101) (375) (253) (FD) ;(01110010) (162) (114) (72) ;(00001101) (15) (13) (0D) ;(11001010) (312) (202) (CA) ;(00101000) (50) (40) (28) ;(00011011) (33) (27) (1B) ;(00010100) (24) (20) (14) ;(11001101) (315) (205) (CD) ; -;7144;(10001011) (213) (139) (8B) ;(00011001) (31) (25) (19) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(11001111) (317) (207) (CF) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ; -;7152;(00100101) (45) (37) (25) ;(11000000) (300) (192) (C0) ;(11000001) (301) (193) (C1) ;(11000001) (301) (193) (C1) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ; -;7160;(10111010) (272) (186) (BA) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(11001010) (312) (202) (CA) ;(00101000) (50) (40) (28) ;(00011011) (33) (27) (1B) ;(11000011) (303) (195) (C3) ;(10001010) (212) (138) (8A) ; -;7168;(00011100) (34) (28) (1C) ;(00001111) (17) (15) (0F) ;(00011101) (35) (29) (1D) ;(01001011) (113) (75) (4B) ;(00001001) (11) (9) (09) ;(01100111) (147) (103) (67) ;(00001011) (13) (11) (0B) ;(01111011) (173) (123) (7B) ; -;7176;(10001110) (216) (142) (8E) ;(01110001) (161) (113) (71) ;(10110100) (264) (180) (B4) ;(10000001) (201) (129) (81) ;(11001111) (317) (207) (CF) ;(11001101) (315) (205) (CD) ;(11011110) (336) (222) (DE) ;(00011100) (34) (28) (1C) ; -;7184;(10111111) (277) (191) (BF) ;(11000001) (301) (193) (C1) ;(11001100) (314) (204) (CC) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01110100) (164) (116) (74) ; -;7192;(01011100) (134) (92) (5C) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11101011) (353) (235) (EB) ;(11000101) (305) (197) (C5) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ; -;7200;(10110010) (262) (178) (B2) ;(00101000) (50) (40) (28) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ; -;7208;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(11001110) (316) (206) (CE) ;(00100000) (40) (32) (20) ;(00011000) (30) (24) (18) ;(11001111) (317) (207) (CF) ;(00000001) (1) (1) (01) ; -;7216;(11001100) (314) (204) (CC) ;(10010110) (226) (150) (96) ;(00101001) (51) (41) (29) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ;(00100000) (40) (32) (20) ; -;7224;(00001101) (15) (13) (0D) ;(10101111) (257) (175) (AF) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ; -;7232;(00100001) (41) (33) (21) ;(01110001) (161) (113) (71) ;(01011100) (134) (92) (5C) ;(10110110) (266) (182) (B6) ;(01110111) (167) (119) (77) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ; -;7240;(01110010) (162) (114) (72) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11000001) (301) (193) (C1) ;(11001101) (315) (205) (CD) ; -;7248;(01010110) (126) (86) (56) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001001) (311) (201) (C9) ;(00111010) (72) (58) (3A) ;(00111011) (73) (59) (3B) ; -;7256;(01011100) (134) (92) (5C) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11110001) (361) (241) (F1) ;(11111101) (375) (253) (FD) ;(01010110) (126) (86) (56) ; -;7264;(00000001) (1) (1) (01) ;(10101010) (252) (170) (AA) ;(11100110) (346) (230) (E6) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100100) (44) (36) (24) ;(11001011) (313) (203) (CB) ;(01111010) (172) (122) (7A) ; -;7272;(11000010) (302) (194) (C2) ;(11111111) (377) (255) (FF) ;(00101010) (52) (42) (2A) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101000) (50) (40) (28) ;(11110101) (365) (245) (F5) ; -;7280;(01111001) (171) (121) (79) ;(11110110) (366) (246) (F6) ;(10011111) (237) (159) (9F) ;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ;(00010100) (24) (20) (14) ;(11110001) (361) (241) (F1) ;(00011000) (30) (24) (18) ; -;7288;(10101001) (251) (169) (A9) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ; -;7296;(00001001) (11) (9) (09) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;7304;(01110110) (166) (118) (76) ;(11000000) (300) (192) (C0) ;(11001111) (317) (207) (CF) ;(00001011) (13) (11) (0B) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11111101) (375) (253) (FD) ; -;7312;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ;(11001000) (310) (200) (C8) ;(00011000) (30) (24) (18) ;(11110100) (364) (244) (F4) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;7320;(00000001) (1) (1) (01) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11000100) (304) (196) (C4) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ; -;7328;(00000000) (0) (0) (00) ;(11110001) (361) (241) (F1) ;(00111010) (72) (58) (3A) ;(01110100) (164) (116) (74) ;(01011100) (134) (92) (5C) ;(11010110) (326) (214) (D6) ;(00010011) (23) (19) (13) ;(11001101) (315) (205) (CD) ; -;7336;(11111100) (374) (252) (FC) ;(00100001) (41) (33) (21) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(00101010) (52) (42) (2A) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ; -;7344;(00100010) (42) (34) (22) ;(10001101) (215) (141) (8D) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(00000111) (7) (7) (07) ; -;7352;(10101110) (256) (174) (AE) ;(11100110) (346) (230) (E6) ;(10101010) (252) (170) (AA) ;(10101110) (256) (174) (AE) ;(01110111) (167) (119) (77) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ; -;7360;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00010011) (23) (19) (13) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ; -;7368;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00100001) (41) (33) (21) ;(10010000) (220) (144) (90) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11110110) (366) (246) (F6) ;(11111000) (370) (248) (F8) ; -;7376;(01110111) (167) (119) (77) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ;(10110110) (266) (182) (B6) ;(11011111) (337) (223) (DF) ;(11001101) (315) (205) (CD) ;(11100010) (342) (226) (E2) ; -;7384;(00100001) (41) (33) (21) ;(00011000) (30) (24) (18) ;(10011111) (237) (159) (9F) ;(11000011) (303) (195) (C3) ;(00000101) (5) (5) (05) ;(00000110) (6) (6) (06) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ; -;7392;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(00100000) (40) (32) (20) ;(10011100) (234) (156) (9C) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ; -;7400;(00100101) (45) (37) (25) ;(11001000) (310) (200) (C8) ;(11101111) (357) (239) (EF) ;(10100000) (240) (160) (A0) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11001111) (317) (207) (CF) ;(00001000) (10) (8) (08) ; -;7408;(11000001) (301) (193) (C1) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ; -;7416;(00111000) (70) (56) (38) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(11011010) (332) (218) (DA) ;(10110011) (263) (179) (B3) ;(00011011) (33) (27) (1B) ; -;7424;(11000011) (303) (195) (C3) ;(00101001) (51) (41) (29) ;(00011011) (33) (27) (1B) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ;(00100000) (40) (32) (20) ;(00001001) (11) (9) (09) ;(11100111) (347) (231) (E7) ; -;7432;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(00011000) (30) (24) (18) ;(00000110) (6) (6) (06) ; -;7440;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11101111) (357) (239) (EF) ;(10100001) (241) (161) (A1) ;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(11000000) (300) (192) (C0) ; -;7448;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(11100000) (340) (224) (E0) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11111111) (377) (255) (FF) ;(00101010) (52) (42) (2A) ; -;7456;(00100010) (42) (34) (22) ;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(01111110) (176) (126) (7E) ;(11001011) (313) (203) (CB) ;(11111110) (376) (254) (FE) ;(00000001) (1) (1) (01) ; -;7464;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(00000111) (7) (7) (07) ;(00111000) (70) (56) (38) ;(00000110) (6) (6) (06) ;(00001110) (16) (14) (0E) ;(00001101) (15) (13) (0D) ; -;7472;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ; -;7480;(00111000) (70) (56) (38) ;(11100001) (341) (225) (E1) ;(11101011) (353) (235) (EB) ;(00001110) (16) (14) (0E) ;(00001010) (12) (10) (0A) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00101010) (52) (42) (2A) ; -;7488;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(11111101) (375) (253) (FD) ;(01010110) (126) (86) (56) ; -;7496;(00001101) (15) (13) (0D) ;(00010100) (24) (20) (14) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(11001101) (315) (205) (CD) ;(11011010) (332) (218) (DA) ;(00011101) (35) (29) (1D) ;(11010000) (320) (208) (D0) ; -;7504;(11111101) (375) (253) (FD) ;(01000110) (106) (70) (46) ;(00111000) (70) (56) (38) ;(00101010) (52) (42) (2A) ;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01000010) (102) (66) (42) ; -;7512;(01011100) (134) (92) (5C) ;(00111010) (72) (58) (3A) ;(01000111) (107) (71) (47) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(01010111) (127) (87) (57) ;(00101010) (52) (42) (2A) ; -;7520;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00011110) (36) (30) (1E) ;(11110011) (363) (243) (F3) ;(11000101) (305) (197) (C5) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01010101) (125) (85) (55) ; -;7528;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10000110) (206) (134) (86) ;(00011101) (35) (29) (1D) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01010101) (125) (85) (55) ;(01011100) (134) (92) (5C) ; -;7536;(11000001) (301) (193) (C1) ;(00111000) (70) (56) (38) ;(00010001) (21) (17) (11) ;(11100111) (347) (231) (E7) ;(11110110) (366) (246) (F6) ;(00100000) (40) (32) (20) ;(10111000) (270) (184) (B8) ;(00101000) (50) (40) (28) ; -;7544;(00000011) (3) (3) (03) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11101000) (350) (232) (E8) ;(11100111) (347) (231) (E7) ;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(10010010) (222) (146) (92) ; -;7552;(00110010) (62) (50) (32) ;(01000100) (104) (68) (44) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11001111) (317) (207) (CF) ;(00010001) (21) (17) (11) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ; -;7560;(00111010) (72) (58) (3A) ;(00101000) (50) (40) (28) ;(00011000) (30) (24) (18) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(11000000) (300) (192) (C0) ;(00110111) (67) (55) (37) ; -;7568;(11000000) (300) (192) (C0) ;(01000110) (106) (70) (46) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01000010) (102) (66) (42) ;(01011100) (134) (92) (5C) ; -;7576;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11100101) (345) (229) (E5) ;(00001001) (11) (9) (09) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ; -;7584;(11100001) (341) (225) (E1) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10001011) (213) (139) (8B) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ; -;7592;(11010000) (320) (208) (D0) ;(00011000) (30) (24) (18) ;(11100000) (340) (224) (E0) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01001110) (116) (78) (4E) ;(11000010) (302) (194) (C2) ; -;7600;(00101110) (56) (46) (2E) ;(00011100) (34) (28) (1C) ;(00101010) (52) (42) (2A) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ; -;7608;(00011111) (37) (31) (1F) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(11101111) (357) (239) (EF) ;(11100000) (340) (224) (E0) ;(11100010) (342) (226) (E2) ; -;7616;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11011010) (332) (218) (DA) ;(00011101) (35) (29) (1D) ;(11011000) (330) (216) (D8) ; -;7624;(00101010) (52) (42) (2A) ;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(00001111) (17) (15) (0F) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(01011110) (136) (94) (5E) ; -;7632;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01100110) (146) (102) (66) ;(11101011) (353) (235) (EB) ;(11000011) (303) (195) (C3) ;(01110011) (163) (115) (73) ;(00011110) (36) (30) (1E) ; -;7640;(11001111) (317) (207) (CF) ;(00000000) (0) (0) (00) ;(11101111) (357) (239) (EF) ;(11100001) (341) (225) (E1) ;(11100000) (340) (224) (E0) ;(11100010) (342) (226) (E2) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ; -;7648;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(00000011) (3) (3) (03) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ;(10100111) (247) (167) (A7) ; -;7656;(11001001) (311) (201) (C9) ;(00111000) (70) (56) (38) ;(00110111) (67) (55) (37) ;(11001001) (311) (201) (C9) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(00011111) (37) (31) (1F) ;(00011100) (34) (28) (1C) ; -;7664;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00101001) (51) (41) (29) ;(11011111) (337) (223) (DF) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ; -;7672;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01010111) (127) (87) (57) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ; -;7680;(00001001) (11) (9) (09) ;(00011110) (36) (30) (1E) ;(11100100) (344) (228) (E4) ;(11001101) (315) (205) (CD) ;(10000110) (206) (134) (86) ;(00011101) (35) (29) (1D) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ; -;7688;(11001111) (317) (207) (CF) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(01110111) (167) (119) (77) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(01010110) (126) (86) (56) ;(00011100) (34) (28) (1C) ; -;7696;(11011111) (337) (223) (DF) ;(00100010) (42) (34) (22) ;(01010111) (127) (87) (57) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ; -;7704;(00110110) (66) (54) (36) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(01111000) (170) (120) (78) ;(00000000) (0) (0) (00) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ; -;7712;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ; -;7720;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00100000) (40) (32) (20) ;(00001011) (13) (11) (0B) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11111110) (376) (254) (FE) ; -;7728;(00101100) (54) (44) (2C) ;(11000100) (304) (196) (C4) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11110101) (365) (245) (F5) ;(00111110) (76) (62) (3E) ; -;7736;(11100100) (344) (228) (E4) ;(01000111) (107) (71) (47) ;(11101101) (355) (237) (ED) ;(10111001) (271) (185) (B9) ;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(11000011) (303) (195) (C3) ; -;7744;(10001011) (213) (139) (8B) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(10110111) (267) (183) (B7) ;(00111100) (74) (60) (3C) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(11001101) (315) (205) (CD) ; -;7752;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ;(01010111) (127) (87) (57) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ; -;7760;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ; -;7768;(01111000) (170) (120) (78) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01110110) (166) (118) (76) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ; -;7776;(01101110) (156) (110) (6E) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(01010110) (126) (86) (56) ;(00110110) (66) (54) (36) ;(00011000) (30) (24) (18) ;(00001100) (14) (12) (0C) ;(11001101) (315) (205) (CD) ; -;7784;(10110111) (267) (183) (B7) ;(00111100) (74) (60) (3C) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(11111110) (376) (254) (FE) ; -;7792;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00101100) (54) (44) (2C) ;(00100010) (42) (34) (22) ;(01000010) (102) (66) (42) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(01110010) (162) (114) (72) ; -;7800;(00001010) (12) (10) (0A) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10000101) (205) (133) (85) ;(00011110) (36) (30) (1E) ;(11101101) (355) (237) (ED) ;(01111001) (171) (121) (79) ;(11001001) (311) (201) (C9) ; -;7808;(11001101) (315) (205) (CD) ;(10000101) (205) (133) (85) ;(00011110) (36) (30) (1E) ;(00000010) (2) (2) (02) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ; -;7816;(00111000) (70) (56) (38) ;(00010101) (25) (21) (15) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ; -;7824;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(11110001) (361) (241) (F1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(00011000) (30) (24) (18) ; -;7832;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ;(10100010) (242) (162) (A2) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(00000001) (1) (1) (01) ;(11001000) (310) (200) (C8) ;(11001111) (317) (207) (CF) ; -;7840;(00001010) (12) (10) (0A) ;(11001101) (315) (205) (CD) ;(01100111) (147) (103) (67) ;(00011110) (36) (30) (1E) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ; -;7848;(01000101) (105) (69) (45) ;(00011110) (36) (30) (1E) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(01111000) (170) (120) (78) ; -;7856;(10110001) (261) (177) (B1) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10110010) (262) (178) (B2) ;(01011100) (134) (92) (5C) ;(11000101) (305) (197) (C5) ; -;7864;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01001011) (113) (75) (4B) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;7872;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(01101011) (153) (107) (6B) ;(00001101) (15) (13) (0D) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ; -;7880;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(00110010) (62) (50) (32) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;7888;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(00101010) (52) (42) (2A) ;(10110100) (264) (180) (B4) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;7896;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00010101) (25) (21) (15) ;(11101011) (353) (235) (EB) ;(00100010) (42) (34) (22) ;(10110010) (262) (178) (B2) ;(01011100) (134) (92) (5C) ; -;7904;(11010001) (321) (209) (D1) ;(11000001) (301) (193) (C1) ;(00110110) (66) (54) (36) ;(00111110) (76) (62) (3E) ;(00101011) (53) (43) (2B) ;(11111001) (371) (249) (F9) ;(11000101) (305) (197) (C5) ;(11101101) (355) (237) (ED) ; -;7912;(01110011) (163) (115) (73) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11101011) (353) (235) (EB) ;(11101001) (351) (233) (E9) ;(11010001) (321) (209) (D1) ;(11111101) (375) (253) (FD) ;(01100110) (146) (102) (66) ; -;7920;(00001101) (15) (13) (0D) ;(00100100) (44) (36) (24) ;(11100011) (343) (227) (E3) ;(00110011) (63) (51) (33) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01000101) (105) (69) (45) ;(01011100) (134) (92) (5C) ; -;7928;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ; -;7936;(01100111) (147) (103) (67) ;(00011110) (36) (30) (1E) ;(00000001) (1) (1) (01) ;(00010100) (24) (20) (14) ;(00000000) (0) (0) (00) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ; -;7944;(00001001) (11) (9) (09) ;(00111000) (70) (56) (38) ;(00001010) (12) (10) (0A) ;(11101011) (353) (235) (EB) ;(00100001) (41) (33) (21) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ; -;7952;(00111000) (70) (56) (38) ;(00000011) (3) (3) (03) ;(11101101) (355) (237) (ED) ;(01110010) (162) (114) (72) ;(11011000) (330) (216) (D8) ;(00101110) (56) (46) (2E) ;(00000011) (3) (3) (03) ;(11000011) (303) (195) (C3) ; -;7960;(01010101) (125) (85) (55) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(00000101) (5) (5) (05) ;(00011111) (37) (31) (1F) ; -;7968;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11001001) (311) (201) (C9) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ;(11010001) (321) (209) (D1) ;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ; -;7976;(00111110) (76) (62) (3E) ;(00101000) (50) (40) (28) ;(00001011) (13) (11) (0B) ;(00111011) (73) (59) (3B) ;(11100011) (343) (227) (E3) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ; -;7984;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11000101) (305) (197) (C5) ;(11000011) (303) (195) (C3) ;(01110011) (163) (115) (73) ;(00011110) (36) (30) (1E) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ; -;7992;(11001111) (317) (207) (CF) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(01110110) (166) (118) (76) ;(00001011) (13) (11) (0B) ;(01111000) (170) (120) (78) ; -;8000;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ;(01111000) (170) (120) (78) ;(10100001) (241) (161) (A1) ;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ; -;8008;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01101110) (156) (110) (6E) ;(00101000) (50) (40) (28) ;(11101110) (356) (238) (EE) ;(11111101) (375) (253) (FD) ; -;8016;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10101110) (256) (174) (AE) ;(11001001) (311) (201) (C9) ;(00111110) (76) (62) (3E) ;(01111111) (177) (127) (7F) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ; -;8024;(00011111) (37) (31) (1F) ;(11011000) (330) (216) (D8) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ;(11011011) (333) (219) (DB) ;(11111110) (376) (254) (FE) ;(00011111) (37) (31) (1F) ;(11001001) (311) (201) (C9) ; -;8032;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ;(00111110) (76) (62) (3E) ;(11001110) (316) (206) (CE) ;(11000011) (303) (195) (C3) ; -;8040;(00111001) (71) (57) (39) ;(00011110) (36) (30) (1E) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11110110) (366) (246) (F6) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ; -;8048;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ;(00010110) (26) (22) (16) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ; -;8056;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10110110) (266) (182) (B6) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ; -;8064;(00111100) (74) (60) (3C) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ; -;8072;(00101100) (54) (44) (2C) ;(11010010) (322) (210) (D2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11101011) (353) (235) (EB) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ; -;8080;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11101011) (353) (235) (EB) ;(11100111) (347) (231) (E7) ;(11101011) (353) (235) (EB) ;(00000001) (1) (1) (01) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;8088;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00001110) (16) (14) (0E) ;(11111110) (376) (254) (FE) ; -;8096;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11100000) (340) (224) (E0) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ; -;8104;(00100000) (40) (32) (20) ;(00010011) (23) (19) (13) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ;(11100111) (347) (231) (E7) ; -;8112;(00111010) (72) (58) (3A) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11110001) (361) (241) (F1) ; -;8120;(11111101) (375) (253) (FD) ;(10101110) (256) (174) (AE) ;(00000001) (1) (1) (01) ;(11100110) (346) (230) (E6) ;(01000000) (100) (64) (40) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;8128;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11100001) (341) (225) (E1) ;(11001000) (310) (200) (C8) ; -;8136;(11101001) (351) (233) (E9) ;(00111110) (76) (62) (3E) ;(00000011) (3) (3) (03) ;(00011000) (30) (24) (18) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(00000010) (2) (2) (02) ;(11001101) (315) (205) (CD) ; -;8144;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ; -;8152;(11001101) (315) (205) (CD) ;(11011111) (337) (223) (DF) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11001001) (311) (201) (C9) ;(11011111) (337) (223) (DF) ; -;8160;(11001101) (315) (205) (CD) ;(01000101) (105) (69) (45) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ; -;8168;(00101000) (50) (40) (28) ;(11111011) (373) (251) (FB) ;(11001101) (315) (205) (CD) ;(11111100) (374) (252) (FC) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ; -;8176;(00101000) (50) (40) (28) ;(11110011) (363) (243) (F3) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11001000) (310) (200) (C8) ;(11001101) (315) (205) (CD) ;(11000011) (303) (195) (C3) ;(00011111) (37) (31) (1F) ; -;8184;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ;(11010111) (327) (215) (D7) ;(11001001) (311) (201) (C9) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(10101100) (254) (172) (AC) ;(00100000) (40) (32) (20) ; -;8192;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(01111001) (171) (121) (79) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11000011) (303) (195) (C3) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ; -;8200;(00000111) (7) (7) (07) ;(00100011) (43) (35) (23) ;(00111110) (76) (62) (3E) ;(00010110) (26) (22) (16) ;(00011000) (30) (24) (18) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(10101101) (255) (173) (AD) ; -;8208;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11000011) (303) (195) (C3) ; -;8216;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(00111110) (76) (62) (3E) ;(00010111) (27) (23) (17) ;(11010111) (327) (215) (D7) ;(01111001) (171) (121) (79) ; -;8224;(11010111) (327) (215) (D7) ;(01111000) (170) (120) (78) ;(11010111) (327) (215) (D7) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11110010) (362) (242) (F2) ;(00100001) (41) (33) (21) ;(11010000) (320) (208) (D0) ; -;8232;(11001101) (315) (205) (CD) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11001101) (315) (205) (CD) ; -;8240;(11000011) (303) (195) (C3) ;(00011111) (37) (31) (1F) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ;(11001100) (314) (204) (CC) ;(11110001) (361) (241) (F1) ; -;8248;(00101011) (53) (43) (2B) ;(11000010) (302) (194) (C2) ;(11100011) (343) (227) (E3) ;(00101101) (55) (45) (2D) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00001011) (13) (11) (0B) ;(11001000) (310) (200) (C8) ; -;8256;(00011010) (32) (26) (1A) ;(00010011) (23) (19) (13) ;(11010111) (327) (215) (D7) ;(00011000) (30) (24) (18) ;(11110111) (367) (247) (F7) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11001000) (310) (200) (C8) ; -;8264;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ;(11001001) (311) (201) (C9) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ; -;8272;(00111011) (73) (59) (3B) ;(00101000) (50) (40) (28) ;(00010100) (24) (20) (14) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(00001010) (12) (10) (0A) ;(11001101) (315) (205) (CD) ; -;8280;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00001011) (13) (11) (0B) ;(00111110) (76) (62) (3E) ;(00000110) (6) (6) (06) ;(11010111) (327) (215) (D7) ;(00011000) (30) (24) (18) ; -;8288;(00000110) (6) (6) (06) ;(11111110) (376) (254) (FE) ;(00100111) (47) (39) (27) ;(11000000) (300) (192) (C0) ;(11001101) (315) (205) (CD) ;(11110101) (365) (245) (F5) ;(00011111) (37) (31) (1F) ;(11100111) (347) (231) (E7) ; -;8296;(11001101) (315) (205) (CD) ;(01000101) (105) (69) (45) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(11000001) (301) (193) (C1) ;(10111111) (277) (191) (BF) ;(11001001) (311) (201) (C9) ; -;8304;(11111110) (376) (254) (FE) ;(00100011) (43) (35) (23) ;(00110111) (67) (55) (37) ;(11000000) (300) (192) (C0) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ; -;8312;(10100111) (247) (167) (A7) ;(11001101) (315) (205) (CD) ;(11000011) (303) (195) (C3) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ;(11111110) (376) (254) (FE) ; -;8320;(00010000) (20) (16) (10) ;(11010010) (322) (210) (D2) ;(00001110) (16) (14) (0E) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(10100111) (247) (167) (A7) ; -;8328;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ; -;8336;(00001101) (15) (13) (0D) ;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ; -;8344;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(11001101) (315) (205) (CD) ;(11000001) (301) (193) (C1) ;(00100000) (40) (32) (20) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ; -;8352;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10001000) (210) (136) (88) ;(01011100) (134) (92) (5C) ;(00111010) (72) (58) (3A) ;(01101011) (153) (107) (6B) ;(01011100) (134) (92) (5C) ;(10111000) (270) (184) (B8) ; -;8360;(00111000) (70) (56) (38) ;(00000011) (3) (3) (03) ;(00001110) (16) (14) (0E) ;(00100001) (41) (33) (21) ;(01000111) (107) (71) (47) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(10001000) (210) (136) (88) ; -;8368;(01011100) (134) (92) (5C) ;(00111110) (76) (62) (3E) ;(00011001) (31) (25) (19) ;(10010000) (220) (144) (90) ;(00110010) (62) (50) (32) ;(10001100) (214) (140) (8C) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ; -;8376;(11001011) (313) (203) (CB) ;(00000010) (2) (2) (02) ;(10000110) (206) (134) (86) ;(11001101) (315) (205) (CD) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(11000011) (303) (195) (C3) ;(01101110) (156) (110) (6E) ; -;8384;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(11111011) (373) (251) (FB) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ; -;8392;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11011111) (337) (223) (DF) ;(00011111) (37) (31) (1F) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ; -;8400;(00101001) (51) (41) (29) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ;(10110010) (262) (178) (B2) ;(00100001) (41) (33) (21) ; -;8408;(11111110) (376) (254) (FE) ;(11001010) (312) (202) (CA) ;(00100000) (40) (32) (20) ;(00010001) (21) (17) (11) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(00011111) (37) (31) (1F) ;(00011100) (34) (28) (1C) ; -;8416;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(11111110) (376) (254) (FE) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ; -;8424;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(00011000) (30) (24) (18) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ; -;8432;(11010010) (322) (210) (D2) ;(10101111) (257) (175) (AF) ;(00100001) (41) (33) (21) ;(11001101) (315) (205) (CD) ;(00011111) (37) (31) (1F) ;(00011100) (34) (28) (1C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;8440;(00110111) (67) (55) (37) ;(10111110) (276) (190) (BE) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11001010) (312) (202) (CA) ;(10110010) (262) (178) (B2) ;(00100001) (41) (33) (21) ; -;8448;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00010110) (26) (22) (16) ;(00100001) (41) (33) (21) ;(01110001) (161) (113) (71) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10110110) (266) (182) (B6) ; -;8456;(11001011) (313) (203) (CB) ;(11101110) (356) (238) (EE) ;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00100000) (40) (32) (20) ; -;8464;(00001011) (13) (11) (0B) ;(00111010) (72) (58) (3A) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11100110) (346) (230) (E6) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ; -;8472;(00001110) (16) (14) (0E) ;(00000011) (3) (3) (03) ;(10110110) (266) (182) (B6) ;(01110111) (167) (119) (77) ;(11110111) (367) (247) (F7) ;(00110110) (66) (54) (36) ;(00001101) (15) (13) (0D) ;(01111001) (171) (121) (79) ; -;8480;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00110000) (60) (48) (30) ;(00000101) (5) (5) (05) ;(00111110) (76) (62) (3E) ;(00100010) (42) (34) (22) ;(00010010) (22) (18) (12) ;(00101011) (53) (43) (2B) ; -;8488;(01110111) (167) (119) (77) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01111110) (176) (126) (7E) ; -;8496;(00100000) (40) (32) (20) ;(00101100) (54) (44) (2C) ;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(00111101) (75) (61) (3D) ; -;8504;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ;(00111010) (72) (58) (3A) ;(00100001) (41) (33) (21) ;(11100101) (345) (229) (E5) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;8512;(00110000) (60) (48) (30) ;(01100110) (146) (102) (66) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11101101) (355) (237) (ED) ;(01110011) (163) (115) (73) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ; -;8520;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10100111) (247) (167) (A7) ;(00010001) (21) (17) (11) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ; -;8528;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(00101100) (54) (44) (2C) ;(00001111) (17) (15) (0F) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;8536;(10111110) (276) (190) (BE) ;(11001101) (315) (205) (CD) ;(10111001) (271) (185) (B9) ;(00100001) (41) (33) (21) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ;(00101100) (54) (44) (2C) ; -;8544;(00001111) (17) (15) (0F) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00100010) (42) (34) (22) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(11010110) (326) (214) (D6) ;(00100001) (41) (33) (21) ; -;8552;(00100000) (40) (32) (20) ;(00001010) (12) (10) (0A) ;(11001101) (315) (205) (CD) ;(00011101) (35) (29) (1D) ;(00010001) (21) (17) (11) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10000010) (202) (130) (82) ; -;8560;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(11011001) (331) (217) (D9) ;(00001101) (15) (13) (0D) ;(00100001) (41) (33) (21) ;(01110001) (161) (113) (71) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ; -;8568;(10101110) (256) (174) (AE) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(11001011) (313) (203) (CB) ;(10111110) (276) (190) (BE) ;(00100000) (40) (32) (20) ;(00011100) (34) (28) (1C) ;(11100001) (341) (225) (E1) ; -;8576;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ; -;8584;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ;(10111001) (271) (185) (B9) ;(00100001) (41) (33) (21) ;(00101010) (52) (42) (2A) ; -;8592;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(00110110) (66) (54) (36) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ; -;8600;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00010111) (27) (23) (17) ;(00101010) (52) (42) (2A) ;(01100011) (143) (99) (63) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ; -;8608;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00110111) (67) (55) (37) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11001101) (315) (205) (CD) ; -;8616;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11001101) (315) (205) (CD) ;(11111111) (377) (255) (FF) ;(00101010) (52) (42) (2A) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ; -;8624;(11111100) (374) (252) (FC) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(01001110) (116) (78) (4E) ;(00100000) (40) (32) (20) ;(11001010) (312) (202) (CA) ;(11000001) (301) (193) (C1) ;(00100000) (40) (32) (20) ; -;8632;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11011111) (337) (223) (DF) ; -;8640;(11111110) (376) (254) (FE) ;(11100010) (342) (226) (E2) ;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ;(00111010) (72) (58) (3A) ;(01110001) (161) (113) (71) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ; -;8648;(01011001) (131) (89) (59) ;(00011100) (34) (28) (1C) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001000) (310) (200) (C8) ;(11001111) (317) (207) (CF) ;(00001011) (13) (11) (0B) ; -;8656;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11001000) (310) (200) (C8) ;(11001111) (317) (207) (CF) ;(00010000) (20) (16) (10) ;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ; -;8664;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(01001011) (113) (75) (4B) ; -;8672;(11001001) (311) (201) (C9) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11110010) (362) (242) (F2) ;(00100001) (41) (33) (21) ;(11011000) (330) (216) (D8) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ; -;8680;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ;(11110110) (366) (246) (F6) ;(11111110) (376) (254) (FE) ;(00111011) (73) (59) (3B) ;(00101000) (50) (40) (28) ;(11110010) (362) (242) (F2) ;(11000011) (303) (195) (C3) ; -;8688;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11111110) (376) (254) (FE) ;(11011001) (331) (217) (D9) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(11011111) (337) (223) (DF) ;(00111111) (77) (63) (3F) ; -;8696;(11011000) (330) (216) (D8) ;(11110101) (365) (245) (F5) ;(11100111) (347) (231) (E7) ;(11110001) (361) (241) (F1) ;(11010110) (326) (214) (D6) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ; -;8704;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11110001) (361) (241) (F1) ;(10100111) (247) (167) (A7) ;(11001101) (315) (205) (CD) ;(11000011) (303) (195) (C3) ;(00011111) (37) (31) (1F) ;(11110101) (365) (245) (F5) ; -;8712;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ;(01010111) (127) (87) (57) ;(11110001) (361) (241) (F1) ;(11010111) (327) (215) (D7) ;(01111010) (172) (122) (7A) ;(11010111) (327) (215) (D7) ; -;8720;(11001001) (311) (201) (C9) ;(11010110) (326) (214) (D6) ;(00010001) (21) (17) (11) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(00101000) (50) (40) (28) ;(00011101) (35) (29) (1D) ;(11010110) (326) (214) (D6) ; -;8728;(00000010) (2) (2) (02) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(00101000) (50) (40) (28) ;(01010110) (126) (86) (56) ;(11111110) (376) (254) (FE) ;(00000001) (1) (1) (01) ;(01111010) (172) (122) (7A) ; -;8736;(00000110) (6) (6) (06) ;(00000001) (1) (1) (01) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000110) (6) (6) (06) ;(00000100) (4) (4) (04) ; -;8744;(01001111) (117) (79) (4F) ;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ;(00110000) (60) (48) (30) ;(00010110) (26) (22) (16) ;(01111001) (171) (121) (79) ;(00100001) (41) (33) (21) ; -;8752;(10010001) (221) (145) (91) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(00111000) (70) (56) (38) ;(01111010) (172) (122) (7A) ;(00000110) (6) (6) (06) ;(00000111) (7) (7) (07) ;(00111000) (70) (56) (38) ; -;8760;(00000101) (5) (5) (05) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000110) (6) (6) (06) ;(00111000) (70) (56) (38) ;(01001111) (117) (79) (4F) ;(01111010) (172) (122) (7A) ; -;8768;(11111110) (376) (254) (FE) ;(00001010) (12) (10) (0A) ;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00010011) (23) (19) (13) ;(00100001) (41) (33) (21) ;(10001111) (217) (143) (8F) ; -;8776;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00001011) (13) (11) (0B) ;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ;(00000111) (7) (7) (07) ; -;8784;(10110000) (260) (176) (B0) ;(00101111) (57) (47) (2F) ;(11100110) (346) (230) (E6) ;(00100100) (44) (36) (24) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(01111000) (170) (120) (78) ;(01001111) (117) (79) (4F) ; -;8792;(01111001) (171) (121) (79) ;(11001101) (315) (205) (CD) ;(01101100) (154) (108) (6C) ;(00100010) (42) (34) (22) ;(00111110) (76) (62) (3E) ;(00000111) (7) (7) (07) ;(10111010) (272) (186) (BA) ;(10011111) (237) (159) (9F) ; -;8800;(11001101) (315) (205) (CD) ;(01101100) (154) (108) (6C) ;(00100010) (42) (34) (22) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(11100110) (346) (230) (E6) ;(01010000) (120) (80) (50) ;(01000111) (107) (71) (47) ; -;8808;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(10111010) (272) (186) (BA) ;(10011111) (237) (159) (9F) ;(10101110) (256) (174) (AE) ;(10100000) (240) (160) (A0) ;(10101110) (256) (174) (AE) ;(01110111) (167) (119) (77) ; -;8816;(00100011) (43) (35) (23) ;(01111000) (170) (120) (78) ;(11001001) (311) (201) (C9) ;(10011111) (237) (159) (9F) ;(01111010) (172) (122) (7A) ;(00001111) (17) (15) (0F) ;(00000110) (6) (6) (06) ;(10000000) (200) (128) (80) ; -;8824;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(00001111) (17) (15) (0F) ;(00000110) (6) (6) (06) ;(01000000) (100) (64) (40) ;(01001111) (117) (79) (4F) ;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ; -;8832;(00001000) (10) (8) (08) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ;(00110000) (60) (48) (30) ;(10111101) (275) (189) (BD) ;(01111001) (171) (121) (79) ; -;8840;(00100001) (41) (33) (21) ;(10001111) (217) (143) (8F) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(01101100) (154) (108) (6C) ;(00100010) (42) (34) (22) ;(01111001) (171) (121) (79) ;(00001111) (17) (15) (0F) ; -;8848;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00011000) (30) (24) (18) ;(11011000) (330) (216) (D8) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ;(11111110) (376) (254) (FE) ; -;8856;(00001000) (10) (8) (08) ;(00110000) (60) (48) (30) ;(10101001) (251) (169) (A9) ;(11010011) (323) (211) (D3) ;(11111110) (376) (254) (FE) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ; -;8864;(11001011) (313) (203) (CB) ;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11101110) (356) (238) (EE) ;(00000111) (7) (7) (07) ;(00110010) (62) (50) (32) ;(01001000) (110) (72) (48) ; -;8872;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(00111110) (76) (62) (3E) ;(10101111) (257) (175) (AF) ;(10010000) (220) (144) (90) ;(11011010) (332) (218) (DA) ;(11111001) (371) (249) (F9) ;(00100100) (44) (36) (24) ; -;8880;(01000111) (107) (71) (47) ;(10100111) (247) (167) (A7) ;(00011111) (37) (31) (1F) ;(00110111) (67) (55) (37) ;(00011111) (37) (31) (1F) ;(10100111) (247) (167) (A7) ;(00011111) (37) (31) (1F) ;(10101000) (250) (168) (A8) ; -;8888;(11100110) (346) (230) (E6) ;(11111000) (370) (248) (F8) ;(10101000) (250) (168) (A8) ;(01100111) (147) (103) (67) ;(01111001) (171) (121) (79) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ; -;8896;(10101000) (250) (168) (A8) ;(11100110) (346) (230) (E6) ;(11000111) (307) (199) (C7) ;(10101000) (250) (168) (A8) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(01101111) (157) (111) (6F) ;(01111001) (171) (121) (79) ; -;8904;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11001101) (315) (205) (CD) ;(00111100) (74) (60) (3C) ;(11001101) (315) (205) (CD) ;(10101010) (252) (170) (AA) ; -;8912;(00100010) (42) (34) (22) ;(01000111) (107) (71) (47) ;(00000100) (4) (4) (04) ;(01111110) (176) (126) (7E) ;(00000111) (7) (7) (07) ;(00010000) (20) (16) (10) ;(11111101) (375) (253) (FD) ;(11100110) (346) (230) (E6) ; -;8920;(00000001) (1) (1) (01) ;(11000011) (303) (195) (C3) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11001101) (315) (205) (CD) ;(11001101) (315) (205) (CD) ;(00111100) (74) (60) (3C) ;(11001101) (315) (205) (CD) ; -;8928;(11100101) (345) (229) (E5) ;(00100010) (42) (34) (22) ;(11000011) (303) (195) (C3) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01111101) (175) (125) (7D) ; -;8936;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10101010) (252) (170) (AA) ;(00100010) (42) (34) (22) ;(01000111) (107) (71) (47) ;(00000100) (4) (4) (04) ;(00111110) (76) (62) (3E) ;(11111110) (376) (254) (FE) ; -;8944;(00001111) (17) (15) (0F) ;(00010000) (20) (16) (10) ;(11111101) (375) (253) (FD) ;(01000111) (107) (71) (47) ;(01111110) (176) (126) (7E) ;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(01010111) (127) (87) (57) ; -;8952;(11001011) (313) (203) (CB) ;(01000001) (101) (65) (41) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(10100000) (240) (160) (A0) ;(11001011) (313) (203) (CB) ;(01010001) (121) (81) (51) ;(00100000) (40) (32) (20) ; -;8960;(00000010) (2) (2) (02) ;(10101000) (250) (168) (A8) ;(00101111) (57) (47) (2F) ;(01110111) (167) (119) (77) ;(11000011) (303) (195) (C3) ;(11011011) (333) (219) (DB) ;(00001011) (13) (11) (0B) ;(11001101) (315) (205) (CD) ; -;8968;(00010100) (24) (20) (14) ;(00100011) (43) (35) (23) ;(01000111) (107) (71) (47) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(00010100) (24) (20) (14) ;(00100011) (43) (35) (23) ;(01011001) (131) (89) (59) ; -;8976;(11000001) (301) (193) (C1) ;(01010001) (121) (81) (51) ;(01001111) (117) (79) (4F) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(11011010) (332) (218) (DA) ; -;8984;(11111001) (371) (249) (F9) ;(00100100) (44) (36) (24) ;(00001110) (16) (14) (0E) ;(00000001) (1) (1) (01) ;(11001000) (310) (200) (C8) ;(00001110) (16) (14) (0E) ;(11111111) (377) (255) (FF) ;(11001001) (311) (201) (C9) ; -;8992;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ; -;9000;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11101111) (357) (239) (EF) ;(00101010) (52) (42) (2A) ;(00111101) (75) (61) (3D) ; -;9008;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(10000001) (201) (129) (81) ;(00110000) (60) (48) (30) ;(00000101) (5) (5) (05) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ; -;9016;(00111000) (70) (56) (38) ;(00011000) (30) (24) (18) ;(10100001) (241) (161) (A1) ;(11101111) (357) (239) (EF) ;(10100011) (243) (163) (A3) ;(00111000) (70) (56) (38) ;(00110110) (66) (54) (36) ;(10000011) (203) (131) (83) ; -;9024;(11101111) (357) (239) (EF) ;(11000101) (305) (197) (C5) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(01111101) (175) (125) (7D) ;(00100100) (44) (36) (24) ;(11000101) (305) (197) (C5) ; -;9032;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(11100001) (341) (225) (E1) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(10000000) (200) (128) (80) ; -;9040;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11000001) (301) (193) (C1) ;(11000011) (303) (195) (C3) ; -;9048;(11011100) (334) (220) (DC) ;(00100010) (42) (34) (22) ;(11101111) (357) (239) (EF) ;(11000010) (302) (194) (C2) ;(00000001) (1) (1) (01) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(00000011) (3) (3) (03) ; -;9056;(00000001) (1) (1) (01) ;(11100000) (340) (224) (E0) ;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(11100000) (340) (224) (E0) ;(00000001) (1) (1) (01) ; -;9064;(00110001) (61) (49) (31) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ; -;9072;(01100010) (142) (98) (62) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ;(01101111) (157) (111) (6F) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ; -;9080;(00011110) (36) (30) (1E) ;(11100001) (341) (225) (E1) ;(01100111) (147) (103) (67) ;(00100010) (42) (34) (22) ;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(11000001) (301) (193) (C1) ;(11000011) (303) (195) (C3) ; -;9088;(00100000) (40) (32) (20) ;(00100100) (44) (36) (24) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ; -;9096;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11000011) (303) (195) (C3) ;(01110111) (167) (119) (77) ;(00100100) (44) (36) (24) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ; -;9104;(00011100) (34) (28) (1C) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(11101111) (357) (239) (EF) ;(11000101) (305) (197) (C5) ;(10100010) (242) (162) (A2) ;(00000100) (4) (4) (04) ; -;9112;(00011111) (37) (31) (1F) ;(00110001) (61) (49) (31) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000110) (6) (6) (06) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ; -;9120;(11000011) (303) (195) (C3) ;(01110111) (167) (119) (77) ;(00100100) (44) (36) (24) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ; -;9128;(00101010) (52) (42) (2A) ;(11100001) (341) (225) (E1) ;(00000001) (1) (1) (01) ;(11100001) (341) (225) (E1) ;(00101010) (52) (42) (2A) ;(00001111) (17) (15) (0F) ;(11100000) (340) (224) (E0) ;(00000101) (5) (5) (05) ; -;9136;(00101010) (52) (42) (2A) ;(11100000) (340) (224) (E0) ;(00000001) (1) (1) (01) ;(00111101) (75) (61) (3D) ;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(10000001) (201) (129) (81) ; -;9144;(00110000) (60) (48) (30) ;(00000111) (7) (7) (07) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11000011) (303) (195) (C3) ;(01110111) (167) (119) (77) ; -;9152;(00100100) (44) (36) (24) ;(11001101) (315) (205) (CD) ;(01111101) (175) (125) (7D) ;(00100100) (44) (36) (24) ;(11000101) (305) (197) (C5) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(11100001) (341) (225) (E1) ; -;9160;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(11100001) (341) (225) (E1) ;(00000100) (4) (4) (04) ; -;9168;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(11100001) (341) (225) (E1) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(11100101) (345) (229) (E5) ; -;9176;(11100000) (340) (224) (E0) ;(00000011) (3) (3) (03) ;(10100010) (242) (162) (A2) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(00011111) (37) (31) (1F) ;(11000101) (305) (197) (C5) ;(00000010) (2) (2) (02) ; -;9184;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(11000001) (301) (193) (C1) ;(11100101) (345) (229) (E5) ;(00000100) (4) (4) (04) ; -;9192;(11100000) (340) (224) (E0) ;(11100010) (342) (226) (E2) ;(00000100) (4) (4) (04) ;(00001111) (17) (15) (0F) ;(11100001) (341) (225) (E1) ;(00000001) (1) (1) (01) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ; -;9200;(11100000) (340) (224) (E0) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(11100101) (345) (229) (E5) ;(00000100) (4) (4) (04) ;(00000011) (3) (3) (03) ;(11000010) (302) (194) (C2) ;(00101010) (52) (42) (2A) ; -;9208;(11100001) (341) (225) (E1) ;(00101010) (52) (42) (2A) ;(00001111) (17) (15) (0F) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(00011010) (32) (26) (1A) ;(11111110) (376) (254) (FE) ;(10000001) (201) (129) (81) ; -;9216;(11000001) (301) (193) (C1) ;(11011010) (332) (218) (DA) ;(01110111) (167) (119) (77) ;(00100100) (44) (36) (24) ;(11000101) (305) (197) (C5) ;(11101111) (357) (239) (EF) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ; -;9224;(00111010) (72) (58) (3A) ;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(11000000) (300) (192) (C0) ; -;9232;(00001111) (17) (15) (0F) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(00111010) (72) (58) (3A) ;(01111110) (176) (126) (7E) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ; -;9240;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(11000101) (305) (197) (C5) ;(00001111) (17) (15) (0F) ;(11100000) (340) (224) (E0) ;(11100101) (345) (229) (E5) ;(00111000) (70) (56) (38) ;(11000001) (301) (193) (C1) ; -;9248;(00000101) (5) (5) (05) ;(00101000) (50) (40) (28) ;(00111100) (74) (60) (3C) ;(00011000) (30) (24) (18) ;(00010100) (24) (20) (14) ;(11101111) (357) (239) (EF) ;(11100001) (341) (225) (E1) ;(00110001) (61) (49) (31) ; -;9256;(11100011) (343) (227) (E3) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(11100100) (344) (228) (E4) ;(00000100) (4) (4) (04) ;(00000011) (3) (3) (03) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ; -;9264;(11100100) (344) (228) (E4) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(11100011) (343) (227) (E3) ;(00000100) (4) (4) (04) ;(00001111) (17) (15) (0F) ;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ; -;9272;(00111000) (70) (56) (38) ;(11000101) (305) (197) (C5) ;(11101111) (357) (239) (EF) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(11100001) (341) (225) (E1) ;(00001111) (17) (15) (0F) ;(00110001) (61) (49) (31) ; -;9280;(00111000) (70) (56) (38) ;(00111010) (72) (58) (3A) ;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ; -;9288;(00000011) (3) (3) (03) ;(11100000) (340) (224) (E0) ;(11100010) (342) (226) (E2) ;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ;(00000001) (1) (1) (01) ;(11100000) (340) (224) (E0) ;(00111000) (70) (56) (38) ; -;9296;(00111010) (72) (58) (3A) ;(01111110) (176) (126) (7E) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(00000011) (3) (3) (03) ; -;9304;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(10110111) (267) (183) (B7) ;(00100100) (44) (36) (24) ;(11000001) (301) (193) (C1) ;(00010000) (20) (16) (10) ;(11000110) (306) (198) (C6) ;(11101111) (357) (239) (EF) ; -;9312;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(00111010) (72) (58) (3A) ;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ; -;9320;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(00000011) (3) (3) (03) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(00111010) (72) (58) (3A) ;(01111110) (176) (126) (7E) ; -;9328;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(00000011) (3) (3) (03) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ; -;9336;(10110111) (267) (183) (B7) ;(00100100) (44) (36) (24) ;(11000011) (303) (195) (C3) ;(01001101) (115) (77) (4D) ;(00001101) (15) (13) (0D) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00101000) (50) (40) (28) ; -;9344;(00110100) (64) (52) (34) ;(00110010) (62) (50) (32) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(11100101) (345) (229) (E5) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ; -;9352;(00101010) (52) (42) (2A) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(00000110) (6) (6) (06) ;(11100110) (346) (230) (E6) ; -;9360;(11111100) (374) (252) (FC) ;(11000110) (306) (198) (C6) ;(00000100) (4) (4) (04) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(11111100) (374) (252) (FC) ;(11110101) (365) (245) (F5) ; -;9368;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(11100101) (345) (229) (E5) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00110001) (61) (49) (31) ; -;9376;(00011111) (37) (31) (1F) ;(11000100) (304) (196) (C4) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(10100010) (242) (162) (A2) ;(00000100) (4) (4) (04) ;(00011111) (37) (31) (1F) ;(11000001) (301) (193) (C1) ; -;9384;(00000001) (1) (1) (01) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(10100001) (241) (161) (A1) ; -;9392;(00000011) (3) (3) (03) ;(00011011) (33) (27) (1B) ;(11000011) (303) (195) (C3) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11000001) (301) (193) (C1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ; -;9400;(00000111) (7) (7) (07) ;(00100011) (43) (35) (23) ;(01111001) (171) (121) (79) ;(10111000) (270) (184) (B8) ;(00110000) (60) (48) (30) ;(00000110) (6) (6) (06) ;(01101001) (151) (105) (69) ;(11010101) (325) (213) (D5) ; -;9408;(10101111) (257) (175) (AF) ;(01011111) (137) (95) (5F) ;(00011000) (30) (24) (18) ;(00000111) (7) (7) (07) ;(10110001) (261) (177) (B1) ;(11001000) (310) (200) (C8) ;(01101000) (150) (104) (68) ;(01000001) (101) (65) (41) ; -;9416;(11010101) (325) (213) (D5) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01111000) (170) (120) (78) ;(00011111) (37) (31) (1F) ;(10000101) (205) (133) (85) ;(00111000) (70) (56) (38) ; -;9424;(00000011) (3) (3) (03) ;(10111100) (274) (188) (BC) ;(00111000) (70) (56) (38) ;(00000111) (7) (7) (07) ;(10010100) (224) (148) (94) ;(01001111) (117) (79) (4F) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ; -;9432;(11000101) (305) (197) (C5) ;(00011000) (30) (24) (18) ;(00000100) (4) (4) (04) ;(01001111) (117) (79) (4F) ;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ;(00101010) (52) (42) (2A) ; -;9440;(01111101) (175) (125) (7D) ;(01011100) (134) (92) (5C) ;(01111000) (170) (120) (78) ;(10000100) (204) (132) (84) ;(01000111) (107) (71) (47) ;(01111001) (171) (121) (79) ;(00111100) (74) (60) (3C) ;(10000101) (205) (133) (85) ; -;9448;(00111000) (70) (56) (38) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ;(00111101) (75) (61) (3D) ;(01001111) (117) (79) (4F) ;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ; -;9456;(00100010) (42) (34) (22) ;(11011001) (331) (217) (D9) ;(01111001) (171) (121) (79) ;(00010000) (20) (16) (10) ;(11011001) (331) (217) (D9) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(00101000) (50) (40) (28) ; -;9464;(11110011) (363) (243) (F3) ;(11001111) (317) (207) (CF) ;(00001010) (12) (10) (0A) ;(11011111) (337) (223) (DF) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11000101) (305) (197) (C5) ;(01001111) (117) (79) (4F) ; -;9472;(00100001) (41) (33) (21) ;(10010110) (226) (150) (96) ;(00100101) (45) (37) (25) ;(11001101) (315) (205) (CD) ;(11011100) (334) (220) (DC) ;(00010110) (26) (22) (16) ;(01111001) (171) (121) (79) ;(11010010) (322) (210) (D2) ; -;9480;(10000100) (204) (132) (84) ;(00100110) (46) (38) (26) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(01001110) (116) (78) (4E) ;(00001001) (11) (9) (09) ;(11101001) (351) (233) (E9) ;(11001101) (315) (205) (CD) ; -;9488;(01110100) (164) (116) (74) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001010) (312) (202) (CA) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;9496;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(11110011) (363) (243) (F3) ;(11001101) (315) (205) (CD) ;(01110100) (164) (116) (74) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ; -;9504;(00100010) (42) (34) (22) ;(11001001) (311) (201) (C9) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ; -;9512;(01111001) (171) (121) (79) ;(00011100) (34) (28) (1C) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;9520;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01111110) (176) (126) (7E) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00111100) (74) (60) (3C) ; -;9528;(00101010) (52) (42) (2A) ;(00110110) (66) (54) (36) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00011001) (31) (25) (19) ;(01111001) (171) (121) (79) ; -;9536;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(11100110) (346) (230) (E6) ;(11100000) (340) (224) (E0) ;(10101000) (250) (168) (A8) ;(01011111) (137) (95) (5F) ;(01111001) (171) (121) (79) ; -;9544;(11100110) (346) (230) (E6) ;(00011000) (30) (24) (18) ;(11101110) (356) (238) (EE) ;(01000000) (100) (64) (40) ;(01010111) (127) (87) (57) ;(00000110) (6) (6) (06) ;(01100000) (140) (96) (60) ;(11000101) (305) (197) (C5) ; -;9552;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(00011010) (32) (26) (1A) ;(10101110) (256) (174) (AE) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ; -;9560;(00011010) (32) (26) (1A) ;(00111101) (75) (61) (3D) ;(01001111) (117) (79) (4F) ;(00000110) (6) (6) (06) ;(00000111) (7) (7) (07) ;(00010100) (24) (20) (14) ;(00100011) (43) (35) (23) ;(00011010) (32) (26) (1A) ; -;9568;(10101110) (256) (174) (AE) ;(10101001) (251) (169) (A9) ;(00100000) (40) (32) (20) ;(00001111) (17) (15) (0F) ;(00010000) (20) (16) (10) ;(11110111) (367) (247) (F7) ;(11000001) (301) (193) (C1) ;(11000001) (301) (193) (C1) ; -;9576;(11000001) (301) (193) (C1) ;(00111110) (76) (62) (3E) ;(10000000) (200) (128) (80) ;(10010000) (220) (144) (90) ;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11110111) (367) (247) (F7) ; -;9584;(00010010) (22) (18) (12) ;(00011000) (30) (24) (18) ;(00001010) (12) (10) (0A) ;(11100001) (341) (225) (E1) ;(00010001) (21) (17) (11) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ; -;9592;(11010001) (321) (209) (D1) ;(11000001) (301) (193) (C1) ;(00010000) (20) (16) (10) ;(11010011) (323) (211) (D3) ;(01001000) (110) (72) (48) ;(11001001) (311) (201) (C9) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;9600;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00111100) (74) (60) (3C) ;(01111001) (171) (121) (79) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(01001111) (117) (79) (4F) ; -;9608;(11100110) (346) (230) (E6) ;(11100000) (340) (224) (E0) ;(10101000) (250) (168) (A8) ;(01101111) (157) (111) (6F) ;(01111001) (171) (121) (79) ;(11100110) (346) (230) (E6) ;(00000011) (3) (3) (03) ;(11101110) (356) (238) (EE) ; -;9616;(01011000) (130) (88) (58) ;(01100111) (147) (103) (67) ;(01111110) (176) (126) (7E) ;(11000011) (303) (195) (C3) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(00100010) (42) (34) (22) ;(00011100) (34) (28) (1C) ; -;9624;(00101000) (50) (40) (28) ;(01001111) (117) (79) (4F) ;(00101110) (56) (46) (2E) ;(11110010) (362) (242) (F2) ;(00101011) (53) (43) (2B) ;(00010010) (22) (18) (12) ;(10101000) (250) (168) (A8) ;(01010110) (126) (86) (56) ; -;9632;(10100101) (245) (165) (A5) ;(01010111) (127) (87) (57) ;(10100111) (247) (167) (A7) ;(10000100) (204) (132) (84) ;(10100110) (246) (166) (A6) ;(10001111) (217) (143) (8F) ;(11000100) (304) (196) (C4) ;(11100110) (346) (230) (E6) ; -;9640;(10101010) (252) (170) (AA) ;(10111111) (277) (191) (BF) ;(10101011) (253) (171) (AB) ;(11000111) (307) (199) (C7) ;(10101001) (251) (169) (A9) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(11100111) (347) (231) (E7) ; -;9648;(11000011) (303) (195) (C3) ;(11111111) (377) (255) (FF) ;(00100100) (44) (36) (24) ;(11011111) (337) (223) (DF) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ; -;9656;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(00001111) (17) (15) (0F) ;(00100101) (45) (37) (25) ;(00100000) (40) (32) (20) ;(00011011) (33) (27) (1B) ;(11001101) (315) (205) (CD) ;(00001111) (17) (15) (0F) ; -;9664;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(11111011) (373) (251) (FB) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00010001) (21) (17) (11) ; -;9672;(11110111) (367) (247) (F7) ;(11100001) (341) (225) (E1) ;(11010101) (325) (213) (D5) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(00010010) (22) (18) (12) ;(00010011) (23) (19) (13) ;(11111110) (376) (254) (FE) ; -;9680;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00101000) (50) (40) (28) ; -;9688;(11110010) (362) (242) (F2) ;(00001011) (13) (11) (0B) ;(11010001) (321) (209) (D1) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10110110) (266) (182) (B6) ; -;9696;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(11000100) (304) (196) (C4) ;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11000011) (303) (195) (C3) ;(00010010) (22) (18) (12) ;(00100111) (47) (39) (27) ; -;9704;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ; -;9712;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ;(00010010) (22) (18) (12) ;(00100111) (47) (39) (27) ;(11000011) (303) (195) (C3) ;(10111101) (275) (189) (BD) ;(00100111) (47) (39) (27) ; -;9720;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01110110) (166) (118) (76) ; -;9728;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00101011) (53) (43) (2B) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(10100001) (241) (161) (A1) ;(00001111) (17) (15) (0F) ;(00110100) (64) (52) (34) ; -;9736;(00110111) (67) (55) (37) ;(00010110) (26) (22) (16) ;(00000100) (4) (4) (04) ;(00110100) (64) (52) (34) ;(10000000) (200) (128) (80) ;(01000001) (101) (65) (41) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;9744;(10000000) (200) (128) (80) ;(00110010) (62) (50) (32) ;(00000010) (2) (2) (02) ;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(00110001) (61) (49) (31) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ; -;9752;(10100010) (242) (162) (A2) ;(00101101) (55) (45) (2D) ;(11101101) (355) (237) (ED) ;(01000011) (103) (67) (43) ;(01110110) (166) (118) (76) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ; -;9760;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(11010110) (326) (214) (D6) ;(00010000) (20) (16) (10) ;(01110111) (167) (119) (77) ;(00011000) (30) (24) (18) ;(00001001) (11) (9) (09) ;(11001101) (315) (205) (CD) ; -;9768;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11101111) (357) (239) (EF) ;(10100011) (243) (163) (A3) ;(00111000) (70) (56) (38) ;(00110100) (64) (52) (34) ; -;9776;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ;(11000011) (303) (195) (C3) ;(00100110) (46) (38) (26) ;(00000001) (1) (1) (01) ;(01011010) (132) (90) (5A) ;(00010000) (20) (16) (10) ;(11100111) (347) (231) (E7) ; -;9784;(11111110) (376) (254) (FE) ;(00100011) (43) (35) (23) ;(11001010) (312) (202) (CA) ;(00001101) (15) (13) (0D) ;(00100111) (47) (39) (27) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ; -;9792;(11001011) (313) (203) (CB) ;(10110110) (266) (182) (B6) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ;(00011111) (37) (31) (1F) ;(11001101) (315) (205) (CD) ;(10001110) (216) (142) (8E) ; -;9800;(00000010) (2) (2) (02) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010011) (23) (19) (13) ;(11001101) (315) (205) (CD) ;(00011110) (36) (30) (1E) ;(00000011) (3) (3) (03) ; -;9808;(00110000) (60) (48) (30) ;(00001110) (16) (14) (0E) ;(00010101) (25) (21) (15) ;(01011111) (137) (95) (5F) ;(11001101) (315) (205) (CD) ;(00110011) (63) (51) (33) ;(00000011) (3) (3) (03) ;(11110101) (365) (245) (F5) ; -;9816;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11110111) (367) (247) (F7) ;(11110001) (361) (241) (F1) ;(00010010) (22) (18) (12) ;(00001110) (16) (14) (0E) ;(00000001) (1) (1) (01) ; -;9824;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11000011) (303) (195) (C3) ;(00010010) (22) (18) (12) ;(00100111) (47) (39) (27) ; -;9832;(11001101) (315) (205) (CD) ;(00100010) (42) (34) (22) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(00110101) (65) (53) (35) ;(00100101) (45) (37) (25) ;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ; -;9840;(11011011) (333) (219) (DB) ;(00100101) (45) (37) (25) ;(11001101) (315) (205) (CD) ;(00100010) (42) (34) (22) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(10000000) (200) (128) (80) ;(00100101) (45) (37) (25) ; -;9848;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(01001000) (110) (72) (48) ;(11001101) (315) (205) (CD) ;(00100010) (42) (34) (22) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(11001011) (313) (203) (CB) ; -;9856;(00100010) (42) (34) (22) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(00111111) (77) (63) (3F) ;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ; -;9864;(01010110) (126) (86) (56) ;(11111110) (376) (254) (FE) ;(01000001) (101) (65) (41) ;(00110000) (60) (48) (30) ;(00111100) (74) (60) (3C) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ; -;9872;(00100000) (40) (32) (20) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00101100) (54) (44) (2C) ;(11011111) (337) (223) (DF) ;(00000001) (1) (1) (01) ;(00000110) (6) (6) (06) ; -;9880;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00001110) (16) (14) (0E) ;(00100011) (43) (35) (23) ; -;9888;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00001110) (16) (14) (0E) ;(00000101) (5) (5) (05) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ; -;9896;(01000010) (102) (66) (42) ;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11101011) (353) (235) (EB) ;(00101011) (53) (43) (2B) ; -;9904;(11001101) (315) (205) (CD) ;(01110111) (167) (119) (77) ;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(00001110) (16) (14) (0E) ;(11011111) (337) (223) (DF) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ; -;9912;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ;(00100000) (40) (32) (20) ;(11111010) (372) (250) (FA) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(10110100) (264) (180) (B4) ;(00110011) (63) (51) (33) ; -;9920;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11110110) (366) (246) (F6) ;(00011000) (30) (24) (18) ; -;9928;(00010100) (24) (20) (14) ;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101000) (50) (40) (28) ;(11011010) (332) (218) (DA) ;(00101110) (56) (46) (2E) ;(00011100) (34) (28) (1C) ;(11001100) (314) (204) (CC) ; -;9936;(10010110) (226) (150) (96) ;(00101001) (51) (41) (29) ;(00111010) (72) (58) (3A) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11111110) (376) (254) (FE) ;(11000000) (300) (192) (C0) ;(00111000) (70) (56) (38) ; -;9944;(00000100) (4) (4) (04) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(10110100) (264) (180) (B4) ;(00110011) (63) (51) (33) ;(00011000) (30) (24) (18) ;(00110011) (63) (51) (33) ;(00000001) (1) (1) (01) ; -;9952;(11011011) (333) (219) (DB) ;(00001001) (11) (9) (09) ;(11111110) (376) (254) (FE) ;(00101101) (55) (45) (2D) ;(00101000) (50) (40) (28) ;(00100111) (47) (39) (27) ;(00000001) (1) (1) (01) ;(00011000) (30) (24) (18) ; -;9960;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(10101110) (256) (174) (AE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(11010110) (326) (214) (D6) ;(10101111) (257) (175) (AF) ;(11011010) (332) (218) (DA) ; -;9968;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(00000001) (1) (1) (01) ;(11110000) (360) (240) (F0) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(00010100) (24) (20) (14) ;(00101000) (50) (40) (28) ; -;9976;(00010100) (24) (20) (14) ;(11010010) (322) (210) (D2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(00000110) (6) (6) (06) ;(00010000) (20) (16) (10) ;(11000110) (306) (198) (C6) ;(11011100) (334) (220) (DC) ; -;9984;(01001111) (117) (79) (4F) ;(11111110) (376) (254) (FE) ;(11011111) (337) (223) (DF) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(10110001) (261) (177) (B1) ;(11111110) (376) (254) (FE) ; -;9992;(11101110) (356) (238) (EE) ;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(10111001) (271) (185) (B9) ;(11000101) (305) (197) (C5) ;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ; -;10000;(11111111) (377) (255) (FF) ;(00100100) (44) (36) (24) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(00001100) (14) (12) (0C) ;(11111101) (375) (253) (FD) ; -;10008;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ;(00100000) (40) (32) (20) ;(00010111) (27) (23) (17) ;(11001101) (315) (205) (CD) ;(01010010) (122) (82) (52) ;(00101010) (52) (42) (2A) ; -;10016;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11110000) (360) (240) (F0) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(01001111) (117) (79) (4F) ;(00100001) (41) (33) (21) ;(10010101) (225) (149) (95) ; -;10024;(00100111) (47) (39) (27) ;(11001101) (315) (205) (CD) ;(11011100) (334) (220) (DC) ;(00010110) (26) (22) (16) ;(00110000) (60) (48) (30) ;(00000110) (6) (6) (06) ;(01001110) (116) (78) (4E) ;(00100001) (41) (33) (21) ; -;10032;(11101101) (355) (237) (ED) ;(00100110) (46) (38) (26) ;(00001001) (11) (9) (09) ;(01000110) (106) (70) (46) ;(11010001) (321) (209) (D1) ;(01111010) (172) (122) (7A) ;(10111000) (270) (184) (B8) ;(00111000) (70) (56) (38) ; -;10040;(00111010) (72) (58) (3A) ;(10100111) (247) (167) (A7) ;(11001010) (312) (202) (CA) ;(00011000) (30) (24) (18) ;(00000000) (0) (0) (00) ;(11000101) (305) (197) (C5) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ; -;10048;(01011100) (134) (92) (5C) ;(01111011) (173) (123) (7B) ;(11111110) (376) (254) (FE) ;(11101101) (355) (237) (ED) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11001011) (313) (203) (CB) ;(01110110) (166) (118) (76) ; -;10056;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00011110) (36) (30) (1E) ;(10011001) (231) (153) (99) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ; -;10064;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(01111011) (173) (123) (7B) ;(11100110) (346) (230) (E6) ;(00111111) (77) (63) (3F) ;(01000111) (107) (71) (47) ;(11101111) (357) (239) (EF) ;(00111011) (73) (59) (3B) ; -;10072;(00111000) (70) (56) (38) ;(00011000) (30) (24) (18) ;(00001001) (11) (9) (09) ;(01111011) (173) (123) (7B) ;(11111101) (375) (253) (FD) ;(10101110) (256) (174) (AE) ;(00000001) (1) (1) (01) ;(11100110) (346) (230) (E6) ; -;10080;(01000000) (100) (64) (40) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11010001) (321) (209) (D1) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ; -;10088;(11001011) (313) (203) (CB) ;(11110110) (366) (246) (F6) ;(11001011) (313) (203) (CB) ;(01111011) (173) (123) (7B) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(10110110) (266) (182) (B6) ; -;10096;(11000001) (301) (193) (C1) ;(00011000) (30) (24) (18) ;(11000001) (301) (193) (C1) ;(11010101) (325) (213) (D5) ;(01111001) (171) (121) (79) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;10104;(01110110) (166) (118) (76) ;(00100000) (40) (32) (20) ;(00010101) (25) (21) (15) ;(11100110) (346) (230) (E6) ;(00111111) (77) (63) (3F) ;(11000110) (306) (198) (C6) ;(00001000) (10) (8) (08) ;(01001111) (117) (79) (4F) ; -;10112;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(11001011) (313) (203) (CB) ;(11110001) (361) (241) (F1) ;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ; -;10120;(00111000) (70) (56) (38) ;(11010111) (327) (215) (D7) ;(11111110) (376) (254) (FE) ;(00010111) (27) (23) (17) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(11111001) (371) (249) (F9) ; -;10128;(11000101) (305) (197) (C5) ;(11100111) (347) (231) (E7) ;(11000011) (303) (195) (C3) ;(11111111) (377) (255) (FF) ;(00100100) (44) (36) (24) ;(00101011) (53) (43) (2B) ;(11001111) (317) (207) (CF) ;(00101101) (55) (45) (2D) ; -;10136;(11000011) (303) (195) (C3) ;(00101010) (52) (42) (2A) ;(11000100) (304) (196) (C4) ;(00101111) (57) (47) (2F) ;(11000101) (305) (197) (C5) ;(01011110) (136) (94) (5E) ;(11000110) (306) (198) (C6) ;(00111101) (75) (61) (3D) ; -;10144;(11001110) (316) (206) (CE) ;(00111110) (76) (62) (3E) ;(11001100) (314) (204) (CC) ;(00111100) (74) (60) (3C) ;(11001101) (315) (205) (CD) ;(11000111) (307) (199) (C7) ;(11001001) (311) (201) (C9) ;(11001000) (310) (200) (C8) ; -;10152;(11001010) (312) (202) (CA) ;(11001001) (311) (201) (C9) ;(11001011) (313) (203) (CB) ;(11000101) (305) (197) (C5) ;(11000111) (307) (199) (C7) ;(11000110) (306) (198) (C6) ;(11001000) (310) (200) (C8) ;(00000000) (0) (0) (00) ; -;10160;(00000110) (6) (6) (06) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001010) (12) (10) (0A) ;(00000010) (2) (2) (02) ;(00000011) (3) (3) (03) ;(00000101) (5) (5) (05) ;(00000101) (5) (5) (05) ; -;10168;(00000101) (5) (5) (05) ;(00000101) (5) (5) (05) ;(00000101) (5) (5) (05) ;(00000101) (5) (5) (05) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ; -;10176;(00100000) (40) (32) (20) ;(00110101) (65) (53) (35) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ;(11010010) (322) (210) (D2) ;(10001010) (212) (138) (8A) ; -;10184;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ;(11110101) (365) (245) (F5) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(11100111) (347) (231) (E7) ; -;10192;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ; -;10200;(00010000) (20) (16) (10) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ; -;10208;(00000011) (3) (3) (03) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11110101) (365) (245) (F5) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ; -;10216;(00011100) (34) (28) (1C) ;(11100111) (347) (231) (E7) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(10110110) (266) (182) (B6) ;(11110001) (361) (241) (F1) ; -;10224;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11001011) (313) (203) (CB) ;(11110110) (366) (246) (F6) ;(11000011) (303) (195) (C3) ;(00010010) (22) (18) (12) ;(00100111) (47) (39) (27) ;(11100111) (347) (231) (E7) ; -;10232;(11100110) (346) (230) (E6) ;(11011111) (337) (223) (DF) ;(01000111) (107) (71) (47) ;(11100111) (347) (231) (E7) ;(11010110) (326) (214) (D6) ;(00100100) (44) (36) (24) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ; -;10240;(00000001) (1) (1) (01) ;(11100111) (347) (231) (E7) ;(11100111) (347) (231) (E7) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;10248;(00010001) (21) (17) (11) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10000110) (206) (134) (86) ;(00011101) (35) (29) (1D) ;(11000001) (301) (193) (C1) ; -;10256;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00011000) (30) (24) (18) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ; -;10264;(11100110) (346) (230) (E6) ;(11011111) (337) (223) (DF) ;(10111000) (270) (184) (B8) ;(00100000) (40) (32) (20) ;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ; -;10272;(11010110) (326) (214) (D6) ;(00100100) (44) (36) (24) ;(10111001) (271) (185) (B9) ;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ;(11100001) (341) (225) (E1) ;(00101011) (53) (43) (2B) ;(00010001) (21) (17) (11) ; -;10280;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10001011) (213) (139) (8B) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(00011000) (30) (24) (18) ; -;10288;(11010111) (327) (215) (D7) ;(10100111) (247) (167) (A7) ;(11001100) (314) (204) (CC) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(11010001) (321) (209) (D1) ;(11010001) (321) (209) (D1) ;(11101101) (355) (237) (ED) ; -;10296;(01010011) (123) (83) (53) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(11100101) (345) (229) (E5) ;(11111110) (376) (254) (FE) ; -;10304;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(01000010) (102) (66) (42) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ;(00010110) (26) (22) (16) ; -;10312;(01000000) (100) (64) (40) ;(00101000) (50) (40) (28) ;(00000111) (7) (7) (07) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(00100011) (43) (35) (23) ; -;10320;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ; -;10328;(11110001) (361) (241) (F1) ;(11111101) (375) (253) (FD) ;(10101110) (256) (174) (AE) ;(00000001) (1) (1) (01) ;(11100110) (346) (230) (E6) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00101011) (53) (43) (2B) ; -;10336;(11100001) (341) (225) (E1) ;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ; -;10344;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11101011) (353) (235) (EB) ; -;10352;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ; -;10360;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(00001101) (15) (13) (0D) ;(11100111) (347) (231) (E7) ;(11100001) (341) (225) (E1) ; -;10368;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(00011000) (30) (24) (18) ;(10111110) (276) (190) (BE) ;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ; -;10376;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11001111) (317) (207) (CF) ;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ;(11101011) (353) (235) (EB) ;(00100010) (42) (34) (22) ; -;10384;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(00001011) (13) (11) (0B) ;(01011100) (134) (92) (5C) ;(11100011) (343) (227) (E3) ;(00100010) (42) (34) (22) ;(00001011) (13) (11) (0B) ; -;10392;(01011100) (134) (92) (5C) ;(11010101) (325) (213) (D5) ;(11100111) (347) (231) (E7) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ;(11100001) (341) (225) (E1) ; -;10400;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(00001011) (13) (11) (0B) ;(01011100) (134) (92) (5C) ;(11100111) (347) (231) (E7) ; -;10408;(11000011) (303) (195) (C3) ;(00010010) (22) (18) (12) ;(00100111) (47) (39) (27) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00111000) (70) (56) (38) ; -;10416;(11111010) (372) (250) (FA) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11110110) (366) (246) (F6) ;(11011111) (337) (223) (DF) ;(11001101) (315) (205) (CD) ; -;10424;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ;(11010010) (322) (210) (D2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11100101) (345) (229) (E5) ;(11100110) (346) (230) (E6) ;(00011111) (37) (31) (1F) ; -;10432;(01001111) (117) (79) (4F) ;(11100111) (347) (231) (E7) ;(11100101) (345) (229) (E5) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(11001011) (313) (203) (CB) ; -;10440;(11110001) (361) (241) (F1) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ;(00101000) (50) (40) (28) ;(00010001) (21) (17) (11) ;(11001011) (313) (203) (CB) ;(11101001) (351) (233) (E9) ;(11001101) (315) (205) (CD) ; -;10448;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ; -;10456;(00010110) (26) (22) (16) ;(11001011) (313) (203) (CB) ;(10110001) (261) (177) (B1) ;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11110110) (366) (246) (F6) ;(11100111) (347) (231) (E7) ;(11111101) (375) (253) (FD) ; -;10464;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10110110) (266) (182) (B6) ;(00111010) (72) (58) (3A) ;(00001100) (14) (12) (0C) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ; -;10472;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11000010) (302) (194) (C2) ;(01010001) (121) (81) (51) ;(00101001) (51) (41) (29) ;(01000001) (101) (65) (41) ; -;10480;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00100000) (40) (32) (20) ;(00001000) (10) (8) (08) ;(01111001) (171) (121) (79) ;(11100110) (346) (230) (E6) ;(11100000) (340) (224) (E0) ; -;10488;(11001011) (313) (203) (CB) ;(11111111) (377) (255) (FF) ;(01001111) (117) (79) (4F) ;(00011000) (30) (24) (18) ;(00110111) (67) (55) (37) ;(00101010) (52) (42) (2A) ;(01001011) (113) (75) (4B) ;(01011100) (134) (92) (5C) ; -;10496;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(01111111) (177) (127) (7F) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(10111001) (271) (185) (B9) ;(00100000) (40) (32) (20) ;(00100010) (42) (34) (22) ; -;10504;(00010111) (27) (23) (17) ;(10000111) (207) (135) (87) ;(11110010) (362) (242) (F2) ;(00111111) (77) (63) (3F) ;(00101001) (51) (41) (29) ;(00111000) (70) (56) (38) ;(00110000) (60) (48) (30) ;(11010001) (321) (209) (D1) ; -;10512;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(00100011) (43) (35) (23) ;(00011010) (32) (26) (1A) ;(00010011) (23) (19) (13) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ; -;10520;(11111010) (372) (250) (FA) ;(11110110) (366) (246) (F6) ;(00100000) (40) (32) (20) ;(10111110) (276) (190) (BE) ;(00101000) (50) (40) (28) ;(11110100) (364) (244) (F4) ;(11110110) (366) (246) (F6) ;(10000000) (200) (128) (80) ; -;10528;(10111110) (276) (190) (BE) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(00011010) (32) (26) (1A) ;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ; -;10536;(00010101) (25) (21) (15) ;(11100001) (341) (225) (E1) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11000001) (301) (193) (C1) ; -;10544;(00011000) (30) (24) (18) ;(11001110) (316) (206) (CE) ;(11001011) (313) (203) (CB) ;(11111000) (370) (248) (F8) ;(11010001) (321) (209) (D1) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ; -;10552;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(11001011) (313) (203) (CB) ;(11101000) (350) (232) (E8) ;(00011000) (30) (24) (18) ;(00001101) (15) (13) (0D) ;(11010001) (321) (209) (D1) ;(11010001) (321) (209) (D1) ; -;10560;(11010001) (321) (209) (D1) ;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(11001101) (315) (205) (CD) ;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00110000) (60) (48) (30) ;(00000011) (3) (3) (03) ; -;10568;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11111000) (370) (248) (F8) ;(11100001) (341) (225) (E1) ;(11001011) (313) (203) (CB) ;(00010000) (20) (16) (10) ;(11001011) (313) (203) (CB) ;(01110000) (160) (112) (70) ; -;10576;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(00001011) (13) (11) (0B) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11001010) (312) (202) (CA) ; -;10584;(11101111) (357) (239) (EF) ;(00101000) (50) (40) (28) ;(01111110) (176) (126) (7E) ;(11110110) (366) (246) (F6) ;(01100000) (140) (96) (60) ;(01000111) (107) (71) (47) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ; -;10592;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ;(00101000) (50) (40) (28) ;(00000111) (7) (7) (07) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ; -;10600;(00100011) (43) (35) (23) ;(11001011) (313) (203) (CB) ;(10101000) (250) (168) (A8) ;(01111000) (170) (120) (78) ;(10111001) (271) (185) (B9) ;(00101000) (50) (40) (28) ;(00010010) (22) (18) (12) ;(00100011) (43) (35) (23) ; -;10608;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(11111110) (376) (254) (FE) ; -;10616;(00101001) (51) (41) (29) ;(11001010) (312) (202) (CA) ;(11101111) (357) (239) (EF) ;(00101000) (50) (40) (28) ;(11001101) (315) (205) (CD) ;(10101011) (253) (171) (AB) ;(00101000) (50) (40) (28) ;(00011000) (30) (24) (18) ; -;10624;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(01101001) (151) (105) (69) ;(00100000) (40) (32) (20) ;(00001100) (14) (12) (0C) ;(00100011) (43) (35) (23) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ; -;10632;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110011) (63) (51) (33) ;(11101011) (353) (235) (EB) ;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ; -;10640;(01011100) (134) (92) (5C) ;(11010001) (321) (209) (D1) ;(11010001) (321) (209) (D1) ;(10101111) (257) (175) (AF) ;(00111100) (74) (60) (3C) ;(11001001) (311) (201) (C9) ;(10101111) (257) (175) (AF) ;(01000111) (107) (71) (47) ; -;10648;(11001011) (313) (203) (CB) ;(01111001) (171) (121) (79) ;(00100000) (40) (32) (20) ;(01001011) (113) (75) (4B) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ; -;10656;(00111100) (74) (60) (3C) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(00100011) (43) (35) (23) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ; -;10664;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11011111) (337) (223) (DF) ;(11000011) (303) (195) (C3) ;(01001001) (111) (73) (49) ;(00101010) (52) (42) (2A) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;10672;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11001011) (313) (203) (CB) ;(01110001) (161) (113) (71) ;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ;(00000101) (5) (5) (05) ;(00101000) (50) (40) (28) ; -;10680;(11101000) (350) (232) (E8) ;(11101011) (353) (235) (EB) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(01100001) (141) (97) (61) ;(11101011) (353) (235) (EB) ; -;10688;(11101011) (353) (235) (EB) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(11100001) (341) (225) (E1) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ; -;10696;(00101000) (50) (40) (28) ;(00100000) (40) (32) (20) ;(11001011) (313) (203) (CB) ;(01111001) (171) (121) (79) ;(00101000) (50) (40) (28) ;(01010010) (122) (82) (52) ;(11001011) (313) (203) (CB) ;(01110001) (161) (113) (71) ; -;10704;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00100000) (40) (32) (20) ;(00111100) (74) (60) (3C) ;(11100111) (347) (231) (E7) ;(11001001) (311) (201) (C9) ; -;10712;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(01101100) (154) (108) (6C) ;(11111110) (376) (254) (FE) ;(11001100) (314) (204) (CC) ;(00100000) (40) (32) (20) ;(00110010) (62) (50) (32) ; -;10720;(11011111) (337) (223) (DF) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(01011110) (136) (94) (5E) ;(00100001) (41) (33) (21) ; -;10728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100101) (345) (229) (E5) ;(11100111) (347) (231) (E7) ;(11100001) (341) (225) (E1) ;(01111001) (171) (121) (79) ;(11111110) (376) (254) (FE) ;(11000000) (300) (192) (C0) ; -;10736;(00100000) (40) (32) (20) ;(00001001) (11) (9) (09) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(01010001) (121) (81) (51) ;(11111110) (376) (254) (FE) ; -;10744;(11001100) (314) (204) (CC) ;(00101000) (50) (40) (28) ;(11100101) (345) (229) (E5) ;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00101010) (52) (42) (2A) ; -;10752;(11100011) (343) (227) (E3) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11001100) (314) (204) (CC) ;(00101010) (52) (42) (2A) ;(00111000) (70) (56) (38) ;(00011001) (31) (25) (19) ;(00001011) (13) (11) (0B) ; -;10760;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00101010) (52) (42) (2A) ;(00001001) (11) (9) (09) ;(11010001) (321) (209) (D1) ;(11000001) (301) (193) (C1) ;(00010000) (20) (16) (10) ;(10110011) (263) (179) (B3) ; -;10768;(11001011) (313) (203) (CB) ;(01111001) (171) (121) (79) ;(00100000) (40) (32) (20) ;(01100110) (146) (102) (66) ;(11100101) (345) (229) (E5) ;(11001011) (313) (203) (CB) ;(01110001) (161) (113) (71) ;(00100000) (40) (32) (20) ; -;10776;(00010011) (23) (19) (13) ;(01000010) (102) (66) (42) ;(01001011) (113) (75) (4B) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ; -;10784;(11001111) (317) (207) (CF) ;(00000010) (2) (2) (02) ;(11100111) (347) (231) (E7) ;(11100001) (341) (225) (E1) ;(00010001) (21) (17) (11) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ; -;10792;(11110100) (364) (244) (F4) ;(00101010) (52) (42) (2A) ;(00001001) (11) (9) (09) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00101010) (52) (42) (2A) ;(11100011) (343) (227) (E3) ; -;10800;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00101010) (52) (42) (2A) ;(11000001) (301) (193) (C1) ;(00001001) (11) (9) (09) ;(00100011) (43) (35) (23) ;(01000010) (102) (66) (42) ;(01001011) (113) (75) (4B) ; -;10808;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(10110001) (261) (177) (B1) ;(00101010) (52) (42) (2A) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ; -;10816;(00000111) (7) (7) (07) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(11011011) (333) (219) (DB) ;(11001101) (315) (205) (CD) ;(01010010) (122) (82) (52) ;(00101010) (52) (42) (2A) ; -;10824;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(11111000) (370) (248) (F8) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ; -;10832;(10110110) (266) (182) (B6) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11000100) (304) (196) (C4) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ; -;10840;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(01010000) (120) (80) (50) ;(11010101) (325) (213) (D5) ;(10101111) (257) (175) (AF) ;(11110101) (365) (245) (F5) ; -;10848;(11000101) (305) (197) (C5) ;(00010001) (21) (17) (11) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11011111) (337) (223) (DF) ;(11100001) (341) (225) (E1) ;(11111110) (376) (254) (FE) ;(11001100) (314) (204) (CC) ; -;10856;(00101000) (50) (40) (28) ;(00010111) (27) (23) (17) ;(11110001) (361) (241) (F1) ;(11001101) (315) (205) (CD) ;(11001101) (315) (205) (CD) ;(00101010) (52) (42) (2A) ;(11110101) (365) (245) (F5) ;(01010000) (120) (80) (50) ; -;10864;(01011001) (131) (89) (59) ;(11100101) (345) (229) (E5) ;(11011111) (337) (223) (DF) ;(11100001) (341) (225) (E1) ;(11111110) (376) (254) (FE) ;(11001100) (314) (204) (CC) ;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ; -;10872;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(00011000) (30) (24) (18) ; -;10880;(00010011) (23) (19) (13) ;(11100101) (345) (229) (E5) ;(11100111) (347) (231) (E7) ;(11100001) (341) (225) (E1) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00101000) (50) (40) (28) ;(00001100) (14) (12) (0C) ; -;10888;(11110001) (361) (241) (F1) ;(11001101) (315) (205) (CD) ;(11001101) (315) (205) (CD) ;(00101010) (52) (42) (2A) ;(11110101) (365) (245) (F5) ;(11011111) (337) (223) (DF) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ; -;10896;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ;(00100000) (40) (32) (20) ;(11100110) (346) (230) (E6) ;(11110001) (361) (241) (F1) ;(11100011) (343) (227) (E3) ;(00011001) (31) (25) (19) ;(00101011) (53) (43) (2B) ; -;10904;(11100011) (343) (227) (E3) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ; -;10912;(00000111) (7) (7) (07) ;(00100011) (43) (35) (23) ;(10100111) (247) (167) (A7) ;(11111010) (372) (250) (FA) ;(00100000) (40) (32) (20) ;(00101010) (52) (42) (2A) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ; -;10920;(11010001) (321) (209) (D1) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10110110) (266) (182) (B6) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ; -;10928;(11001000) (310) (200) (C8) ;(10101111) (257) (175) (AF) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10110110) (266) (182) (B6) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ; -;10936;(10101001) (251) (169) (A9) ;(00110011) (63) (51) (33) ;(11000001) (301) (193) (C1) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ; -;10944;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(00100011) (43) (35) (23) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01110000) (160) (112) (70) ;(00100011) (43) (35) (23) ; -;10952;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(10101111) (257) (175) (AF) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(11110101) (365) (245) (F5) ; -;10960;(11001101) (315) (205) (CD) ;(10000010) (202) (130) (82) ;(00011100) (34) (28) (1C) ;(11110001) (361) (241) (F1) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00101000) (50) (40) (28) ; -;10968;(00010010) (22) (18) (12) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(11010001) (321) (209) (D1) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ; -;10976;(00110111) (67) (55) (37) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ;(11100001) (341) (225) (E1) ;(11100101) (345) (229) (E5) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ; -;10984;(01111010) (172) (122) (7A) ;(11011110) (336) (222) (DE) ;(00000000) (0) (0) (00) ;(11100001) (341) (225) (E1) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11101011) (353) (235) (EB) ;(00100011) (43) (35) (23) ; -;10992;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(11001000) (310) (200) (C8) ; -;11000;(11001101) (315) (205) (CD) ;(10101001) (251) (169) (A9) ;(00110000) (60) (48) (30) ;(11011010) (332) (218) (DA) ;(00010101) (25) (21) (15) ;(00011111) (37) (31) (1F) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ; -;11008;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01001110) (116) (78) (4E) ;(00101000) (50) (40) (28) ;(01011110) (136) (94) (5E) ; -;11016;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ; -;11024;(00101000) (50) (40) (28) ;(11111010) (372) (250) (FA) ;(00110000) (60) (48) (30) ;(00001011) (13) (11) (0B) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00010001) (21) (17) (11) ; -;11032;(11111110) (376) (254) (FE) ;(00010110) (26) (22) (16) ;(00110000) (60) (48) (30) ;(00001101) (15) (13) (0D) ;(00100011) (43) (35) (23) ;(00011000) (30) (24) (18) ;(11101101) (355) (237) (ED) ;(11001101) (315) (205) (CD) ; -;11040;(10001000) (210) (136) (88) ;(00101100) (54) (44) (2C) ;(00111000) (70) (56) (38) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ;(11001010) (312) (202) (CA) ;(11000000) (300) (192) (C0) ; -;11048;(00101011) (53) (43) (2B) ;(01111001) (171) (121) (79) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ; -;11056;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(11101011) (353) (235) (EB) ;(11010101) (325) (213) (D5) ;(00101010) (52) (42) (2A) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ; -;11064;(00011011) (33) (27) (1B) ;(11010110) (326) (214) (D6) ;(00000110) (6) (6) (06) ;(01000111) (107) (71) (47) ;(00101000) (50) (40) (28) ;(00010001) (21) (17) (11) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ; -;11072;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00111000) (70) (56) (38) ;(11111010) (372) (250) (FA) ;(11110110) (366) (246) (F6) ;(00100000) (40) (32) (20) ;(00010011) (23) (19) (13) ;(00010010) (22) (18) (12) ; -;11080;(00010000) (20) (16) (10) ;(11110100) (364) (244) (F4) ;(11110110) (366) (246) (F6) ;(10000000) (200) (128) (80) ;(00010010) (22) (18) (12) ;(00111110) (76) (62) (3E) ;(11000000) (300) (192) (C0) ;(00101010) (52) (42) (2A) ; -;11088;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(10101110) (256) (174) (AE) ;(11110110) (366) (246) (F6) ;(00100000) (40) (32) (20) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(11101010) (352) (234) (EA) ; -;11096;(00101011) (53) (43) (2B) ;(11100101) (345) (229) (E5) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11100001) (341) (225) (E1) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ; -;11104;(00000000) (0) (0) (00) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00011000) (30) (24) (18) ;(01000000) (100) (64) (40) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;11112;(00000001) (1) (1) (01) ;(01110110) (166) (118) (76) ;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(00010001) (21) (17) (11) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ; -;11120;(00011000) (30) (24) (18) ;(11100111) (347) (231) (E7) ;(00101010) (52) (42) (2A) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01110010) (162) (114) (72) ; -;11128;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01000110) (106) (70) (46) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01111000) (170) (120) (78) ; -;11136;(10110001) (261) (177) (B1) ;(11001000) (310) (200) (C8) ;(11100101) (345) (229) (E5) ;(11110111) (367) (247) (F7) ;(11010101) (325) (213) (D5) ;(11000101) (305) (197) (C5) ;(01010100) (124) (84) (54) ;(01011101) (135) (93) (5D) ; -;11144;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00100000) (40) (32) (20) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ; -;11152;(00101011) (53) (43) (2B) ;(11100001) (341) (225) (E1) ;(11100011) (343) (227) (E3) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00001001) (11) (9) (09) ;(00110000) (60) (48) (30) ; -;11160;(00000010) (2) (2) (02) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11100011) (343) (227) (E3) ;(11101011) (353) (235) (EB) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ; -;11168;(00000010) (2) (2) (02) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11000001) (301) (193) (C1) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ;(11101011) (353) (235) (EB) ;(01111000) (170) (120) (78) ; -;11176;(10110001) (261) (177) (B1) ;(11001000) (310) (200) (C8) ;(11010101) (325) (213) (D5) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(00101011) (53) (43) (2B) ; -;11184;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(01111110) (176) (126) (7E) ;(11100101) (345) (229) (E5) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(11000110) (306) (198) (C6) ;(00101011) (53) (43) (2B) ; -;11192;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(11000011) (303) (195) (C3) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ; -;11200;(00111110) (76) (62) (3E) ;(11011111) (337) (223) (DF) ;(00101010) (52) (42) (2A) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(10100110) (246) (166) (A6) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ; -;11208;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11101011) (353) (235) (EB) ;(00001001) (11) (9) (09) ;(11000101) (305) (197) (C5) ;(00101011) (53) (43) (2B) ;(00100010) (42) (34) (22) ;(01001101) (115) (77) (4D) ; -;11216;(01011100) (134) (92) (5C) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(00000011) (3) (3) (03) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;11224;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00101010) (52) (42) (2A) ;(01001101) (115) (77) (4D) ;(01011100) (134) (92) (5C) ;(11000001) (301) (193) (C1) ;(11000101) (305) (197) (C5) ; -;11232;(00000011) (3) (3) (03) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11101011) (353) (235) (EB) ;(00100011) (43) (35) (23) ;(11000001) (301) (193) (C1) ;(01110000) (160) (112) (70) ;(00101011) (53) (43) (2B) ; -;11240;(01110001) (161) (113) (71) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(01110111) (167) (119) (77) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;11248;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(01000110) (106) (70) (46) ;(00101011) (53) (43) (2B) ;(01001110) (116) (78) (4E) ; -;11256;(00101011) (53) (43) (2B) ;(01010110) (126) (86) (56) ;(00101011) (53) (43) (2B) ;(01011110) (136) (94) (5E) ;(00101011) (53) (43) (2B) ;(01111110) (176) (126) (7E) ;(00100010) (42) (34) (22) ;(01100101) (145) (101) (65) ; -;11264;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101000) (50) (40) (28) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ; -;11272;(11001101) (315) (205) (CD) ;(00110000) (60) (48) (30) ;(00100101) (45) (37) (25) ;(00100000) (40) (32) (20) ;(00001000) (10) (8) (08) ;(11001011) (313) (203) (CB) ;(10110001) (261) (177) (B1) ;(11001101) (315) (205) (CD) ; -;11280;(10010110) (226) (150) (96) ;(00101001) (51) (41) (29) ;(11001101) (315) (205) (CD) ;(11101110) (356) (238) (EE) ;(00011011) (33) (27) (1B) ;(00111000) (70) (56) (38) ;(00001000) (10) (8) (08) ;(11000101) (305) (197) (C5) ; -;11288;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(11101000) (350) (232) (E8) ;(00011001) (31) (25) (19) ;(11000001) (301) (193) (C1) ;(11001011) (313) (203) (CB) ; -;11296;(11111001) (371) (249) (F9) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11000101) (305) (197) (C5) ;(00100001) (41) (33) (21) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ; -;11304;(01110001) (161) (113) (71) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00101110) (56) (46) (2E) ;(00000101) (5) (5) (05) ;(11101011) (353) (235) (EB) ;(11100111) (347) (231) (E7) ;(00100110) (46) (38) (26) ; -;11312;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(11001100) (314) (204) (CC) ;(00101010) (52) (42) (2A) ;(11011010) (332) (218) (DA) ;(00100000) (40) (32) (20) ;(00101010) (52) (42) (2A) ;(11100001) (341) (225) (E1) ; -;11320;(11000101) (305) (197) (C5) ;(00100100) (44) (36) (24) ;(11100101) (345) (229) (E5) ;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(11001101) (315) (205) (CD) ;(11110100) (364) (244) (F4) ;(00101010) (52) (42) (2A) ; -;11328;(11101011) (353) (235) (EB) ;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00101100) (54) (44) (2C) ;(00101000) (50) (40) (28) ;(11101000) (350) (232) (E8) ;(11111110) (376) (254) (FE) ;(00101001) (51) (41) (29) ; -;11336;(00100000) (40) (32) (20) ;(10111011) (273) (187) (BB) ;(11100111) (347) (231) (E7) ;(11000001) (301) (193) (C1) ;(01111001) (171) (121) (79) ;(01101000) (150) (104) (68) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ; -;11344;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00101001) (51) (41) (29) ;(00011001) (31) (25) (19) ;(11011010) (332) (218) (DA) ;(00010101) (25) (21) (15) ;(00011111) (37) (31) (1F) ;(11010101) (325) (213) (D5) ; -;11352;(11000101) (305) (197) (C5) ;(11100101) (345) (229) (E5) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;11360;(11001101) (315) (205) (CD) ;(01010101) (125) (85) (55) ;(00010110) (26) (22) (16) ;(00100011) (43) (35) (23) ;(01110111) (167) (119) (77) ;(11000001) (301) (193) (C1) ;(00001011) (13) (11) (0B) ;(00001011) (13) (11) (0B) ; -;11368;(00001011) (13) (11) (0B) ;(00100011) (43) (35) (23) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01110000) (160) (112) (70) ;(11000001) (301) (193) (C1) ;(01111000) (170) (120) (78) ;(00100011) (43) (35) (23) ; -;11376;(01110111) (167) (119) (77) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(00011011) (33) (27) (1B) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(01110001) (161) (113) (71) ; -;11384;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(00110110) (66) (54) (36) ;(00100000) (40) (32) (20) ;(11000001) (301) (193) (C1) ;(11101101) (355) (237) (ED) ;(10111000) (270) (184) (B8) ;(11000001) (301) (193) (C1) ; -;11392;(01110000) (160) (112) (70) ;(00101011) (53) (43) (2B) ;(01110001) (161) (113) (71) ;(00101011) (53) (43) (2B) ;(00111101) (75) (61) (3D) ;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ;(11001001) (311) (201) (C9) ; -;11400;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(00111111) (77) (63) (3F) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(01000001) (101) (65) (41) ;(00111111) (77) (63) (3F) ; -;11408;(11010000) (320) (208) (D0) ;(11111110) (376) (254) (FE) ;(01011011) (133) (91) (5B) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(01100001) (141) (97) (61) ;(00111111) (77) (63) (3F) ;(11010000) (320) (208) (D0) ; -;11416;(11111110) (376) (254) (FE) ;(01111011) (173) (123) (7B) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ;(11000100) (304) (196) (C4) ;(00100000) (40) (32) (20) ;(00011001) (31) (25) (19) ;(00010001) (21) (17) (11) ; -;11424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100111) (347) (231) (E7) ;(11010110) (326) (214) (D6) ;(00110001) (61) (49) (31) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; -;11432;(00001010) (12) (10) (0A) ;(11101011) (353) (235) (EB) ;(00111111) (77) (63) (3F) ;(11101101) (355) (237) (ED) ;(01101010) (152) (106) (6A) ;(11011010) (332) (218) (DA) ;(10101101) (255) (173) (AD) ;(00110001) (61) (49) (31) ; -;11440;(11101011) (353) (235) (EB) ;(00011000) (30) (24) (18) ;(11101111) (357) (239) (EF) ;(01000010) (102) (66) (42) ;(01001011) (113) (75) (4B) ;(11000011) (303) (195) (C3) ;(00101011) (53) (43) (2B) ;(00101101) (55) (45) (2D) ; -;11448;(11111110) (376) (254) (FE) ;(00101110) (56) (46) (2E) ;(00101000) (50) (40) (28) ;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00101101) (55) (45) (2D) ;(11111110) (376) (254) (FE) ; -;11456;(00101110) (56) (46) (2E) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ; -;11464;(00100010) (42) (34) (22) ;(00011000) (30) (24) (18) ;(00001010) (12) (10) (0A) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(11011010) (332) (218) (DA) ; -;11472;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(11101111) (357) (239) (EF) ;(10100000) (240) (160) (A0) ;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(10100001) (241) (161) (A1) ;(11000000) (300) (192) (C0) ; -;11480;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11011111) (337) (223) (DF) ;(11001101) (315) (205) (CD) ;(00100010) (42) (34) (22) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(00001011) (13) (11) (0B) ; -;11488;(11101111) (357) (239) (EF) ;(11100000) (340) (224) (E0) ;(10100100) (244) (164) (A4) ;(00000100) (4) (4) (04) ;(11000000) (300) (192) (C0) ;(00000101) (5) (5) (05) ;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ; -;11496;(11100111) (347) (231) (E7) ;(00011000) (30) (24) (18) ;(11101111) (357) (239) (EF) ;(11111110) (376) (254) (FE) ;(01000101) (105) (69) (45) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(11111110) (376) (254) (FE) ; -;11504;(01100101) (145) (101) (65) ;(11000000) (300) (192) (C0) ;(00000110) (6) (6) (06) ;(11111111) (377) (255) (FF) ;(11100111) (347) (231) (E7) ;(11111110) (376) (254) (FE) ;(00101011) (53) (43) (2B) ;(00101000) (50) (40) (28) ; -;11512;(00000101) (5) (5) (05) ;(11111110) (376) (254) (FE) ;(00101101) (55) (45) (2D) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00000100) (4) (4) (04) ;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ; -;11520;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(11001011) (313) (203) (CB) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00101101) (55) (45) (2D) ; -;11528;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(11000001) (301) (193) (C1) ;(11011010) (332) (218) (DA) ;(10101101) (255) (173) (AD) ;(00110001) (61) (49) (31) ;(10100111) (247) (167) (A7) ; -;11536;(11111010) (372) (250) (FA) ;(10101101) (255) (173) (AD) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ; -;11544;(00011000) (30) (24) (18) ;(00110101) (65) (53) (35) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00110000) (60) (48) (30) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(00111010) (72) (58) (3A) ; -;11552;(00111111) (77) (63) (3F) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(11011000) (330) (216) (D8) ;(11010110) (326) (214) (D6) ;(00110000) (60) (48) (30) ; -;11560;(01001111) (117) (79) (4F) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(11111101) (375) (253) (FD) ;(00100001) (41) (33) (21) ;(00111010) (72) (58) (3A) ;(01011100) (134) (92) (5C) ;(10101111) (257) (175) (AF) ; -;11568;(01011111) (137) (95) (5F) ;(01010001) (121) (81) (51) ;(01001000) (110) (72) (48) ;(01000111) (107) (71) (47) ;(11001101) (315) (205) (CD) ;(10110110) (266) (182) (B6) ;(00101010) (52) (42) (2A) ;(11101111) (357) (239) (EF) ; -;11576;(00111000) (70) (56) (38) ;(10100111) (247) (167) (A7) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11101111) (357) (239) (EF) ;(10100000) (240) (160) (A0) ;(00111000) (70) (56) (38) ;(11110001) (361) (241) (F1) ; -;11584;(11001101) (315) (205) (CD) ;(00100010) (42) (34) (22) ;(00101101) (55) (45) (2D) ;(11011000) (330) (216) (D8) ;(11101111) (357) (239) (EF) ;(00000001) (1) (1) (01) ;(10100100) (244) (164) (A4) ;(00000100) (4) (4) (04) ; -;11592;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(01110100) (164) (116) (74) ;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(11110001) (361) (241) (F1) ;(00000111) (7) (7) (07) ; -;11600;(00001111) (17) (15) (0F) ;(00110000) (60) (48) (30) ;(00000010) (2) (2) (02) ;(00101111) (57) (47) (2F) ;(00111100) (74) (60) (3C) ;(11110101) (365) (245) (F5) ;(00100001) (41) (33) (21) ;(10010010) (222) (146) (92) ; -;11608;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00001011) (13) (11) (0B) ;(00110101) (65) (53) (35) ;(11101111) (357) (239) (EF) ;(10100100) (244) (164) (A4) ;(00111000) (70) (56) (38) ;(11110001) (361) (241) (F1) ; -;11616;(11001011) (313) (203) (CB) ;(00111111) (77) (63) (3F) ;(00110000) (60) (48) (30) ;(00001101) (15) (13) (0D) ;(11110101) (365) (245) (F5) ;(11101111) (357) (239) (EF) ;(11000001) (301) (193) (C1) ;(11100000) (340) (224) (E0) ; -;11624;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00110011) (63) (51) (33) ;(00000010) (2) (2) (02) ;(00000101) (5) (5) (05) ;(11100001) (341) (225) (E1) ;(00111000) (70) (56) (38) ; -;11632;(11110001) (361) (241) (F1) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(11110101) (365) (245) (F5) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; -;11640;(11110001) (361) (241) (F1) ;(00011000) (30) (24) (18) ;(11100101) (345) (229) (E5) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(00100011) (43) (35) (23) ; -;11648;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(10101001) (251) (169) (A9) ;(10010001) (221) (145) (91) ;(01011111) (137) (95) (5F) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ; -;11656;(10001001) (211) (137) (89) ;(10101001) (251) (169) (A9) ;(01010111) (127) (87) (57) ;(11001001) (311) (201) (C9) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ;(11100101) (345) (229) (E5) ;(00110110) (66) (54) (36) ; -;11664;(00000000) (0) (0) (00) ;(00100011) (43) (35) (23) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01111011) (173) (123) (7B) ;(10101001) (251) (169) (A9) ;(10010001) (221) (145) (91) ;(01110111) (167) (119) (77) ; -;11672;(00100011) (43) (35) (23) ;(01111010) (172) (122) (7A) ;(10001001) (211) (137) (89) ;(10101001) (251) (169) (A9) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ; -;11680;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ; -;11688;(11101111) (357) (239) (EF) ;(10100010) (242) (162) (A2) ;(00001111) (17) (15) (0F) ;(00100111) (47) (39) (27) ;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ; -;11696;(11100101) (345) (229) (E5) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ;(01000110) (106) (70) (46) ;(11001101) (315) (205) (CD) ;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ;(10101111) (257) (175) (AF) ; -;11704;(10010000) (220) (144) (90) ;(11001011) (313) (203) (CB) ;(01111001) (171) (121) (79) ;(01000010) (102) (66) (42) ;(01001011) (113) (75) (4B) ;(01111011) (173) (123) (7B) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ; -;11712;(11001001) (311) (201) (C9) ;(01010111) (127) (87) (57) ;(00010111) (27) (23) (17) ;(10011111) (237) (159) (9F) ;(01011111) (137) (95) (5F) ;(01001111) (117) (79) (4F) ;(10101111) (257) (175) (AF) ;(01000111) (107) (71) (47) ; -;11720;(11001101) (315) (205) (CD) ;(10110110) (266) (182) (B6) ;(00101010) (52) (42) (2A) ;(11101111) (357) (239) (EF) ;(00110100) (64) (52) (34) ;(11101111) (357) (239) (EF) ;(00011010) (32) (26) (1A) ;(00100000) (40) (32) (20) ; -;11728;(10011010) (232) (154) (9A) ;(10000101) (205) (133) (85) ;(00000100) (4) (4) (04) ;(00100111) (47) (39) (27) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(10100010) (242) (162) (A2) ;(00101101) (55) (45) (2D) ; -;11736;(11011000) (330) (216) (D8) ;(11110101) (365) (245) (F5) ;(00000101) (5) (5) (05) ;(00000100) (4) (4) (04) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(11110001) (361) (241) (F1) ;(00110111) (67) (55) (37) ; -;11744;(11001001) (311) (201) (C9) ;(11110001) (361) (241) (F1) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00001011) (13) (11) (0B) ; -;11752;(00110001) (61) (49) (31) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00001101) (15) (13) (0D) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(00111110) (76) (62) (3E) ;(00110000) (60) (48) (30) ; -;11760;(11010111) (327) (215) (D7) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(00111000) (70) (56) (38) ;(00111110) (76) (62) (3E) ;(00101101) (55) (45) (2D) ;(11010111) (327) (215) (D7) ;(11101111) (357) (239) (EF) ; -;11768;(10100000) (240) (160) (A0) ;(11000011) (303) (195) (C3) ;(11000100) (304) (196) (C4) ;(11000101) (305) (197) (C5) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ; -;11776;(11011001) (331) (217) (D9) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00100111) (47) (39) (27) ;(11000010) (302) (194) (C2) ;(00000011) (3) (3) (03) ;(11100010) (342) (226) (E2) ;(00000001) (1) (1) (01) ; -;11784;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(01000111) (107) (71) (47) ;(11001101) (315) (205) (CD) ; -;11792;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ;(00000110) (6) (6) (06) ;(00010000) (20) (16) (10) ;(01111010) (172) (122) (7A) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ; -;11800;(10110011) (263) (179) (B3) ;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(01010011) (123) (83) (53) ;(00000110) (6) (6) (06) ;(00001000) (10) (8) (08) ;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ; -;11808;(11010001) (321) (209) (D1) ;(11011001) (331) (217) (D9) ;(00011000) (30) (24) (18) ;(01010111) (127) (87) (57) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(11100010) (342) (226) (E2) ;(00111000) (70) (56) (38) ; -;11816;(01111110) (176) (126) (7E) ;(11010110) (326) (214) (D6) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(11000001) (301) (193) (C1) ;(00101101) (55) (45) (2D) ;(01010111) (127) (87) (57) ;(00111010) (72) (58) (3A) ; -;11824;(10101100) (254) (172) (AC) ;(01011100) (134) (92) (5C) ;(10010010) (222) (146) (92) ;(00110010) (62) (50) (32) ;(10101100) (254) (172) (AC) ;(01011100) (134) (92) (5C) ;(01111010) (172) (122) (7A) ;(11001101) (315) (205) (CD) ; -;11832;(01001111) (117) (79) (4F) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00100111) (47) (39) (27) ;(11000001) (301) (193) (C1) ;(00000011) (3) (3) (03) ;(11100001) (341) (225) (E1) ; -;11840;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(11100101) (345) (229) (E5) ;(00110010) (62) (50) (32) ;(10100001) (241) (161) (A1) ;(01011100) (134) (92) (5C) ; -;11848;(00111101) (75) (61) (3D) ;(00010111) (27) (23) (17) ;(10011111) (237) (159) (9F) ;(00111100) (74) (60) (3C) ;(00100001) (41) (33) (21) ;(10101011) (253) (171) (AB) ;(01011100) (134) (92) (5C) ;(01110111) (167) (119) (77) ; -;11856;(00100011) (43) (35) (23) ;(10000110) (206) (134) (86) ;(01110111) (167) (119) (77) ;(11100001) (341) (225) (E1) ;(00011000) (30) (24) (18) ;(01111001) (171) (121) (79) ;(11010110) (326) (214) (D6) ;(10000000) (200) (128) (80) ; -;11864;(11111110) (376) (254) (FE) ;(00011100) (34) (28) (1C) ;(00111000) (70) (56) (38) ;(00010011) (23) (19) (13) ;(11001101) (315) (205) (CD) ;(11000001) (301) (193) (C1) ;(00101101) (55) (45) (2D) ;(11010110) (326) (214) (D6) ; -;11872;(00000111) (7) (7) (07) ;(01000111) (107) (71) (47) ;(00100001) (41) (33) (21) ;(10101100) (254) (172) (AC) ;(01011100) (134) (92) (5C) ;(10000110) (206) (134) (86) ;(01110111) (167) (119) (77) ;(01111000) (170) (120) (78) ; -;11880;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(11001101) (315) (205) (CD) ;(01001111) (117) (79) (4F) ;(00101101) (55) (45) (2D) ;(00011000) (30) (24) (18) ;(10010010) (222) (146) (92) ;(11101011) (353) (235) (EB) ; -;11888;(11001101) (315) (205) (CD) ;(10111010) (272) (186) (BA) ;(00101111) (57) (47) (2F) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(11111010) (372) (250) (FA) ;(01111101) (175) (125) (7D) ;(11011001) (331) (217) (D9) ; -;11896;(11010110) (326) (214) (D6) ;(10000000) (200) (128) (80) ;(01000111) (107) (71) (47) ;(11001011) (313) (203) (CB) ;(00100011) (43) (35) (23) ;(11001011) (313) (203) (CB) ;(00010010) (22) (18) (12) ;(11011001) (331) (217) (D9) ; -;11904;(11001011) (313) (203) (CB) ;(00010011) (23) (19) (13) ;(11001011) (313) (203) (CB) ;(00010010) (22) (18) (12) ;(11011001) (331) (217) (D9) ;(00100001) (41) (33) (21) ;(10101010) (252) (170) (AA) ;(01011100) (134) (92) (5C) ; -;11912;(00001110) (16) (14) (0E) ;(00000101) (5) (5) (05) ;(01111110) (176) (126) (7E) ;(10001111) (217) (143) (8F) ;(00100111) (47) (39) (27) ;(01110111) (167) (119) (77) ;(00101011) (53) (43) (2B) ;(00001101) (15) (13) (0D) ; -;11920;(00100000) (40) (32) (20) ;(11111000) (370) (248) (F8) ;(00010000) (20) (16) (10) ;(11100111) (347) (231) (E7) ;(10101111) (257) (175) (AF) ;(00100001) (41) (33) (21) ;(10100110) (246) (166) (A6) ;(01011100) (134) (92) (5C) ; -;11928;(00010001) (21) (17) (11) ;(10100001) (241) (161) (A1) ;(01011100) (134) (92) (5C) ;(00000110) (6) (6) (06) ;(00001001) (11) (9) (09) ;(11101101) (355) (237) (ED) ;(01101111) (157) (111) (6F) ;(00001110) (16) (14) (0E) ; -;11936;(11111111) (377) (255) (FF) ;(11101101) (355) (237) (ED) ;(01101111) (157) (111) (6F) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(00001101) (15) (13) (0D) ;(00001100) (14) (12) (0C) ;(00100000) (40) (32) (20) ; -;11944;(00001010) (12) (10) (0A) ;(00010010) (22) (18) (12) ;(00010011) (23) (19) (13) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(01110001) (161) (113) (71) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ; -;11952;(01110010) (162) (114) (72) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(01000000) (100) (64) (40) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(00100011) (43) (35) (23) ; -;11960;(00010000) (20) (16) (10) ;(11100111) (347) (231) (E7) ;(00111010) (72) (58) (3A) ;(10101011) (253) (171) (AB) ;(01011100) (134) (92) (5C) ;(11010110) (326) (214) (D6) ;(00001001) (11) (9) (09) ;(00111000) (70) (56) (38) ; -;11968;(00001010) (12) (10) (0A) ;(11111101) (375) (253) (FD) ;(00110101) (65) (53) (35) ;(01110001) (161) (113) (71) ;(00111110) (76) (62) (3E) ;(00000100) (4) (4) (04) ;(11111101) (375) (253) (FD) ;(10111110) (276) (190) (BE) ; -;11976;(01101111) (157) (111) (6F) ;(00011000) (30) (24) (18) ;(01000001) (101) (65) (41) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(11100010) (342) (226) (E2) ;(00111000) (70) (56) (38) ;(11101011) (353) (235) (EB) ; -;11984;(11001101) (315) (205) (CD) ;(10111010) (272) (186) (BA) ;(00101111) (57) (47) (2F) ;(11011001) (331) (217) (D9) ;(00111110) (76) (62) (3E) ;(10000000) (200) (128) (80) ;(10010101) (225) (149) (95) ;(00101110) (56) (46) (2E) ; -;11992;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(11111010) (372) (250) (FA) ;(11011001) (331) (217) (D9) ;(11001101) (315) (205) (CD) ;(11011101) (335) (221) (DD) ;(00101111) (57) (47) (2F) ;(11111101) (375) (253) (FD) ; -;12000;(01111110) (176) (126) (7E) ;(01110001) (161) (113) (71) ;(11111110) (376) (254) (FE) ;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00000110) (6) (6) (06) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ; -;12008;(00010010) (22) (18) (12) ;(11011001) (331) (217) (D9) ;(00011000) (30) (24) (18) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(01111011) (173) (123) (7B) ; -;12016;(11001101) (315) (205) (CD) ;(10001011) (213) (139) (8B) ;(00101111) (57) (47) (2F) ;(01011111) (137) (95) (5F) ;(01111010) (172) (122) (7A) ;(11001101) (315) (205) (CD) ;(10001011) (213) (139) (8B) ;(00101111) (57) (47) (2F) ; -;12024;(01010111) (127) (87) (57) ;(11000101) (305) (197) (C5) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ;(00010000) (20) (16) (10) ;(11110001) (361) (241) (F1) ;(00100001) (41) (33) (21) ;(10100001) (241) (161) (A1) ; -;12032;(01011100) (134) (92) (5C) ;(01111001) (171) (121) (79) ;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(01110001) (161) (113) (71) ;(00001001) (11) (9) (09) ;(01110111) (167) (119) (77) ;(11111101) (375) (253) (FD) ; -;12040;(00110100) (64) (52) (34) ;(01110001) (161) (113) (71) ;(00011000) (30) (24) (18) ;(11010011) (323) (211) (D3) ;(11110101) (365) (245) (F5) ;(00100001) (41) (33) (21) ;(10100001) (241) (161) (A1) ;(01011100) (134) (92) (5C) ; -;12048;(11111101) (375) (253) (FD) ;(01001110) (116) (78) (4E) ;(01110001) (161) (113) (71) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(01000001) (101) (65) (41) ;(11110001) (361) (241) (F1) ; -;12056;(00101011) (53) (43) (2B) ;(01111110) (176) (126) (7E) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(01110111) (167) (119) (77) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ; -;12064;(11111110) (376) (254) (FE) ;(00001010) (12) (10) (0A) ;(00111111) (77) (63) (3F) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(11110001) (361) (241) (F1) ;(00110110) (66) (54) (36) ; -;12072;(00000001) (1) (1) (01) ;(00000100) (4) (4) (04) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(01110010) (162) (114) (72) ;(11111101) (375) (253) (FD) ;(01110000) (160) (112) (70) ;(01110001) (161) (113) (71) ; -;12080;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11011001) (331) (217) (D9) ;(11100001) (341) (225) (E1) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ; -;12088;(10101011) (253) (171) (AB) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(10100001) (241) (161) (A1) ;(01011100) (134) (92) (5C) ;(01111000) (170) (120) (78) ;(11111110) (376) (254) (FE) ;(00001001) (11) (9) (09) ; -;12096;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(11111110) (376) (254) (FE) ;(11111100) (374) (252) (FC) ;(00111000) (70) (56) (38) ;(00100110) (46) (38) (26) ;(10100111) (247) (167) (A7) ;(11001100) (314) (204) (CC) ; -;12104;(11101111) (357) (239) (EF) ;(00010101) (25) (21) (15) ;(10101111) (257) (175) (AF) ;(10010000) (220) (144) (90) ;(11111010) (372) (250) (FA) ;(01010010) (122) (82) (52) ;(00101111) (57) (47) (2F) ;(01000111) (107) (71) (47) ; -;12112;(00011000) (30) (24) (18) ;(00001100) (14) (12) (0C) ;(01111001) (171) (121) (79) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00000011) (3) (3) (03) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ; -;12120;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(11101111) (357) (239) (EF) ;(00010101) (25) (21) (15) ;(00010000) (20) (16) (10) ;(11110100) (364) (244) (F4) ;(01111001) (171) (121) (79) ;(10100111) (247) (167) (A7) ; -;12128;(11001000) (310) (200) (C8) ;(00000100) (4) (4) (04) ;(00111110) (76) (62) (3E) ;(00101110) (56) (46) (2E) ;(11010111) (327) (215) (D7) ;(00111110) (76) (62) (3E) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; -;12136;(11111011) (373) (251) (FB) ;(01000001) (101) (65) (41) ;(00011000) (30) (24) (18) ;(11100110) (346) (230) (E6) ;(01010000) (120) (80) (50) ;(00010101) (25) (21) (15) ;(00000110) (6) (6) (06) ;(00000001) (1) (1) (01) ; -;12144;(11001101) (315) (205) (CD) ;(01001010) (112) (74) (4A) ;(00101111) (57) (47) (2F) ;(00111110) (76) (62) (3E) ;(01000101) (105) (69) (45) ;(11010111) (327) (215) (D7) ;(01001010) (112) (74) (4A) ;(01111001) (171) (121) (79) ; -;12152;(10100111) (247) (167) (A7) ;(11110010) (362) (242) (F2) ;(10000011) (203) (131) (83) ;(00101111) (57) (47) (2F) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(01001111) (117) (79) (4F) ;(00111110) (76) (62) (3E) ; -;12160;(00101101) (55) (45) (2D) ;(00011000) (30) (24) (18) ;(00000010) (2) (2) (02) ;(00111110) (76) (62) (3E) ;(00101011) (53) (43) (2B) ;(11010111) (327) (215) (D7) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;12168;(11000011) (303) (195) (C3) ;(00011011) (33) (27) (1B) ;(00011010) (32) (26) (1A) ;(11010101) (325) (213) (D5) ;(01101111) (157) (111) (6F) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(01011101) (135) (93) (5D) ; -;12176;(01010100) (124) (84) (54) ;(00101001) (51) (41) (29) ;(00101001) (51) (41) (29) ;(00011001) (31) (25) (19) ;(00101001) (51) (41) (29) ;(01011001) (131) (89) (59) ;(00011001) (31) (25) (19) ;(01001100) (114) (76) (4C) ; -;12184;(01111101) (175) (125) (7D) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(01111110) (176) (126) (7E) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(10100111) (247) (167) (A7) ;(11001000) (310) (200) (C8) ; -;12192;(00100011) (43) (35) (23) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(11001011) (313) (203) (CB) ;(11111110) (376) (254) (FE) ;(00101011) (53) (43) (2B) ;(11001000) (310) (200) (C8) ;(11000101) (305) (197) (C5) ; -;12200;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(01000001) (101) (65) (41) ;(01001111) (117) (79) (4F) ;(00110111) (67) (55) (37) ;(00101011) (53) (43) (2B) ; -;12208;(01111110) (176) (126) (7E) ;(00101111) (57) (47) (2F) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(01110111) (167) (119) (77) ;(00010000) (20) (16) (10) ;(11111000) (370) (248) (F8) ;(01111001) (171) (121) (79) ; -;12216;(11000001) (301) (193) (C1) ;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(11110101) (365) (245) (F5) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(01110111) (167) (119) (77) ; -;12224;(00100011) (43) (35) (23) ;(01111001) (171) (121) (79) ;(01001110) (116) (78) (4E) ;(11000101) (305) (197) (C5) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ; -;12232;(11101011) (353) (235) (EB) ;(01010111) (127) (87) (57) ;(01011110) (136) (94) (5E) ;(11010101) (325) (213) (D5) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ; -;12240;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ;(11000001) (301) (193) (C1) ;(11011001) (331) (217) (D9) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ; -;12248;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(11110001) (361) (241) (F1) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(10100111) (247) (167) (A7) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ; -;12256;(00100001) (41) (33) (21) ;(00110000) (60) (48) (30) ;(00010110) (26) (22) (16) ;(11000101) (305) (197) (C5) ;(01000111) (107) (71) (47) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00101101) (55) (45) (2D) ; -;12264;(11001011) (313) (203) (CB) ;(00011010) (32) (26) (1A) ;(11001011) (313) (203) (CB) ;(00011011) (33) (27) (1B) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00011010) (32) (26) (1A) ;(11001011) (313) (203) (CB) ; -;12272;(00011011) (33) (27) (1B) ;(00010000) (20) (16) (10) ;(11110010) (362) (242) (F2) ;(11000001) (301) (193) (C1) ;(11010000) (320) (208) (D0) ;(11001101) (315) (205) (CD) ;(00000100) (4) (4) (04) ;(00110000) (60) (48) (30) ; -;12280;(11000000) (300) (192) (C0) ;(11011001) (331) (217) (D9) ;(10101111) (257) (175) (AF) ;(00101110) (56) (46) (2E) ;(00000000) (0) (0) (00) ;(01010111) (127) (87) (57) ;(01011101) (135) (93) (5D) ;(11011001) (331) (217) (D9) ; -;12288;(00010001) (21) (17) (11) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001001) (311) (201) (C9) ;(00011100) (34) (28) (1C) ;(11000000) (300) (192) (C0) ;(00010100) (24) (20) (14) ;(11000000) (300) (192) (C0) ; -;12296;(11011001) (331) (217) (D9) ;(00011100) (34) (28) (1C) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00010100) (24) (20) (14) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(11101011) (353) (235) (EB) ; -;12304;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00110100) (64) (52) (34) ;(11101011) (353) (235) (EB) ;(00011010) (32) (26) (1A) ;(10110110) (266) (182) (B6) ;(00100000) (40) (32) (20) ;(00100110) (46) (38) (26) ; -;12312;(11010101) (325) (213) (D5) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ; -;12320;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11100001) (341) (225) (E1) ; -;12328;(11101011) (353) (235) (EB) ;(00001001) (11) (9) (09) ;(11101011) (353) (235) (EB) ;(10001110) (216) (142) (8E) ;(00001111) (17) (15) (0F) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(11000011) (303) (195) (C3) ; -;12336;(00100101) (45) (37) (25) ;(00110010) (62) (50) (32) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(01110011) (163) (115) (73) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(00101011) (53) (43) (2B) ; -;12344;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(00101011) (53) (43) (2B) ;(11010001) (321) (209) (D1) ;(11001101) (315) (205) (CD) ;(10010011) (223) (147) (93) ; -;12352;(00110010) (62) (50) (32) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(11011001) (331) (217) (D9) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ; -;12360;(00101111) (57) (47) (2F) ;(01000111) (107) (71) (47) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(10011011) (233) (155) (9B) ;(00101111) (57) (47) (2F) ;(01001111) (117) (79) (4F) ;(10111000) (270) (184) (B8) ; -;12368;(00110000) (60) (48) (30) ;(00000011) (3) (3) (03) ;(01111000) (170) (120) (78) ;(01000001) (101) (65) (41) ;(11101011) (353) (235) (EB) ;(11110101) (365) (245) (F5) ;(10010000) (220) (144) (90) ;(11001101) (315) (205) (CD) ; -;12376;(10111010) (272) (186) (BA) ;(00101111) (57) (47) (2F) ;(11001101) (315) (205) (CD) ;(11011101) (335) (221) (DD) ;(00101111) (57) (47) (2F) ;(11110001) (361) (241) (F1) ;(11100001) (341) (225) (E1) ;(01110111) (167) (119) (77) ; -;12384;(11100101) (345) (229) (E5) ;(01101000) (150) (104) (68) ;(01100001) (141) (97) (61) ;(00011001) (31) (25) (19) ;(11011001) (331) (217) (D9) ;(11101011) (353) (235) (EB) ;(11101101) (355) (237) (ED) ;(01001010) (112) (74) (4A) ; -;12392;(11101011) (353) (235) (EB) ;(01111100) (174) (124) (7C) ;(10001101) (215) (141) (8D) ;(01101111) (157) (111) (6F) ;(00011111) (37) (31) (1F) ;(10101101) (255) (173) (AD) ;(11011001) (331) (217) (D9) ;(11101011) (353) (235) (EB) ; -;12400;(11100001) (341) (225) (E1) ;(00011111) (37) (31) (1F) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00000001) (1) (1) (01) ;(11001101) (315) (205) (CD) ;(11011101) (335) (221) (DD) ; -;12408;(00101111) (57) (47) (2F) ;(00110100) (64) (52) (34) ;(00101000) (50) (40) (28) ;(00100011) (43) (35) (23) ;(11011001) (331) (217) (D9) ;(01111101) (175) (125) (7D) ;(11100110) (346) (230) (E6) ;(10000000) (200) (128) (80) ; -;12416;(11011001) (331) (217) (D9) ;(00100011) (43) (35) (23) ;(01110111) (167) (119) (77) ;(00101011) (53) (43) (2B) ;(00101000) (50) (40) (28) ;(00011111) (37) (31) (1F) ;(01111011) (173) (123) (7B) ;(11101101) (355) (237) (ED) ; -;12424;(01000100) (104) (68) (44) ;(00111111) (77) (63) (3F) ;(01011111) (137) (95) (5F) ;(01111010) (172) (122) (7A) ;(00101111) (57) (47) (2F) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(01010111) (127) (87) (57) ; -;12432;(11011001) (331) (217) (D9) ;(01111011) (173) (123) (7B) ;(00101111) (57) (47) (2F) ;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(01011111) (137) (95) (5F) ;(01111010) (172) (122) (7A) ;(00101111) (57) (47) (2F) ; -;12440;(11001110) (316) (206) (CE) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000111) (7) (7) (07) ;(00011111) (37) (31) (1F) ;(11011001) (331) (217) (D9) ;(00110100) (64) (52) (34) ;(11001010) (312) (202) (CA) ; -;12448;(10101101) (255) (173) (AD) ;(00110001) (61) (49) (31) ;(11011001) (331) (217) (D9) ;(01010111) (127) (87) (57) ;(11011001) (331) (217) (D9) ;(10101111) (257) (175) (AF) ;(11000011) (303) (195) (C3) ;(01010101) (125) (85) (55) ; -;12456;(00110001) (61) (49) (31) ;(11000101) (305) (197) (C5) ;(00000110) (6) (6) (06) ;(00010000) (20) (16) (10) ;(01111100) (174) (124) (7C) ;(01001101) (115) (77) (4D) ;(00100001) (41) (33) (21) ;(00000000) (0) (0) (00) ; -;12464;(00000000) (0) (0) (00) ;(00101001) (51) (41) (29) ;(00111000) (70) (56) (38) ;(00001010) (12) (10) (0A) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ;(00010111) (27) (23) (17) ;(00110000) (60) (48) (30) ; -;12472;(00000011) (3) (3) (03) ;(00011001) (31) (25) (19) ;(00111000) (70) (56) (38) ;(00000010) (2) (2) (02) ;(00010000) (20) (16) (10) ;(11110011) (363) (243) (F3) ;(11000001) (301) (193) (C1) ;(11001001) (311) (201) (C9) ; -;12480;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(11011000) (330) (216) (D8) ;(00100011) (43) (35) (23) ;(10101110) (256) (174) (AE) ;(11001011) (313) (203) (CB) ;(11111110) (376) (254) (FE) ; -;12488;(00101011) (53) (43) (2B) ;(11001001) (311) (201) (C9) ;(00011010) (32) (26) (1A) ;(10110110) (266) (182) (B6) ;(00100000) (40) (32) (20) ;(00100010) (42) (34) (22) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ; -;12496;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ;(11101011) (353) (235) (EB) ;(11100011) (343) (227) (E3) ;(01000001) (101) (65) (41) ;(11001101) (315) (205) (CD) ; -;12504;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ;(01111000) (170) (120) (78) ;(10101001) (251) (169) (A9) ;(01001111) (117) (79) (4F) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(10101001) (251) (169) (A9) ; -;12512;(00110000) (60) (48) (30) ;(11101011) (353) (235) (EB) ;(11100001) (341) (225) (E1) ;(00111000) (70) (56) (38) ;(00001010) (12) (10) (0A) ;(01111010) (172) (122) (7A) ;(10110011) (263) (179) (B3) ;(00100000) (40) (32) (20) ; -;12520;(00000001) (1) (1) (01) ;(01001111) (117) (79) (4F) ;(11001101) (315) (205) (CD) ;(10001110) (216) (142) (8E) ;(00101101) (55) (45) (2D) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11010001) (321) (209) (D1) ; -;12528;(11001101) (315) (205) (CD) ;(10010011) (223) (147) (93) ;(00110010) (62) (50) (32) ;(10101111) (257) (175) (AF) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11011000) (330) (216) (D8) ; -;12536;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(11011001) (331) (217) (D9) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; -;12544;(11101011) (353) (235) (EB) ;(00111000) (70) (56) (38) ;(01011010) (132) (90) (5A) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(10111010) (272) (186) (BA) ;(00101111) (57) (47) (2F) ;(01111000) (170) (120) (78) ; -;12552;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01100010) (142) (98) (62) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(11101101) (355) (237) (ED) ;(01100010) (142) (98) (62) ;(11011001) (331) (217) (D9) ; -;12560;(00000110) (6) (6) (06) ;(00100001) (41) (33) (21) ;(00011000) (30) (24) (18) ;(00010001) (21) (17) (11) ;(00110000) (60) (48) (30) ;(00000101) (5) (5) (05) ;(00011001) (31) (25) (19) ;(11011001) (331) (217) (D9) ; -;12568;(11101101) (355) (237) (ED) ;(01011010) (132) (90) (5A) ;(11011001) (331) (217) (D9) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00011100) (34) (28) (1C) ;(11001011) (313) (203) (CB) ;(00011101) (35) (29) (1D) ; -;12576;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00011100) (34) (28) (1C) ;(11001011) (313) (203) (CB) ;(00011101) (35) (29) (1D) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00011000) (30) (24) (18) ; -;12584;(11001011) (313) (203) (CB) ;(00011001) (31) (25) (19) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00011001) (31) (25) (19) ;(00011111) (37) (31) (1F) ;(00010000) (20) (16) (10) ;(11100100) (344) (228) (E4) ; -;12592;(11101011) (353) (235) (EB) ;(11011001) (331) (217) (D9) ;(11101011) (353) (235) (EB) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ;(01111000) (170) (120) (78) ;(10000001) (201) (129) (81) ; -;12600;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(10100111) (247) (167) (A7) ;(00111101) (75) (61) (3D) ;(00111111) (77) (63) (3F) ;(00010111) (27) (23) (17) ;(00111111) (77) (63) (3F) ;(00011111) (37) (31) (1F) ; -;12608;(11110010) (362) (242) (F2) ;(01000110) (106) (70) (46) ;(00110001) (61) (49) (31) ;(00110000) (60) (48) (30) ;(01101000) (150) (104) (68) ;(10100111) (247) (167) (A7) ;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ; -;12616;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00000110) (6) (6) (06) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(01111010) (172) (122) (7A) ;(11011001) (331) (217) (D9) ;(00100000) (40) (32) (20) ; -;12624;(01011100) (134) (92) (5C) ;(01110111) (167) (119) (77) ;(11011001) (331) (217) (D9) ;(01111000) (170) (120) (78) ;(11011001) (331) (217) (D9) ;(00110000) (60) (48) (30) ;(00010101) (25) (21) (15) ;(01111110) (176) (126) (7E) ; -;12632;(10100111) (247) (167) (A7) ;(00111110) (76) (62) (3E) ;(10000000) (200) (128) (80) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(10101111) (257) (175) (AF) ;(11011001) (331) (217) (D9) ;(10100010) (242) (162) (A2) ; -;12640;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00101111) (57) (47) (2F) ;(00000111) (7) (7) (07) ;(01110111) (167) (119) (77) ;(00111000) (70) (56) (38) ;(00101110) (56) (46) (2E) ;(00100011) (43) (35) (23) ; -;12648;(01110111) (167) (119) (77) ;(00101011) (53) (43) (2B) ;(00011000) (30) (24) (18) ;(00101001) (51) (41) (29) ;(00000110) (6) (6) (06) ;(00100000) (40) (32) (20) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ; -;12656;(01111010) (172) (122) (7A) ;(11011001) (331) (217) (D9) ;(00100000) (40) (32) (20) ;(00010010) (22) (18) (12) ;(00000111) (7) (7) (07) ;(11001011) (313) (203) (CB) ;(00010011) (23) (19) (13) ;(11001011) (313) (203) (CB) ; -;12664;(00010010) (22) (18) (12) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00010011) (23) (19) (13) ;(11001011) (313) (203) (CB) ;(00010010) (22) (18) (12) ;(11011001) (331) (217) (D9) ;(00110101) (65) (53) (35) ; -;12672;(00101000) (50) (40) (28) ;(11010111) (327) (215) (D7) ;(00010000) (20) (16) (10) ;(11101010) (352) (234) (EA) ;(00011000) (30) (24) (18) ;(11010111) (327) (215) (D7) ;(00010111) (27) (23) (17) ;(00110000) (60) (48) (30) ; -;12680;(00001100) (14) (12) (0C) ;(11001101) (315) (205) (CD) ;(00000100) (4) (4) (04) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(11011001) (331) (217) (D9) ;(00010110) (26) (22) (16) ; -;12688;(10000000) (200) (128) (80) ;(11011001) (331) (217) (D9) ;(00110100) (64) (52) (34) ;(00101000) (50) (40) (28) ;(00011000) (30) (24) (18) ;(11100101) (345) (229) (E5) ;(00100011) (43) (35) (23) ;(11011001) (331) (217) (D9) ; -;12696;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ;(01111000) (170) (120) (78) ;(00010111) (27) (23) (17) ;(11001011) (313) (203) (CB) ;(00010110) (26) (22) (16) ;(00011111) (37) (31) (1F) ; -;12704;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01110010) (162) (114) (72) ;(00100011) (43) (35) (23) ;(01110011) (163) (115) (73) ;(11100001) (341) (225) (E1) ; -;12712;(11010001) (321) (209) (D1) ;(11011001) (331) (217) (D9) ;(11100001) (341) (225) (E1) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(11001111) (317) (207) (CF) ;(00000101) (5) (5) (05) ;(11001101) (315) (205) (CD) ; -;12720;(10010011) (223) (147) (93) ;(00110010) (62) (50) (32) ;(11101011) (353) (235) (EB) ;(10101111) (257) (175) (AF) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00111000) (70) (56) (38) ; -;12728;(11110100) (364) (244) (F4) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11011000) (330) (216) (D8) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ; -;12736;(11011001) (331) (217) (D9) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(10111010) (272) (186) (BA) ;(00101111) (57) (47) (2F) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ; -;12744;(01100000) (140) (96) (60) ;(01101001) (151) (105) (69) ;(11011001) (331) (217) (D9) ;(01100001) (141) (97) (61) ;(01101000) (150) (104) (68) ;(10101111) (257) (175) (AF) ;(00000110) (6) (6) (06) ;(11011111) (337) (223) (DF) ; -;12752;(00011000) (30) (24) (18) ;(00010000) (20) (16) (10) ;(00010111) (27) (23) (17) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ;(11011001) (331) (217) (D9) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ; -;12760;(11001011) (313) (203) (CB) ;(00010000) (20) (16) (10) ;(11011001) (331) (217) (D9) ;(00101001) (51) (41) (29) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01101010) (152) (106) (6A) ;(11011001) (331) (217) (D9) ; -;12768;(00111000) (70) (56) (38) ;(00010000) (20) (16) (10) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11011001) (331) (217) (D9) ; -;12776;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(00011001) (31) (25) (19) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01011010) (132) (90) (5A) ;(11011001) (331) (217) (D9) ;(10100111) (247) (167) (A7) ; -;12784;(00011000) (30) (24) (18) ;(00001000) (10) (8) (08) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;12792;(11011001) (331) (217) (D9) ;(00110111) (67) (55) (37) ;(00000100) (4) (4) (04) ;(11111010) (372) (250) (FA) ;(11010010) (322) (210) (D2) ;(00110001) (61) (49) (31) ;(11110101) (365) (245) (F5) ;(00101000) (50) (40) (28) ; -;12800;(11100001) (341) (225) (E1) ;(01011111) (137) (95) (5F) ;(01010001) (121) (81) (51) ;(11011001) (331) (217) (D9) ;(01011001) (131) (89) (59) ;(01010000) (120) (80) (50) ;(11110001) (361) (241) (F1) ;(11001011) (313) (203) (CB) ; -;12808;(00011000) (30) (24) (18) ;(11110001) (361) (241) (F1) ;(11001011) (313) (203) (CB) ;(00011000) (30) (24) (18) ;(11011001) (331) (217) (D9) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ;(01111000) (170) (120) (78) ; -;12816;(10010001) (221) (145) (91) ;(11000011) (303) (195) (C3) ;(00111101) (75) (61) (3D) ;(00110001) (61) (49) (31) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ; -;12824;(10000001) (201) (129) (81) ;(00110000) (60) (48) (30) ;(00000110) (6) (6) (06) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(00011000) (30) (24) (18) ; -;12832;(01010001) (121) (81) (51) ;(11111110) (376) (254) (FE) ;(10010001) (221) (145) (91) ;(00011000) (30) (24) (18) ;(00011010) (32) (26) (1A) ;(11000010) (302) (194) (C2) ;(00111100) (74) (60) (3C) ;(00110000) (60) (48) (30) ; -;12840;(10011111) (237) (159) (9F) ;(01001111) (117) (79) (4F) ;(00111100) (74) (60) (3C) ;(10110011) (263) (179) (B3) ;(10110010) (262) (178) (B2) ;(01111001) (171) (121) (79) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ; -;12848;(00101011) (53) (43) (2B) ;(00110110) (66) (54) (36) ;(10010001) (221) (145) (91) ;(00100011) (43) (35) (23) ;(11100110) (346) (230) (E6) ;(10000000) (200) (128) (80) ;(11000011) (303) (195) (C3) ;(00110010) (62) (50) (32) ; -;12856;(00110000) (60) (48) (30) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00100011) (43) (35) (23) ;(01000110) (106) (70) (46) ;(11001001) (311) (201) (C9) ;(00110000) (60) (48) (30) ; -;12864;(00101100) (54) (44) (2C) ;(11010101) (325) (213) (D5) ;(00101111) (57) (47) (2F) ;(11000110) (306) (198) (C6) ;(10010001) (221) (145) (91) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ; -;12872;(01011110) (136) (94) (5E) ;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ;(11001011) (313) (203) (CB) ;(01111010) (172) (122) (7A) ;(00101000) (50) (40) (28) ; -;12880;(00000001) (1) (1) (01) ;(00001101) (15) (13) (0D) ;(11001011) (313) (203) (CB) ;(11111010) (372) (250) (FA) ;(00000110) (6) (6) (06) ;(00001000) (10) (8) (08) ;(10010000) (220) (144) (90) ;(10000000) (200) (128) (80) ; -;12888;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(01011010) (132) (90) (5A) ;(00010110) (26) (22) (16) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00101000) (50) (40) (28) ;(00000111) (7) (7) (07) ; -;12896;(01000111) (107) (71) (47) ;(11001011) (313) (203) (CB) ;(00111010) (72) (58) (3A) ;(11001011) (313) (203) (CB) ;(00011011) (33) (27) (1B) ;(00010000) (20) (16) (10) ;(11111010) (372) (250) (FA) ;(11001101) (315) (205) (CD) ; -;12904;(10001110) (216) (142) (8E) ;(00101101) (55) (45) (2D) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(01111110) (176) (126) (7E) ;(11010110) (326) (214) (D6) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ; -;12912;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(11010101) (325) (213) (D5) ;(11101011) (353) (235) (EB) ;(00101011) (53) (43) (2B) ;(01000111) (107) (71) (47) ;(11001011) (313) (203) (CB) ;(00111000) (70) (56) (38) ; -;12920;(11001011) (313) (203) (CB) ;(00111000) (70) (56) (38) ;(11001011) (313) (203) (CB) ;(00111000) (70) (56) (38) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ; -;12928;(00101011) (53) (43) (2B) ;(00010000) (20) (16) (10) ;(11111011) (373) (251) (FB) ;(11100110) (346) (230) (E6) ;(00000111) (7) (7) (07) ;(00101000) (50) (40) (28) ;(00001001) (11) (9) (09) ;(01000111) (107) (71) (47) ; -;12936;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11001011) (313) (203) (CB) ;(00100111) (47) (39) (27) ;(00010000) (20) (16) (10) ;(11111100) (374) (252) (FC) ;(10100110) (246) (166) (A6) ;(01110111) (167) (119) (77) ; -;12944;(11101011) (353) (235) (EB) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10010110) (226) (150) (96) ;(00110010) (62) (50) (32) ;(11101011) (353) (235) (EB) ;(01111110) (176) (126) (7E) ; -;12952;(10100111) (247) (167) (A7) ;(11000000) (300) (192) (C0) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ;(10101111) (257) (175) (AF) ;(00100011) (43) (35) (23) ; -;12960;(01110111) (167) (119) (77) ;(00101011) (53) (43) (2B) ;(01110111) (167) (119) (77) ;(00000110) (6) (6) (06) ;(10010001) (221) (145) (91) ;(01111010) (172) (122) (7A) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ; -;12968;(00001000) (10) (8) (08) ;(10110011) (263) (179) (B3) ;(01000010) (102) (66) (42) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(01010011) (123) (83) (53) ;(01011000) (130) (88) (58) ;(00000110) (6) (6) (06) ; -;12976;(10001001) (211) (137) (89) ;(11101011) (353) (235) (EB) ;(00000101) (5) (5) (05) ;(00101001) (51) (41) (29) ;(00110000) (60) (48) (30) ;(11111100) (374) (252) (FC) ;(11001011) (313) (203) (CB) ;(00001001) (11) (9) (09) ; -;12984;(11001011) (313) (203) (CB) ;(00011100) (34) (28) (1C) ;(11001011) (313) (203) (CB) ;(00011101) (35) (29) (1D) ;(11101011) (353) (235) (EB) ;(00101011) (53) (43) (2B) ;(01110011) (163) (115) (73) ;(00101011) (53) (43) (2B) ; -;12992;(01110010) (162) (114) (72) ;(00101011) (53) (43) (2B) ;(01110000) (160) (112) (70) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ; -;13000;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110001) (361) (241) (F1) ;(01001001) (111) (73) (49) ; -;13008;(00001111) (17) (15) (0F) ;(11011010) (332) (218) (DA) ;(10100010) (242) (162) (A2) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00001010) (12) (10) (0A) ;(10001111) (217) (143) (8F) ; -;13016;(00110110) (66) (54) (36) ;(00111100) (74) (60) (3C) ;(00110100) (64) (52) (34) ;(10100001) (241) (161) (A1) ;(00110011) (63) (51) (33) ;(00001111) (17) (15) (0F) ;(00110000) (60) (48) (30) ;(11001010) (312) (202) (CA) ; -;13024;(00110000) (60) (48) (30) ;(10101111) (257) (175) (AF) ;(00110001) (61) (49) (31) ;(01010001) (121) (81) (51) ;(00111000) (70) (56) (38) ;(00011011) (33) (27) (1B) ;(00110101) (65) (53) (35) ;(00100100) (44) (36) (24) ; -;13032;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ; -;13040;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00010100) (24) (20) (14) ;(00110000) (60) (48) (30) ;(00101101) (55) (45) (2D) ; -;13048;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ; -;13056;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(00111011) (73) (59) (3B) ;(00110101) (65) (53) (35) ;(10011100) (234) (156) (9C) ;(00110101) (65) (53) (35) ;(11011110) (336) (222) (DE) ; -;13064;(00110101) (65) (53) (35) ;(10111100) (274) (188) (BC) ;(00110100) (64) (52) (34) ;(01000101) (105) (69) (45) ;(00110110) (66) (54) (36) ;(01101110) (156) (110) (6E) ;(00110100) (64) (52) (34) ;(01101001) (151) (105) (69) ; -;13072;(00110110) (66) (54) (36) ;(11011110) (336) (222) (DE) ;(00110101) (65) (53) (35) ;(01110100) (164) (116) (74) ;(00110110) (66) (54) (36) ;(10110101) (265) (181) (B5) ;(00110111) (67) (55) (37) ;(10101010) (252) (170) (AA) ; -;13080;(00110111) (67) (55) (37) ;(11011010) (332) (218) (DA) ;(00110111) (67) (55) (37) ;(00110011) (63) (51) (33) ;(00111000) (70) (56) (38) ;(01000011) (103) (67) (43) ;(00111000) (70) (56) (38) ;(11100010) (342) (226) (E2) ; -;13088;(00110111) (67) (55) (37) ;(00010011) (23) (19) (13) ;(00110111) (67) (55) (37) ;(11000100) (304) (196) (C4) ;(00110110) (66) (54) (36) ;(10101111) (257) (175) (AF) ;(00110110) (66) (54) (36) ;(01001010) (112) (74) (4A) ; -;13096;(00111000) (70) (56) (38) ;(10010010) (222) (146) (92) ;(00110100) (64) (52) (34) ;(01101010) (152) (106) (6A) ;(00110100) (64) (52) (34) ;(10101100) (254) (172) (AC) ;(00110100) (64) (52) (34) ;(10100101) (245) (165) (A5) ; -;13104;(00110100) (64) (52) (34) ;(10110011) (263) (179) (B3) ;(00110100) (64) (52) (34) ;(00011111) (37) (31) (1F) ;(00110110) (66) (54) (36) ;(11001001) (311) (201) (C9) ;(00110101) (65) (53) (35) ;(00000001) (1) (1) (01) ; -;13112;(00110101) (65) (53) (35) ;(11000000) (300) (192) (C0) ;(00110011) (63) (51) (33) ;(10100000) (240) (160) (A0) ;(00110110) (66) (54) (36) ;(10000110) (206) (134) (86) ;(00110110) (66) (54) (36) ;(11000110) (306) (198) (C6) ; -;13120;(00110011) (63) (51) (33) ;(01111010) (172) (122) (7A) ;(00110110) (66) (54) (36) ;(00000110) (6) (6) (06) ;(00110101) (65) (53) (35) ;(11111001) (371) (249) (F9) ;(00110100) (64) (52) (34) ;(10011011) (233) (155) (9B) ; -;13128;(00110110) (66) (54) (36) ;(10000011) (203) (131) (83) ;(00110111) (67) (55) (37) ;(00010100) (24) (20) (14) ;(00110010) (62) (50) (32) ;(10100010) (242) (162) (A2) ;(00110011) (63) (51) (33) ;(01001111) (117) (79) (4F) ; -;13136;(00101101) (55) (45) (2D) ;(10010111) (227) (151) (97) ;(00110010) (62) (50) (32) ;(01001001) (111) (73) (49) ;(00110100) (64) (52) (34) ;(00011011) (33) (27) (1B) ;(00110100) (64) (52) (34) ;(00101101) (55) (45) (2D) ; -;13144;(00110100) (64) (52) (34) ;(00001111) (17) (15) (0F) ;(00110100) (64) (52) (34) ;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00110101) (65) (53) (35) ;(01111000) (170) (120) (78) ;(00110010) (62) (50) (32) ; -;13152;(01100111) (147) (103) (67) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(11100011) (343) (227) (E3) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(01100101) (145) (101) (65) ; -;13160;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(11100101) (345) (229) (E5) ;(10100111) (247) (167) (A7) ;(11110010) (362) (242) (F2) ;(10000000) (200) (128) (80) ; -;13168;(00110011) (63) (51) (33) ;(01010111) (127) (87) (57) ;(11100110) (346) (230) (E6) ;(01100000) (140) (96) (60) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ;(00001111) (17) (15) (0F) ; -;13176;(11000110) (306) (198) (C6) ;(01111100) (174) (124) (7C) ;(01101111) (157) (111) (6F) ;(01111010) (172) (122) (7A) ;(11100110) (346) (230) (E6) ;(00011111) (37) (31) (1F) ;(00011000) (30) (24) (18) ;(00001110) (16) (14) (0E) ; -;13184;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(11011001) (331) (217) (D9) ;(00000001) (1) (1) (01) ;(11111011) (373) (251) (FB) ;(11111111) (377) (255) (FF) ; -;13192;(01010100) (124) (84) (54) ;(01011101) (135) (93) (5D) ;(00001001) (11) (9) (09) ;(11011001) (331) (217) (D9) ;(00000111) (7) (7) (07) ;(01101111) (157) (111) (6F) ;(00010001) (21) (17) (11) ;(11010111) (327) (215) (D7) ; -;13200;(00110010) (62) (50) (32) ;(00100110) (46) (38) (26) ;(00000000) (0) (0) (00) ;(00011001) (31) (25) (19) ;(01011110) (136) (94) (5E) ;(00100011) (43) (35) (23) ;(01010110) (126) (86) (56) ;(00100001) (41) (33) (21) ; -;13208;(01100101) (145) (101) (65) ;(00110011) (63) (51) (33) ;(11100011) (343) (227) (E3) ;(11010101) (325) (213) (D5) ;(11011001) (331) (217) (D9) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01100110) (146) (102) (66) ; -;13216;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(11110001) (361) (241) (F1) ;(00111010) (72) (58) (3A) ;(01100111) (147) (103) (67) ;(01011100) (134) (92) (5C) ;(11011001) (331) (217) (D9) ;(00011000) (30) (24) (18) ; -;13224;(11000011) (303) (195) (C3) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(00000101) (5) (5) (05) ; -;13232;(00011111) (37) (31) (1F) ;(11100001) (341) (225) (E1) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ; -;13240;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ;(00110011) (63) (51) (33) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ; -;13248;(11001101) (315) (205) (CD) ;(10101001) (251) (169) (A9) ;(00110011) (63) (51) (33) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11001001) (311) (201) (C9) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ; -;13256;(11001101) (315) (205) (CD) ;(10101001) (251) (169) (A9) ;(00110011) (63) (51) (33) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(11011001) (331) (217) (D9) ;(11100011) (343) (227) (E3) ;(11000101) (305) (197) (C5) ; -;13264;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ;(11000000) (300) (192) (C0) ;(00000111) (7) (7) (07) ;(00000111) (7) (7) (07) ;(01001111) (117) (79) (4F) ;(00001100) (14) (12) (0C) ;(01111110) (176) (126) (7E) ; -;13272;(11100110) (346) (230) (E6) ;(00111111) (77) (63) (3F) ;(00100000) (40) (32) (20) ;(00000010) (2) (2) (02) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11000110) (306) (198) (C6) ;(01010000) (120) (80) (50) ; -;13280;(00010010) (22) (18) (12) ;(00111110) (76) (62) (3E) ;(00000101) (5) (5) (05) ;(10010001) (221) (145) (91) ;(00100011) (43) (35) (23) ;(00010011) (23) (19) (13) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ; -;13288;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11000001) (301) (193) (C1) ;(11100011) (343) (227) (E3) ;(11011001) (331) (217) (D9) ;(11100001) (341) (225) (E1) ;(11011001) (331) (217) (D9) ;(01000111) (107) (71) (47) ; -;13296;(10101111) (257) (175) (AF) ;(00000101) (5) (5) (05) ;(11001000) (310) (200) (C8) ;(00010010) (22) (18) (12) ;(00010011) (23) (19) (13) ;(00011000) (30) (24) (18) ;(11111010) (372) (250) (FA) ;(10100111) (247) (167) (A7) ; -;13304;(11001000) (310) (200) (C8) ;(11110101) (365) (245) (F5) ;(11010101) (325) (213) (D5) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(11001000) (310) (200) (C8) ; -;13312;(00110011) (63) (51) (33) ;(11010001) (321) (209) (D1) ;(11110001) (361) (241) (F1) ;(00111101) (75) (61) (3D) ;(00011000) (30) (24) (18) ;(11110010) (362) (242) (F2) ;(01001111) (117) (79) (4F) ;(00000111) (7) (7) (07) ; -;13320;(00000111) (7) (7) (07) ;(10000001) (201) (129) (81) ;(01001111) (117) (79) (4F) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(11001001) (311) (201) (C9) ;(11010101) (325) (213) (D5) ; -;13328;(00101010) (52) (42) (2A) ;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00000110) (6) (6) (06) ;(00110100) (64) (52) (34) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ; -;13336;(00110011) (63) (51) (33) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ; -;13344;(11000101) (305) (197) (C5) ;(00110010) (62) (50) (32) ;(11011001) (331) (217) (D9) ;(11001101) (315) (205) (CD) ;(11110111) (367) (247) (F7) ;(00110011) (63) (51) (33) ;(11001101) (315) (205) (CD) ;(11001000) (310) (200) (C8) ; -;13352;(00110011) (63) (51) (33) ;(11011001) (331) (217) (D9) ;(11100001) (341) (225) (E1) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(11100101) (345) (229) (E5) ;(11101011) (353) (235) (EB) ;(00101010) (52) (42) (2A) ; -;13360;(01101000) (150) (104) (68) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00000110) (6) (6) (06) ;(00110100) (64) (52) (34) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11000000) (300) (192) (C0) ; -;13368;(00110011) (63) (51) (33) ;(11101011) (353) (235) (EB) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(00000110) (6) (6) (06) ;(00000101) (5) (5) (05) ;(00011010) (32) (26) (1A) ;(01001110) (116) (78) (4E) ; -;13376;(11101011) (353) (235) (EB) ;(00010010) (22) (18) (12) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(00010011) (23) (19) (13) ;(00010000) (20) (16) (10) ;(11110111) (367) (247) (F7) ;(11101011) (353) (235) (EB) ; -;13384;(11001001) (311) (201) (C9) ;(01000111) (107) (71) (47) ;(11001101) (315) (205) (CD) ;(01011110) (136) (94) (5E) ;(00110011) (63) (51) (33) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ; -;13392;(00000010) (2) (2) (02) ;(10100000) (240) (160) (A0) ;(11000010) (302) (194) (C2) ;(00110001) (61) (49) (31) ;(11100000) (340) (224) (E0) ;(00000100) (4) (4) (04) ;(11100010) (342) (226) (E2) ;(11000001) (301) (193) (C1) ; -;13400;(00000011) (3) (3) (03) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11000110) (306) (198) (C6) ;(00110011) (63) (51) (33) ;(11001101) (315) (205) (CD) ;(01100010) (142) (98) (62) ;(00110011) (63) (51) (33) ; -;13408;(00001111) (17) (15) (0F) ;(00000001) (1) (1) (01) ;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(00110101) (65) (53) (35) ;(11101110) (356) (238) (EE) ;(11100001) (341) (225) (E1) ;(00000011) (3) (3) (03) ; -;13416;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(00000110) (6) (6) (06) ;(11111111) (377) (255) (FF) ;(00011000) (30) (24) (18) ;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ; -;13424;(00110100) (64) (52) (34) ;(11011000) (330) (216) (D8) ;(00000110) (6) (6) (06) ;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(10100111) (247) (167) (A7) ;(00101000) (50) (40) (28) ;(00001011) (13) (11) (0B) ; -;13432;(00100011) (43) (35) (23) ;(01111000) (170) (120) (78) ;(11100110) (346) (230) (E6) ;(10000000) (200) (128) (80) ;(10110110) (266) (182) (B6) ;(00010111) (27) (23) (17) ;(00111111) (77) (63) (3F) ;(00011111) (37) (31) (1F) ; -;13440;(01110111) (167) (119) (77) ;(00101011) (53) (43) (2B) ;(11001001) (311) (201) (C9) ;(11010101) (325) (213) (D5) ;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(01111111) (177) (127) (7F) ;(00101101) (55) (45) (2D) ; -;13448;(11100001) (341) (225) (E1) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101111) (57) (47) (2F) ;(01001111) (117) (79) (4F) ;(11001101) (315) (205) (CD) ;(10001110) (216) (142) (8E) ;(00101101) (55) (45) (2D) ; -;13456;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(11011000) (330) (216) (D8) ;(11010101) (325) (213) (D5) ;(00010001) (21) (17) (11) ; -;13464;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00100011) (43) (35) (23) ;(11001011) (313) (203) (CB) ;(00010110) (26) (22) (16) ;(00101011) (53) (43) (2B) ;(10011111) (237) (159) (9F) ;(01001111) (117) (79) (4F) ; -;13472;(11001101) (315) (205) (CD) ;(10001110) (216) (142) (8E) ;(00101101) (55) (45) (2D) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ; -;13480;(11101101) (355) (237) (ED) ;(01111000) (170) (120) (78) ;(00011000) (30) (24) (18) ;(00000100) (4) (4) (04) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(00001010) (12) (10) (0A) ; -;13488;(11000011) (303) (195) (C3) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11001101) (315) (205) (CD) ;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(00100001) (41) (33) (21) ;(00101011) (53) (43) (2B) ; -;13496;(00101101) (55) (45) (2D) ;(11100101) (345) (229) (E5) ;(11000101) (305) (197) (C5) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(00001011) (13) (11) (0B) ; -;13504;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00100000) (40) (32) (20) ;(00100011) (43) (35) (23) ;(00011010) (32) (26) (1A) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ; -;13512;(00111000) (70) (56) (38) ;(00001001) (11) (9) (09) ;(11010110) (326) (214) (D6) ;(10010000) (220) (144) (90) ;(00111000) (70) (56) (38) ;(00011001) (31) (25) (19) ;(11111110) (376) (254) (FE) ;(00010101) (25) (21) (15) ; -;13520;(00110000) (60) (48) (30) ;(00010101) (25) (21) (15) ;(00111100) (74) (60) (3C) ;(00111101) (75) (61) (3D) ;(10000111) (207) (135) (87) ;(10000111) (207) (135) (87) ;(10000111) (207) (135) (87) ;(11111110) (376) (254) (FE) ; -;13528;(10101000) (250) (168) (A8) ;(00110000) (60) (48) (30) ;(00001100) (14) (12) (0C) ;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(01111011) (173) (123) (7B) ;(01011100) (134) (92) (5C) ;(10000001) (201) (129) (81) ; -;13536;(01001111) (117) (79) (4F) ;(00110000) (60) (48) (30) ;(00000001) (1) (1) (01) ;(00000100) (4) (4) (04) ;(11000011) (303) (195) (C3) ;(00101011) (53) (43) (2B) ;(00101101) (55) (45) (2D) ;(11001111) (317) (207) (CF) ; -;13544;(00001001) (11) (9) (09) ;(11100101) (345) (229) (E5) ;(11000101) (305) (197) (C5) ;(01000111) (107) (71) (47) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(10110110) (266) (182) (B6) ;(00100011) (43) (35) (23) ; -;13552;(10110110) (266) (182) (B6) ;(00100011) (43) (35) (23) ;(10110110) (266) (182) (B6) ;(01111000) (170) (120) (78) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ;(11000000) (300) (192) (C0) ;(00110111) (67) (55) (37) ; -;13560;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(11011000) (330) (216) (D8) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(00011000) (30) (24) (18) ; -;13568;(00000110) (6) (6) (06) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(00011000) (30) (24) (18) ;(00000101) (5) (5) (05) ;(10101111) (257) (175) (AF) ;(00100011) (43) (35) (23) ; -;13576;(10101110) (256) (174) (AE) ;(00101011) (53) (43) (2B) ;(00000111) (7) (7) (07) ;(11100101) (345) (229) (E5) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ; -;13584;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ;(00010111) (27) (23) (17) ;(01110111) (167) (119) (77) ;(00011111) (37) (31) (1F) ;(00100011) (43) (35) (23) ;(01110111) (167) (119) (77) ;(00100011) (43) (35) (23) ; -;13592;(01110111) (167) (119) (77) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ;(11101011) (353) (235) (EB) ; -;13600;(11011000) (330) (216) (D8) ;(00110111) (67) (55) (37) ;(00011000) (30) (24) (18) ;(11100111) (347) (231) (E7) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ;(00110100) (64) (52) (34) ; -;13608;(11101011) (353) (235) (EB) ;(11010000) (320) (208) (D0) ;(10100111) (247) (167) (A7) ;(00011000) (30) (24) (18) ;(11011110) (336) (222) (DE) ;(11101011) (353) (235) (EB) ;(11001101) (315) (205) (CD) ;(11101001) (351) (233) (E9) ; -;13616;(00110100) (64) (52) (34) ;(11101011) (353) (235) (EB) ;(11010000) (320) (208) (D0) ;(11010101) (325) (213) (D5) ;(00011011) (33) (27) (1B) ;(10101111) (257) (175) (AF) ;(00010010) (22) (18) (12) ;(00011011) (33) (27) (1B) ; -;13624;(00010010) (22) (18) (12) ;(11010001) (321) (209) (D1) ;(11001001) (311) (201) (C9) ;(01111000) (170) (120) (78) ;(11010110) (326) (214) (D6) ;(00001000) (10) (8) (08) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ; -;13632;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00111101) (75) (61) (3D) ;(00001111) (17) (15) (0F) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ; -;13640;(11001101) (315) (205) (CD) ;(00111100) (74) (60) (3C) ;(00110100) (64) (52) (34) ;(11010001) (321) (209) (D1) ;(11101011) (353) (235) (EB) ;(11110001) (361) (241) (F1) ;(11001011) (313) (203) (CB) ;(01010111) (127) (87) (57) ; -;13648;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(00001111) (17) (15) (0F) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(00001111) (17) (15) (0F) ;(00110000) (60) (48) (30) ;(00011000) (30) (24) (18) ; -;13656;(00110011) (63) (51) (33) ;(00001111) (17) (15) (0F) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11010101) (325) (213) (D5) ;(11000101) (305) (197) (C5) ; -;13664;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11100001) (341) (225) (E1) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(11100011) (343) (227) (E3) ;(01111000) (170) (120) (78) ; -;13672;(00100000) (40) (32) (20) ;(00001011) (13) (11) (0B) ;(10110001) (261) (177) (B1) ;(11000001) (301) (193) (C1) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(11110001) (361) (241) (F1) ;(00111111) (77) (63) (3F) ; -;13680;(00011000) (30) (24) (18) ;(00010110) (26) (22) (16) ;(11110001) (361) (241) (F1) ;(00011000) (30) (24) (18) ;(00010011) (23) (19) (13) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ; -;13688;(00011010) (32) (26) (1A) ;(10010110) (226) (150) (96) ;(00111000) (70) (56) (38) ;(00001001) (11) (9) (09) ;(00100000) (40) (32) (20) ;(11101101) (355) (237) (ED) ;(00001011) (13) (11) (0B) ;(00010011) (23) (19) (13) ; -;13696;(00100011) (43) (35) (23) ;(11100011) (343) (227) (E3) ;(00101011) (53) (43) (2B) ;(00011000) (30) (24) (18) ;(11011111) (337) (223) (DF) ;(11000001) (301) (193) (C1) ;(11110001) (361) (241) (F1) ;(10100111) (247) (167) (A7) ; -;13704;(11110101) (365) (245) (F5) ;(11101111) (357) (239) (EF) ;(10100000) (240) (160) (A0) ;(00111000) (70) (56) (38) ;(11110001) (361) (241) (F1) ;(11110101) (365) (245) (F5) ;(11011100) (334) (220) (DC) ;(00000001) (1) (1) (01) ; -;13712;(00110101) (65) (53) (35) ;(11110001) (361) (241) (F1) ;(11110101) (365) (245) (F5) ;(11010100) (324) (212) (D4) ;(11111001) (371) (249) (F9) ;(00110100) (64) (52) (34) ;(11110001) (361) (241) (F1) ;(00001111) (17) (15) (0F) ; -;13720;(11010100) (324) (212) (D4) ;(00000001) (1) (1) (01) ;(00110101) (65) (53) (35) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11010101) (325) (213) (D5) ; -;13728;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11100001) (341) (225) (E1) ;(11100101) (345) (229) (E5) ;(11010101) (325) (213) (D5) ;(11000101) (305) (197) (C5) ; -;13736;(00001001) (11) (9) (09) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11110111) (367) (247) (F7) ;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11000001) (301) (193) (C1) ; -;13744;(11100001) (341) (225) (E1) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11000001) (301) (193) (C1) ; -;13752;(11100001) (341) (225) (E1) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00000010) (2) (2) (02) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00101010) (52) (42) (2A) ; -;13760;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(11111011) (373) (251) (FB) ;(11111111) (377) (255) (FF) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ; -;13768;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(00001110) (16) (14) (0E) ;(00100000) (40) (32) (20) ;(00001100) (14) (12) (0C) ; -;13776;(11110101) (365) (245) (F5) ;(00000001) (1) (1) (01) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11110111) (367) (247) (F7) ;(11110001) (361) (241) (F1) ;(00010010) (22) (18) (12) ;(11001101) (315) (205) (CD) ; -;13784;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11101011) (353) (235) (EB) ;(11001001) (311) (201) (C9) ;(11001111) (317) (207) (CF) ;(00001010) (12) (10) (0A) ;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ; -;13792;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(01111000) (170) (120) (78) ;(11000110) (306) (198) (C6) ;(11100011) (343) (227) (E3) ;(10011111) (237) (159) (9F) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ; -;13800;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11010101) (325) (213) (D5) ;(00000011) (3) (3) (03) ;(11110111) (367) (247) (F7) ;(11100001) (341) (225) (E1) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ; -;13808;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11010101) (325) (213) (D5) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(11101011) (353) (235) (EB) ;(00101011) (53) (43) (2B) ;(00110110) (66) (54) (36) ; -;13816;(00001101) (15) (13) (0D) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(10111110) (276) (190) (BE) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ;(00100100) (44) (36) (24) ; -;13824;(11011111) (337) (223) (DF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(11100001) (341) (225) (E1) ;(11110001) (361) (241) (F1) ;(11111101) (375) (253) (FD) ; -;13832;(10101110) (256) (174) (AE) ;(00000001) (1) (1) (01) ;(11100110) (346) (230) (E6) ;(01000000) (100) (64) (40) ;(11000010) (302) (194) (C2) ;(10001010) (212) (138) (8A) ;(00011100) (34) (28) (1C) ;(00100010) (42) (34) (22) ; -;13840;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00000001) (1) (1) (01) ;(11111110) (376) (254) (FE) ;(11001101) (315) (205) (CD) ;(11111011) (373) (251) (FB) ; -;13848;(00100100) (44) (36) (24) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(10100000) (240) (160) (A0) ;(00000001) (1) (1) (01) ; -;13856;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(11110111) (367) (247) (F7) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ; -;13864;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00111110) (76) (62) (3E) ;(11111111) (377) (255) (FF) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ; -;13872;(11001101) (315) (205) (CD) ;(11100011) (343) (227) (E3) ;(00101101) (55) (45) (2D) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(00010101) (25) (21) (15) ;(00010110) (26) (22) (16) ;(11010001) (321) (209) (D1) ; -;13880;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ; -;13888;(11001101) (315) (205) (CD) ;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11101011) (353) (235) (EB) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10010100) (224) (148) (94) ;(00011110) (36) (30) (1E) ; -;13896;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(11010010) (322) (210) (D2) ;(10011111) (237) (159) (9F) ;(00011110) (36) (30) (1E) ;(00101010) (52) (42) (2A) ;(01010001) (121) (81) (51) ;(01011100) (134) (92) (5C) ; -;13904;(11100101) (345) (229) (E5) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ;(11100110) (346) (230) (E6) ;(00010101) (25) (21) (15) ;(00000001) (1) (1) (01) ; -;13912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000011) (3) (3) (03) ;(00001100) (14) (12) (0C) ;(11110111) (367) (247) (F7) ;(00010010) (22) (18) (12) ;(11001101) (315) (205) (CD) ; -;13920;(10110010) (262) (178) (B2) ;(00101010) (52) (42) (2A) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(00010101) (25) (21) (15) ;(00010110) (26) (22) (16) ;(11000011) (303) (195) (C3) ;(10111111) (277) (191) (BF) ; -;13928;(00110101) (65) (53) (35) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ; -;13936;(00011010) (32) (26) (1A) ;(11000011) (303) (195) (C3) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11001101) (315) (205) (CD) ;(11110001) (361) (241) (F1) ;(00101011) (53) (43) (2B) ;(11000011) (303) (195) (C3) ; -;13944;(00101011) (53) (43) (2B) ;(00101101) (55) (45) (2D) ;(11011001) (331) (217) (D9) ;(11100101) (345) (229) (E5) ;(00100001) (41) (33) (21) ;(01100111) (147) (103) (67) ;(01011100) (134) (92) (5C) ;(00110101) (65) (53) (35) ; -;13952;(11100001) (341) (225) (E1) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(00100011) (43) (35) (23) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(11011001) (331) (217) (D9) ;(01011110) (136) (94) (5E) ; -;13960;(01111011) (173) (123) (7B) ;(00010111) (27) (23) (17) ;(10011111) (237) (159) (9F) ;(01010111) (127) (87) (57) ;(00011001) (31) (25) (19) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(00010011) (23) (19) (13) ; -;13968;(00010011) (23) (19) (13) ;(00011010) (32) (26) (1A) ;(00011011) (33) (27) (1B) ;(00011011) (33) (27) (1B) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(11101111) (357) (239) (EF) ;(11011001) (331) (217) (D9) ; -;13976;(00100011) (43) (35) (23) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ;(11110001) (361) (241) (F1) ;(11011001) (331) (217) (D9) ;(11100011) (343) (227) (E3) ;(11011001) (331) (217) (D9) ;(11001001) (311) (201) (C9) ; -;13984;(11101111) (357) (239) (EF) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(11100000) (340) (224) (E0) ;(00000101) (5) (5) (05) ;(00100111) (47) (39) (27) ;(11100000) (340) (224) (E0) ; -;13992;(00000001) (1) (1) (01) ;(11000000) (300) (192) (C0) ;(00000100) (4) (4) (04) ;(00000011) (3) (3) (03) ;(11100000) (340) (224) (E0) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ; -;14000;(00110001) (61) (49) (31) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00111010) (72) (58) (3A) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(00110001) (61) (49) (31) ; -;14008;(00111010) (72) (58) (3A) ;(11000000) (300) (192) (C0) ;(00000011) (3) (3) (03) ;(11100000) (340) (224) (E0) ;(00000001) (1) (1) (01) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ; -;14016;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00111101) (75) (61) (3D) ;(00110100) (64) (52) (34) ;(11110001) (361) (241) (F1) ; -;14024;(00111000) (70) (56) (38) ;(10101010) (252) (170) (AA) ;(00111011) (73) (59) (3B) ;(00101001) (51) (41) (29) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(00100111) (47) (39) (27) ;(11000011) (303) (195) (C3) ; -;14032;(00000011) (3) (3) (03) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(10001000) (210) (136) (88) ;(00010011) (23) (19) (13) ;(00110110) (66) (54) (36) ; -;14040;(01011000) (130) (88) (58) ;(01100101) (145) (101) (65) ;(01100110) (146) (102) (66) ;(10011101) (235) (157) (9D) ;(01111000) (170) (120) (78) ;(01100101) (145) (101) (65) ;(01000000) (100) (64) (40) ;(10100010) (242) (162) (A2) ; -;14048;(01100000) (140) (96) (60) ;(00110010) (62) (50) (32) ;(11001001) (311) (201) (C9) ;(11100111) (347) (231) (E7) ;(00100001) (41) (33) (21) ;(11110111) (367) (247) (F7) ;(10101111) (257) (175) (AF) ;(00100100) (44) (36) (24) ; -;14056;(11101011) (353) (235) (EB) ;(00101111) (57) (47) (2F) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(00010100) (24) (20) (14) ;(11101110) (356) (238) (EE) ;(01111110) (176) (126) (7E) ;(10111011) (273) (187) (BB) ; -;14064;(10010100) (224) (148) (94) ;(01011000) (130) (88) (58) ;(11110001) (361) (241) (F1) ;(00111010) (72) (58) (3A) ;(01111110) (176) (126) (7E) ;(11111000) (370) (248) (F8) ;(11001111) (317) (207) (CF) ;(11100011) (343) (227) (E3) ; -;14072;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ;(11010101) (325) (213) (D5) ;(00101101) (55) (45) (2D) ;(00100000) (40) (32) (20) ;(00000111) (7) (7) (07) ;(00111000) (70) (56) (38) ;(00000011) (3) (3) (03) ; -;14080;(10000110) (206) (134) (86) ;(00110000) (60) (48) (30) ;(00001001) (11) (9) (09) ;(11001111) (317) (207) (CF) ;(00000101) (5) (5) (05) ;(00111000) (70) (56) (38) ;(00000111) (7) (7) (07) ;(10010110) (226) (150) (96) ; -;14088;(00110000) (60) (48) (30) ;(00000100) (4) (4) (04) ;(11101101) (355) (237) (ED) ;(01000100) (104) (68) (44) ;(01110111) (167) (119) (77) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00000010) (2) (2) (02) ; -;14096;(10100000) (240) (160) (A0) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00111101) (75) (61) (3D) ;(00110001) (61) (49) (31) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ; -;14104;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ;(11001111) (317) (207) (CF) ;(00001001) (11) (9) (09) ;(10100000) (240) (160) (A0) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(01111110) (176) (126) (7E) ; -;14112;(00110110) (66) (54) (36) ;(10000000) (200) (128) (80) ;(11001101) (315) (205) (CD) ;(00101000) (50) (40) (28) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(00110100) (64) (52) (34) ;(00111000) (70) (56) (38) ; -;14120;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(00110100) (64) (52) (34) ;(11110000) (360) (240) (F0) ;(01001100) (114) (76) (4C) ;(11001100) (314) (204) (CC) ; -;14128;(11001100) (314) (204) (CC) ;(11001101) (315) (205) (CD) ;(00000011) (3) (3) (03) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00000001) (1) (1) (01) ;(10100001) (241) (161) (A1) ; -;14136;(00000011) (3) (3) (03) ;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(00110100) (64) (52) (34) ;(11101111) (357) (239) (EF) ;(00000001) (1) (1) (01) ;(00110100) (64) (52) (34) ;(11110000) (360) (240) (F0) ; -;14144;(00110001) (61) (49) (31) ;(01110010) (162) (114) (72) ;(00010111) (27) (23) (17) ;(11111000) (370) (248) (F8) ;(00000100) (4) (4) (04) ;(00000001) (1) (1) (01) ;(10100010) (242) (162) (A2) ;(00000011) (3) (3) (03) ; -;14152;(10100010) (242) (162) (A2) ;(00000011) (3) (3) (03) ;(00110001) (61) (49) (31) ;(00110100) (64) (52) (34) ;(00110010) (62) (50) (32) ;(00100000) (40) (32) (20) ;(00000100) (4) (4) (04) ;(10100010) (242) (162) (A2) ; -;14160;(00000011) (3) (3) (03) ;(10001100) (214) (140) (8C) ;(00010001) (21) (17) (11) ;(10101100) (254) (172) (AC) ;(00010100) (24) (20) (14) ;(00001001) (11) (9) (09) ;(01010110) (126) (86) (56) ;(11011010) (332) (218) (DA) ; -;14168;(10100101) (245) (165) (A5) ;(01011001) (131) (89) (59) ;(00110000) (60) (48) (30) ;(11000101) (305) (197) (C5) ;(01011100) (134) (92) (5C) ;(10010000) (220) (144) (90) ;(10101010) (252) (170) (AA) ;(10011110) (236) (158) (9E) ; -;14176;(01110000) (160) (112) (70) ;(01101111) (157) (111) (6F) ;(01100001) (141) (97) (61) ;(10100001) (241) (161) (A1) ;(11001011) (313) (203) (CB) ;(11011010) (332) (218) (DA) ;(10010110) (226) (150) (96) ;(10100100) (244) (164) (A4) ; -;14184;(00110001) (61) (49) (31) ;(10011111) (237) (159) (9F) ;(10110100) (264) (180) (B4) ;(11100111) (347) (231) (E7) ;(10100000) (240) (160) (A0) ;(11111110) (376) (254) (FE) ;(01011100) (134) (92) (5C) ;(11111100) (374) (252) (FC) ; -;14192;(11101010) (352) (234) (EA) ;(00011011) (33) (27) (1B) ;(01000011) (103) (67) (43) ;(11001010) (312) (202) (CA) ;(00110110) (66) (54) (36) ;(11101101) (355) (237) (ED) ;(10100111) (247) (167) (A7) ;(10011100) (234) (156) (9C) ; -;14200;(01111110) (176) (126) (7E) ;(01011110) (136) (94) (5E) ;(11110000) (360) (240) (F0) ;(01101110) (156) (110) (6E) ;(00100011) (43) (35) (23) ;(10000000) (200) (128) (80) ;(10010011) (223) (147) (93) ;(00000100) (4) (4) (04) ; -;14208;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00111101) (75) (61) (3D) ;(00110100) (64) (52) (34) ;(11101110) (356) (238) (EE) ;(00100010) (42) (34) (22) ; -;14216;(11111001) (371) (249) (F9) ;(10000011) (203) (131) (83) ;(01101110) (156) (110) (6E) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(10100010) (242) (162) (A2) ;(00001111) (17) (15) (0F) ;(00100111) (47) (39) (27) ; -;14224;(00000011) (3) (3) (03) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(00110001) (61) (49) (31) ;(00101010) (52) (42) (2A) ;(10100001) (241) (161) (A1) ; -;14232;(00000011) (3) (3) (03) ;(00110001) (61) (49) (31) ;(00110111) (67) (55) (37) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ; -;14240;(11001001) (311) (201) (C9) ;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(00000001) (1) (1) (01) ;(00110110) (66) (54) (36) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(00011011) (33) (27) (1B) ; -;14248;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00111001) (71) (57) (39) ;(00101010) (52) (42) (2A) ;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(11100000) (340) (224) (E0) ; -;14256;(00000000) (0) (0) (00) ;(00000110) (6) (6) (06) ;(00011011) (33) (27) (1B) ;(00110011) (63) (51) (33) ;(00000011) (3) (3) (03) ;(11101111) (357) (239) (EF) ;(00111001) (71) (57) (39) ;(00110001) (61) (49) (31) ; -;14264;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(10000110) (206) (134) (86) ;(00010100) (24) (20) (14) ; -;14272;(11100110) (346) (230) (E6) ;(01011100) (134) (92) (5C) ;(00011111) (37) (31) (1F) ;(00001011) (13) (11) (0B) ;(10100011) (243) (163) (A3) ;(10001111) (217) (143) (8F) ;(00111000) (70) (56) (38) ;(11101110) (356) (238) (EE) ; -;14280;(11101001) (351) (233) (E9) ;(00010101) (25) (21) (15) ;(01100011) (143) (99) (63) ;(10111011) (273) (187) (BB) ;(00100011) (43) (35) (23) ;(11101110) (356) (238) (EE) ;(10010010) (222) (146) (92) ;(00001101) (15) (13) (0D) ; -;14288;(11001101) (315) (205) (CD) ;(11101101) (355) (237) (ED) ;(11110001) (361) (241) (F1) ;(00100011) (43) (35) (23) ;(01011101) (135) (93) (5D) ;(00011011) (33) (27) (1B) ;(11101010) (352) (234) (EA) ;(00000100) (4) (4) (04) ; -;14296;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00011111) (37) (31) (1F) ;(00000001) (1) (1) (01) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ; -;14304;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11001101) (315) (205) (CD) ;(10010111) (227) (151) (97) ;(00110010) (62) (50) (32) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(10000001) (201) (129) (81) ; -;14312;(00111000) (70) (56) (38) ;(00001110) (16) (14) (0E) ;(11101111) (357) (239) (EF) ;(10100001) (241) (161) (A1) ;(00011011) (33) (27) (1B) ;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00110001) (61) (49) (31) ; -;14320;(00110110) (66) (54) (36) ;(10100011) (243) (163) (A3) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000110) (6) (6) (06) ;(00011011) (33) (27) (1B) ;(00110011) (63) (51) (33) ;(00000011) (3) (3) (03) ; -;14328;(11101111) (357) (239) (EF) ;(10100000) (240) (160) (A0) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(00110001) (61) (49) (31) ;(00001111) (17) (15) (0F) ; -;14336;(10100001) (241) (161) (A1) ;(00000011) (3) (3) (03) ;(10001100) (214) (140) (8C) ;(00010000) (20) (16) (10) ;(10110010) (262) (178) (B2) ;(00010011) (23) (19) (13) ;(00001110) (16) (14) (0E) ;(01010101) (125) (85) (55) ; -;14344;(11100100) (344) (228) (E4) ;(10001101) (215) (141) (8D) ;(01011000) (130) (88) (58) ;(00111001) (71) (57) (39) ;(10111100) (274) (188) (BC) ;(01011011) (133) (91) (5B) ;(10011000) (230) (152) (98) ;(11111101) (375) (253) (FD) ; -;14352;(10011110) (236) (158) (9E) ;(00000000) (0) (0) (00) ;(00110110) (66) (54) (36) ;(01110101) (165) (117) (75) ;(10100000) (240) (160) (A0) ;(11011011) (333) (219) (DB) ;(11101000) (350) (232) (E8) ;(10110100) (264) (180) (B4) ; -;14360;(01100011) (143) (99) (63) ;(01000010) (102) (66) (42) ;(11000100) (304) (196) (C4) ;(11100110) (346) (230) (E6) ;(10110101) (265) (181) (B5) ;(00001001) (11) (9) (09) ;(00110110) (66) (54) (36) ;(10111110) (276) (190) (BE) ; -;14368;(11101001) (351) (233) (E9) ;(00110110) (66) (54) (36) ;(01110011) (163) (115) (73) ;(00011011) (33) (27) (1B) ;(01011101) (135) (93) (5D) ;(11101100) (354) (236) (EC) ;(11011000) (330) (216) (D8) ;(11011110) (336) (222) (DE) ; -;14376;(01100011) (143) (99) (63) ;(10111110) (276) (190) (BE) ;(11110000) (360) (240) (F0) ;(01100001) (141) (97) (61) ;(10100001) (241) (161) (A1) ;(10110011) (263) (179) (B3) ;(00001100) (14) (12) (0C) ;(00000100) (4) (4) (04) ; -;14384;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ;(10100001) (241) (161) (A1) ; -;14392;(00000011) (3) (3) (03) ;(00011011) (33) (27) (1B) ;(00101000) (50) (40) (28) ;(10100001) (241) (161) (A1) ;(00001111) (17) (15) (0F) ;(00000101) (5) (5) (05) ;(00100100) (44) (36) (24) ;(00110001) (61) (49) (31) ; -;14400;(00001111) (17) (15) (0F) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00100010) (42) (34) (22) ;(10100011) (243) (163) (A3) ;(00000011) (3) (3) (03) ;(00011011) (33) (27) (1B) ; -;14408;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11101111) (357) (239) (EF) ;(00110001) (61) (49) (31) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00011110) (36) (30) (1E) ;(10100010) (242) (162) (A2) ; -;14416;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(00000001) (1) (1) (01) ;(00110001) (61) (49) (31) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ;(00100101) (45) (37) (25) ; -;14424;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ;(11000011) (303) (195) (C3) ;(11000100) (304) (196) (C4) ;(00110110) (66) (54) (36) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(00110000) (60) (48) (30) ; -;14432;(00000000) (0) (0) (00) ;(00001001) (11) (9) (09) ;(10100000) (240) (160) (A0) ;(00000001) (1) (1) (01) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00000110) (6) (6) (06) ;(10100001) (241) (161) (A1) ; -;14440;(00000001) (1) (1) (01) ;(00000101) (5) (5) (05) ;(00000010) (2) (2) (02) ;(10100001) (241) (161) (A1) ;(00111000) (70) (56) (38) ;(11001001) (311) (201) (C9) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ; -;14448;(00000010) (2) (2) (02) ;(10011110) (236) (158) (9E) ;(11001101) (315) (205) (CD) ;(00110110) (66) (54) (36) ;(00111001) (71) (57) (39) ;(00101101) (55) (45) (2D) ;(00110110) (66) (54) (36) ;(11111111) (377) (255) (FF) ; -;14456;(11001101) (315) (205) (CD) ;(00101100) (54) (44) (2C) ;(00001111) (17) (15) (0F) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ;(01101110) (156) (110) (6E) ;(11000000) (300) (192) (C0) ; -;14464;(00010001) (21) (17) (11) ;(10100110) (246) (166) (A6) ;(00000001) (1) (1) (01) ;(10101111) (257) (175) (AF) ;(11010101) (325) (213) (D5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00101010) (52) (42) (2A) ; -;14472;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(11110101) (365) (245) (F5) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ; -;14480;(11010001) (321) (209) (D1) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ;(01110101) (165) (117) (75) ;(11111110) (376) (254) (FE) ;(11101010) (352) (234) (EA) ; -;14488;(00101000) (50) (40) (28) ;(01110001) (161) (113) (71) ;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(00000001) (1) (1) (01) ;(00001100) (14) (12) (0C) ;(11001011) (313) (203) (CB) ; -;14496;(01000001) (101) (65) (41) ;(00100000) (40) (32) (20) ;(00001110) (16) (14) (0E) ;(11001101) (315) (205) (CD) ;(01000000) (100) (64) (40) ;(00010010) (22) (18) (12) ;(00110000) (60) (48) (30) ;(00000100) (4) (4) (04) ; -;14504;(11001011) (313) (203) (CB) ;(01111000) (170) (120) (78) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ;(11101011) (353) (235) (EB) ;(10111110) (276) (190) (BE) ;(11101011) (353) (235) (EB) ;(00101000) (50) (40) (28) ; -;14512;(00000011) (3) (3) (03) ;(00100011) (43) (35) (23) ;(00011000) (30) (24) (18) ;(11011101) (335) (221) (DD) ;(00100010) (42) (34) (22) ;(10101100) (254) (172) (AC) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ; -;14520;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(01000000) (100) (64) (40) ;(00010010) (22) (18) (12) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00010011) (23) (19) (13) ;(11101011) (353) (235) (EB) ; -;14528;(10111110) (276) (190) (BE) ;(11101011) (353) (235) (EB) ;(00101000) (50) (40) (28) ;(11110011) (363) (243) (F3) ;(00001000) (10) (8) (08) ;(00011010) (32) (26) (1A) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ; -;14536;(00101000) (50) (40) (28) ;(11110011) (363) (243) (F3) ;(00001000) (10) (8) (08) ;(11111110) (376) (254) (FE) ;(00101110) (56) (46) (2E) ;(00101000) (50) (40) (28) ;(00001011) (13) (11) (0B) ;(11101011) (353) (235) (EB) ; -;14544;(11110110) (366) (246) (F6) ;(10000000) (200) (128) (80) ;(10111110) (276) (190) (BE) ;(11101011) (353) (235) (EB) ;(00100000) (40) (32) (20) ;(10111000) (270) (184) (B8) ;(11111110) (376) (254) (FE) ;(11000000) (300) (192) (C0) ; -;14552;(00111000) (70) (56) (38) ;(00010000) (20) (16) (10) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ; -;14560;(00101011) (53) (43) (2B) ;(11111110) (376) (254) (FE) ;(00100100) (44) (36) (24) ;(00101000) (50) (40) (28) ;(10101001) (251) (169) (A9) ;(11001101) (315) (205) (CD) ;(10001101) (215) (141) (8D) ;(00101100) (54) (44) (2C) ; -;14568;(00111000) (70) (56) (38) ;(10100100) (244) (164) (A4) ;(11101101) (355) (237) (ED) ;(01011011) (133) (91) (5B) ;(10101100) (254) (172) (AC) ;(01011100) (134) (92) (5C) ;(00011011) (33) (27) (1B) ;(00011010) (32) (26) (1A) ; -;14576;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(11111010) (372) (250) (FA) ;(00010011) (23) (19) (13) ;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ; -;14584;(11110001) (361) (241) (F1) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ;(11010001) (321) (209) (D1) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; -;14592;(11111111) (377) (255) (FF) ;(11001011) (313) (203) (CB) ;(01101010) (152) (106) (6A) ;(11000000) (300) (192) (C0) ;(01110111) (167) (119) (77) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(10000010) (202) (130) (82) ; -;14600;(00110110) (66) (54) (36) ;(11101010) (352) (234) (EA) ;(11110101) (365) (245) (F5) ;(00010001) (21) (17) (11) ;(00000001) (1) (1) (01) ;(00000010) (2) (2) (02) ;(11110001) (361) (241) (F1) ;(11010110) (326) (214) (D6) ; -;14608;(00000001) (1) (1) (01) ;(00111000) (70) (56) (38) ;(00001110) (16) (14) (0E) ;(11111110) (376) (254) (FE) ;(10100100) (244) (164) (A4) ;(11001000) (310) (200) (C8) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ; -;14616;(11100001) (341) (225) (E1) ;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(11001011) (313) (203) (CB) ;(01111110) (176) (126) (7E) ;(00101000) (50) (40) (28) ;(11111011) (373) (251) (FB) ;(00100011) (43) (35) (23) ; -;14624;(11101011) (353) (235) (EB) ;(11000011) (303) (195) (C3) ;(10000100) (204) (132) (84) ;(00111000) (70) (56) (38) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00001100) (14) (12) (0C) ;(01111110) (176) (126) (7E) ; -;14632;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ;(00100001) (41) (33) (21) ;(01101010) (152) (106) (6A) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11101110) (356) (238) (EE) ;(00100000) (40) (32) (20) ; -;14640;(01110111) (167) (119) (77) ;(11001101) (315) (205) (CD) ;(00110110) (66) (54) (36) ;(00111001) (71) (57) (39) ;(11001111) (317) (207) (CF) ;(00001000) (10) (8) (08) ;(00100001) (41) (33) (21) ;(00111011) (73) (59) (3B) ; -;14648;(01011100) (134) (92) (5C) ;(11001011) (313) (203) (CB) ;(11011110) (336) (222) (DE) ;(11001011) (313) (203) (CB) ;(11010110) (326) (214) (D6) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110000) (60) (48) (30) ; -;14656;(01101110) (156) (110) (6E) ;(11001000) (310) (200) (C8) ;(11111101) (375) (253) (FD) ;(11001011) (313) (203) (CB) ;(00110111) (67) (55) (37) ;(01101110) (156) (110) (6E) ;(11000000) (300) (192) (C0) ;(11001011) (313) (203) (CB) ; -;14664;(10011110) (236) (158) (9E) ;(11001011) (313) (203) (CB) ;(10010110) (226) (150) (96) ;(11001001) (311) (201) (C9) ;(00010100) (24) (20) (14) ;(00000001) (1) (1) (01) ;(00100000) (40) (32) (20) ;(01010011) (123) (83) (53) ; -;14672;(01110100) (164) (116) (74) ;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01100001) (141) (97) (61) ;(01101101) (155) (109) (6D) ;(01110011) (163) (115) (73) ;(00000110) (6) (6) (06) ;(01000110) (106) (70) (46) ; -;14680;(01110010) (162) (114) (72) ;(01100101) (145) (101) (65) ;(01100101) (145) (101) (65) ;(00111010) (72) (58) (3A) ;(10100000) (240) (160) (A0) ;(00000110) (6) (6) (06) ;(00010100) (24) (20) (14) ;(00000000) (0) (0) (00) ; -;14688;(10001101) (215) (141) (8D) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01001101) (115) (77) (4D) ;(00100000) (40) (32) (20) ;(01000011) (103) (67) (43) ;(01001111) (117) (79) (4F) ;(01001101) (115) (77) (4D) ; -;14696;(01001101) (115) (77) (4D) ;(01000001) (101) (65) (41) ;(01001110) (116) (78) (4E) ;(01000100) (104) (68) (44) ;(11010011) (323) (211) (D3) ;(10000110) (206) (134) (86) ;(01010110) (126) (86) (56) ;(00110001) (61) (49) (31) ; -;14704;(00101110) (56) (46) (2E) ;(00110011) (63) (51) (33) ;(10110010) (262) (178) (B2) ;(10000110) (206) (134) (86) ;(01010011) (123) (83) (53) ;(01010100) (124) (84) (54) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ; -;14712;(01000001) (101) (65) (41) ;(01001101) (115) (77) (4D) ;(11010011) (323) (211) (D3) ;(01000100) (104) (68) (44) ;(01000101) (105) (69) (45) ;(01001100) (114) (76) (4C) ;(01000101) (105) (69) (45) ;(01010100) (124) (84) (54) ; -;14720;(01000101) (105) (69) (45) ;(10100000) (240) (160) (A0) ;(01010010) (122) (82) (52) ;(01000101) (105) (69) (45) ;(01001110) (116) (78) (4E) ;(01010101) (125) (85) (55) ;(01001101) (115) (77) (4D) ;(01000010) (102) (66) (42) ; -;14728;(01000101) (105) (69) (45) ;(11010010) (322) (210) (D2) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(01001110) (116) (78) (4E) ;(01001101) (115) (77) (4D) ;(01001001) (111) (73) (49) ;(10100000) (240) (160) (A0) ; -;14736;(00100000) (40) (32) (20) ;(01110011) (163) (115) (73) ;(01110100) (164) (116) (74) ;(01100001) (141) (97) (61) ;(01110010) (162) (114) (72) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01110011) (163) (115) (73) ; -;14744;(01110100) (164) (116) (74) ;(01100101) (145) (101) (65) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100110) (146) (102) (66) ;(01101001) (151) (105) (69) ;(01110010) (162) (114) (72) ; -;14752;(01110011) (163) (115) (73) ;(01110100) (164) (116) (74) ;(00100000) (40) (32) (20) ;(01101100) (154) (108) (6C) ;(01100001) (141) (97) (61) ;(01110011) (163) (115) (73) ;(01110100) (164) (116) (74) ;(11111101) (375) (253) (FD) ; -;14760;(11001011) (313) (203) (CB) ;(00001100) (14) (12) (0C) ;(01111110) (176) (126) (7E) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(00101000) (50) (40) (28) ; -;14768;(00111101) (75) (61) (3D) ;(00101010) (52) (42) (2A) ;(01011001) (131) (89) (59) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(11101010) (352) (234) (EA) ;(00100000) (40) (32) (20) ; -;14776;(00110101) (65) (53) (35) ;(00110110) (66) (54) (36) ;(11100100) (344) (228) (E4) ;(00111110) (76) (62) (3E) ;(10100111) (247) (167) (A7) ;(00010001) (21) (17) (11) ;(10000010) (202) (130) (82) ;(00111001) (71) (57) (39) ; -;14784;(11001101) (315) (205) (CD) ;(10000100) (204) (132) (84) ;(00111000) (70) (56) (38) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11001101) (315) (205) (CD) ;(10101111) (257) (175) (AF) ;(00001101) (15) (13) (0D) ; -;14792;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ;(01100000) (140) (96) (60) ;(00111001) (71) (57) (39) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ; -;14800;(11110001) (361) (241) (F1) ;(11110101) (365) (245) (F5) ;(11111110) (376) (254) (FE) ;(00000101) (5) (5) (05) ;(00111000) (70) (56) (38) ;(00001111) (17) (15) (0F) ;(00010001) (21) (17) (11) ;(10011011) (233) (155) (9B) ; -;14808;(00111001) (71) (57) (39) ;(00000001) (1) (1) (01) ;(00001100) (14) (12) (0C) ;(00000000) (0) (0) (00) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ;(00001110) (16) (14) (0E) ;(00010111) (27) (23) (17) ; -;14816;(00011110) (36) (30) (1E) ;(10010000) (220) (144) (90) ;(11001101) (315) (205) (CD) ;(00111100) (74) (60) (3C) ;(00100000) (40) (32) (20) ;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ;(11010111) (327) (215) (D7) ; -;14824;(11110001) (361) (241) (F1) ;(00111100) (74) (60) (3C) ;(11111110) (376) (254) (FE) ;(00000111) (7) (7) (07) ;(00100000) (40) (32) (20) ;(11011011) (333) (219) (DB) ;(11100001) (341) (225) (E1) ;(00100010) (42) (34) (22) ; -;14832;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11000011) (303) (195) (C3) ;(10110010) (262) (178) (B2) ;(00011011) (33) (27) (1B) ;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(01110111) (167) (119) (77) ; -;14840;(00000000) (0) (0) (00) ;(11001101) (315) (205) (CD) ;(10101111) (257) (175) (AF) ;(00001101) (15) (13) (0D) ;(11011111) (337) (223) (DF) ;(00011000) (30) (24) (18) ;(00000010) (2) (2) (02) ;(11111111) (377) (255) (FF) ; -;14848;(11111111) (377) (255) (FF) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ; -;14856;(00111000) (70) (56) (38) ;(10111011) (273) (187) (BB) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(00111011) (73) (59) (3B) ;(00101101) (55) (45) (2D) ;(11010001) (321) (209) (D1) ;(00010100) (24) (20) (14) ; -;14864;(00011000) (30) (24) (18) ;(11101010) (352) (234) (EA) ;(00001000) (10) (8) (08) ;(11111110) (376) (254) (FE) ;(10100110) (246) (166) (A6) ;(00111000) (70) (56) (38) ;(00100001) (41) (33) (21) ;(00100000) (40) (32) (20) ; -;14872;(01111011) (173) (123) (7B) ;(00010101) (25) (21) (15) ;(00010101) (25) (21) (15) ;(00100000) (40) (32) (20) ;(10101000) (250) (168) (A8) ;(11001101) (315) (205) (CD) ;(10001100) (214) (140) (8C) ;(00011000) (30) (24) (18) ; -;14880;(00100000) (40) (32) (20) ;(10100011) (243) (163) (A3) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(10001100) (214) (140) (8C) ; -;14888;(00011000) (30) (24) (18) ;(11101011) (353) (235) (EB) ;(11100001) (341) (225) (E1) ;(00100000) (40) (32) (20) ;(10011000) (230) (152) (98) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;14896;(00011001) (31) (25) (19) ;(00111000) (70) (56) (38) ;(10010010) (222) (146) (92) ;(11001101) (315) (205) (CD) ;(11100101) (345) (229) (E5) ;(00011001) (31) (25) (19) ;(00011000) (30) (24) (18) ;(10110110) (266) (182) (B6) ; -;14904;(00010001) (21) (17) (11) ;(01001011) (113) (75) (4B) ;(00111001) (71) (57) (39) ;(11001101) (315) (205) (CD) ;(00010011) (23) (19) (13) ;(00000000) (0) (0) (00) ;(00010001) (21) (17) (11) ;(01111110) (176) (126) (7E) ; -;14912;(00000000) (0) (0) (00) ;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00011001) (31) (25) (19) ;(11101101) (355) (237) (ED) ;(01110010) (162) (114) (72) ;(01111101) (175) (125) (7D) ; -;14920;(00101111) (57) (47) (2F) ;(01101111) (157) (111) (6F) ;(01111100) (174) (124) (7C) ;(00101111) (57) (47) (2F) ;(01100111) (147) (103) (67) ;(11111110) (376) (254) (FE) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; -;14928;(00000011) (3) (3) (03) ;(00100010) (42) (34) (22) ;(10010100) (224) (148) (94) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(10010111) (227) (151) (97) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ; -;14936;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(11100011) (343) (227) (E3) ;(00101101) (55) (45) (2D) ;(00010001) (21) (17) (11) ;(01011100) (134) (92) (5C) ;(00111001) (71) (57) (39) ; -;14944;(11001101) (315) (205) (CD) ;(00010011) (23) (19) (13) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(11111101) (375) (253) (FD) ;(00100001) (41) (33) (21) ;(00010000) (20) (16) (10) ;(01011100) (134) (92) (5C) ; -;14952;(10100111) (247) (167) (A7) ;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ;(01001111) (117) (79) (4F) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ; -;14960;(11010111) (327) (215) (D7) ;(00111110) (76) (62) (3E) ;(00001101) (15) (13) (0D) ;(11001101) (315) (205) (CD) ;(10000101) (205) (133) (85) ;(00101111) (57) (47) (2F) ;(00111110) (76) (62) (3E) ;(00000110) (6) (6) (06) ; -;14968;(11010111) (327) (215) (D7) ;(11100001) (341) (225) (E1) ;(01001110) (116) (78) (4E) ;(00101100) (54) (44) (2C) ;(01000110) (106) (70) (46) ;(00101100) (54) (44) (2C) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ; -;14976;(00101000) (50) (40) (28) ;(00001010) (12) (10) (0A) ;(11011101) (335) (221) (DD) ;(00101010) (52) (42) (2A) ;(01001111) (117) (79) (4F) ;(01011100) (134) (92) (5C) ;(11011101) (335) (221) (DD) ;(00001001) (11) (9) (09) ; -;14984;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000011) (3) (3) (03) ;(11010111) (327) (215) (D7) ;(11110001) (361) (241) (F1) ;(00111100) (74) (60) (3C) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ; -;14992;(00100000) (40) (32) (20) ;(11010110) (326) (214) (D6) ;(00011000) (30) (24) (18) ;(10100010) (242) (162) (A2) ;(01111010) (172) (122) (7A) ;(11111110) (376) (254) (FE) ;(00000100) (4) (4) (04) ;(00101000) (50) (40) (28) ; -;15000;(00011100) (34) (28) (1C) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(11111110) (376) (254) (FE) ;(00000010) (2) (2) (02) ;(00101000) (50) (40) (28) ;(00001101) (15) (13) (0D) ;(00110000) (60) (48) (30) ; -;15008;(00001110) (16) (14) (0E) ;(10100111) (247) (167) (A7) ;(00100000) (40) (32) (20) ;(00000101) (5) (5) (05) ;(11101111) (357) (239) (EF) ;(10100100) (244) (164) (A4) ;(00110001) (61) (49) (31) ;(00000100) (4) (4) (04) ; -;15016;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(10100100) (244) (164) (A4) ;(00111000) (70) (56) (38) ;(11101111) (357) (239) (EF) ;(10100001) (241) (161) (A1) ;(00111000) (70) (56) (38) ;(00000001) (1) (1) (01) ; -;15024;(11111111) (377) (255) (FF) ;(00111111) (77) (63) (3F) ;(11001101) (315) (205) (CD) ;(00101011) (53) (43) (2B) ;(00101101) (55) (45) (2D) ;(11101111) (357) (239) (EF) ;(11000100) (304) (196) (C4) ;(11000011) (303) (195) (C3) ; -;15032;(00000010) (2) (2) (02) ;(11000010) (302) (194) (C2) ;(00000010) (2) (2) (02) ;(00110001) (61) (49) (31) ;(00110111) (67) (55) (37) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; -;15040;(00011000) (30) (24) (18) ;(11010000) (320) (208) (D0) ;(11000001) (301) (193) (C1) ;(00000010) (2) (2) (02) ;(11000000) (300) (192) (C0) ;(00000010) (2) (2) (02) ;(00111000) (70) (56) (38) ;(11001101) (315) (205) (CD) ; -;15048;(01011010) (132) (90) (5A) ;(00111100) (74) (60) (3C) ;(00101010) (52) (42) (2A) ;(10010110) (226) (150) (96) ;(01011100) (134) (92) (5C) ;(00010001) (21) (17) (11) ;(00010000) (20) (16) (10) ;(00100111) (47) (39) (27) ; -;15056;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00110000) (60) (48) (30) ;(11101011) (353) (235) (EB) ;(00011001) (31) (25) (19) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ; -;15064;(00011001) (31) (25) (19) ;(00101000) (50) (40) (28) ;(00001111) (17) (15) (0F) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(10010100) (224) (148) (94) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ; -;15072;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11010001) (321) (209) (D1) ;(00101000) (50) (40) (28) ;(00000101) (5) (5) (05) ;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ; -;15080;(00110000) (60) (48) (30) ;(00111111) (77) (63) (3F) ;(00101010) (52) (42) (2A) ;(10100011) (243) (163) (A3) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ; -;15088;(00011001) (31) (25) (19) ;(01010110) (126) (86) (56) ;(00100011) (43) (35) (23) ;(01011110) (136) (94) (5E) ;(00101010) (52) (42) (2A) ;(10010110) (226) (150) (96) ;(01011100) (134) (92) (5C) ;(10100111) (247) (167) (A7) ; -;15096;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00110000) (60) (48) (30) ;(11000100) (304) (196) (C4) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; -;15104;(11111111) (377) (255) (FF) ;(00101010) (52) (42) (2A) ;(10011110) (236) (158) (9E) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11010101) (325) (213) (D5) ; -;15112;(00101010) (52) (42) (2A) ;(10010100) (224) (148) (94) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(01101110) (156) (110) (6E) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11010001) (321) (209) (D1) ; -;15120;(10100111) (247) (167) (A7) ;(11101101) (355) (237) (ED) ;(01010010) (122) (82) (52) ;(00111000) (70) (56) (38) ;(10101011) (253) (171) (AB) ;(00011000) (30) (24) (18) ;(00010010) (22) (18) (12) ;(11101111) (357) (239) (EF) ; -;15128;(11100100) (344) (228) (E4) ;(11000011) (303) (195) (C3) ;(00111000) (70) (56) (38) ;(10100111) (247) (167) (A7) ;(11001101) (315) (205) (CD) ;(01011011) (133) (91) (5B) ;(00111100) (74) (60) (3C) ;(00110111) (67) (55) (37) ; -;15136;(00001000) (10) (8) (08) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00111100) (74) (60) (3C) ;(00001000) (10) (8) (08) ;(00110000) (60) (48) (30) ;(11111000) (370) (248) (F8) ;(00011000) (30) (24) (18) ; -;15144;(10010111) (227) (151) (97) ;(00101010) (52) (42) (2A) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11100110) (346) (230) (E6) ; -;15152;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11100100) (344) (228) (E4) ;(11100101) (345) (229) (E5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ; -;15160;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(00000110) (6) (6) (06) ;(00100011) (43) (35) (23) ; -;15168;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00100010) (42) (34) (22) ;(00100000) (40) (32) (20) ;(11111010) (372) (250) (FA) ;(11111110) (376) (254) (FE) ;(11101010) (352) (234) (EA) ;(00100000) (40) (32) (20) ; -;15176;(00001001) (11) (9) (09) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ; -;15184;(00011000) (30) (24) (18) ;(11011100) (334) (220) (DC) ;(11001101) (315) (205) (CD) ;(10110110) (266) (182) (B6) ;(00011000) (30) (24) (18) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ; -;15192;(11010100) (324) (212) (D4) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00100001) (41) (33) (21) ;(11111001) (371) (249) (F9) ;(00111100) (74) (60) (3C) ;(10111110) (276) (190) (BE) ; -;15200;(00101000) (50) (40) (28) ;(00000110) (6) (6) (06) ;(00101100) (54) (44) (2C) ;(00100000) (40) (32) (20) ;(11111010) (372) (250) (FA) ;(11011111) (337) (223) (DF) ;(00011000) (30) (24) (18) ;(11010001) (321) (209) (D1) ; -;15208;(11100111) (347) (231) (E7) ;(11001101) (315) (205) (CD) ;(00011011) (33) (27) (1B) ;(00101101) (55) (45) (2D) ;(00111000) (70) (56) (38) ;(11001100) (314) (204) (CC) ;(00100010) (42) (34) (22) ;(01011011) (133) (91) (5B) ; -;15216;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(00011010) (32) (26) (1A) ;(00101101) (55) (45) (2D) ;(00100011) (43) (35) (23) ;(00110000) (60) (48) (30) ;(11111010) (372) (250) (FA) ;(11111110) (376) (254) (FE) ; -;15224;(00001110) (16) (14) (0E) ;(00100000) (40) (32) (20) ;(10111111) (277) (191) (BF) ;(00110101) (65) (53) (35) ;(00110100) (64) (52) (34) ;(00100000) (40) (32) (20) ;(00101011) (53) (43) (2B) ;(11001101) (315) (205) (CD) ; -;15232;(00111001) (71) (57) (39) ;(00110010) (62) (50) (32) ;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(01001000) (110) (72) (48) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ; -;15240;(00000110) (6) (6) (06) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00111000) (70) (56) (38) ;(11110101) (365) (245) (F5) ;(00011000) (30) (24) (18) ;(10101011) (253) (171) (AB) ;(11001101) (315) (205) (CD) ; -;15248;(10001111) (217) (143) (8F) ;(00011000) (30) (24) (18) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(01101110) (156) (110) (6E) ;(01100111) (147) (103) (67) ;(11111110) (376) (254) (FE) ;(01000000) (100) (64) (40) ; -;15256;(00111000) (70) (56) (38) ;(00001000) (10) (8) (08) ;(00100001) (41) (33) (21) ;(00001111) (17) (15) (0F) ;(00100111) (47) (39) (27) ;(00100010) (42) (34) (22) ;(10010110) (226) (150) (96) ;(01011100) (134) (92) (5C) ; -;15264;(00011000) (30) (24) (18) ;(00010101) (25) (21) (15) ;(00100010) (42) (34) (22) ;(10100011) (243) (163) (A3) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ;(10101000) (250) (168) (A8) ;(01011100) (134) (92) (5C) ; -;15272;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00111000) (70) (56) (38) ;(01010000) (120) (80) (50) ;(00101010) (52) (42) (2A) ;(10011110) (236) (158) (9E) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ; -;15280;(11101101) (355) (237) (ED) ;(01000010) (102) (66) (42) ;(00110000) (60) (48) (30) ;(01001000) (110) (72) (48) ;(11001101) (315) (205) (CD) ;(01011010) (132) (90) (5A) ;(00111100) (74) (60) (3C) ;(00010001) (21) (17) (11) ; -;15288;(10000001) (201) (129) (81) ;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00001010) (12) (10) (0A) ;(00010001) (21) (17) (11) ;(10000101) (205) (133) (85) ;(00000000) (0) (0) (00) ; -;15296;(00101010) (52) (42) (2A) ;(01100101) (145) (101) (65) ;(01011100) (134) (92) (5C) ;(00011001) (31) (25) (19) ;(11101101) (355) (237) (ED) ;(01110010) (162) (114) (72) ;(11110101) (365) (245) (F5) ;(11001101) (315) (205) (CD) ; -;15304;(00000001) (1) (1) (01) ;(00111100) (74) (60) (3C) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(01110111) (167) (119) (77) ;(11110001) (361) (241) (F1) ;(11101101) (355) (237) (ED) ; -;15312;(01001011) (113) (75) (4B) ;(10010110) (226) (150) (96) ;(01011100) (134) (92) (5C) ;(00111000) (70) (56) (38) ;(00001111) (17) (15) (0F) ;(11001101) (315) (205) (CD) ;(00000001) (1) (1) (01) ;(00111100) (74) (60) (3C) ; -;15320;(00110110) (66) (54) (36) ;(10110000) (260) (176) (B0) ;(00100011) (43) (35) (23) ;(00110110) (66) (54) (36) ;(00100010) (42) (34) (22) ;(11001101) (315) (205) (CD) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; -;15328;(00110110) (66) (54) (36) ;(00100010) (42) (34) (22) ;(00011000) (30) (24) (18) ;(00000011) (3) (3) (03) ;(01110001) (161) (113) (71) ;(00100011) (43) (35) (23) ;(01110000) (160) (112) (70) ;(11001101) (315) (205) (CD) ; -;15336;(00011011) (33) (27) (1B) ;(00011010) (32) (26) (1A) ;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(00101011) (53) (43) (2B) ;(00101011) (53) (43) (2B) ;(11011101) (335) (221) (DD) ; -;15344;(00110100) (64) (52) (34) ;(00000010) (2) (2) (02) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11011101) (335) (221) (DD) ;(00110100) (64) (52) (34) ;(00000011) (3) (3) (03) ;(11001101) (315) (205) (CD) ; -;15352;(00011010) (32) (26) (1A) ;(00101101) (55) (45) (2D) ;(00110000) (60) (48) (30) ;(11110010) (362) (242) (F2) ;(11011111) (337) (223) (DF) ;(00011000) (30) (24) (18) ;(10001110) (216) (142) (8E) ;(11111111) (377) (255) (FF) ; -;15360;(11111111) (377) (255) (FF) ;(00101010) (52) (42) (2A) ;(01011011) (133) (91) (5B) ;(01011100) (134) (92) (5C) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ;(00011000) (30) (24) (18) ;(00010000) (20) (16) (10) ; -;15368;(11000001) (301) (193) (C1) ;(11011101) (335) (221) (DD) ;(01111110) (176) (126) (7E) ;(00000010) (2) (2) (02) ;(11011101) (335) (221) (DD) ;(00110101) (65) (53) (35) ;(00000010) (2) (2) (02) ;(10100111) (247) (167) (A7) ; -;15376;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11011101) (335) (221) (DD) ;(00110101) (65) (53) (35) ;(00000011) (3) (3) (03) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00001110) (16) (14) (0E) ; -;15384;(00100000) (40) (32) (20) ;(11101010) (352) (234) (EA) ;(11001001) (311) (201) (C9) ;(00101010) (52) (42) (2A) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ; -;15392;(00111111) (77) (63) (3F) ;(11010000) (320) (208) (D0) ;(01000110) (106) (70) (46) ;(00100011) (43) (35) (23) ;(01001110) (116) (78) (4E) ;(00101011) (53) (43) (2B) ;(11000101) (305) (197) (C5) ;(11001101) (315) (205) (CD) ; -;15400;(10111000) (270) (184) (B8) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11000101) (305) (197) (C5) ;(11011101) (335) (221) (DD) ;(11100001) (341) (225) (E1) ;(11000001) (301) (193) (C1) ;(11001101) (315) (205) (CD) ; -;15408;(10000000) (200) (128) (80) ;(00011001) (31) (25) (19) ;(00110000) (60) (48) (30) ;(11101010) (352) (234) (EA) ;(00001000) (10) (8) (08) ;(10100111) (247) (167) (A7) ;(00001000) (10) (8) (08) ;(00100011) (43) (35) (23) ; -;15416;(00100011) (43) (35) (23) ;(01111110) (176) (126) (7E) ;(00100011) (43) (35) (23) ;(01100110) (146) (102) (66) ;(01101111) (157) (111) (6F) ;(11011101) (335) (221) (DD) ;(11100101) (345) (229) (E5) ;(11000001) (301) (193) (C1) ; -;15424;(00001001) (11) (9) (09) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(00100011) (43) (35) (23) ;(11000101) (305) (197) (C5) ;(01000100) (104) (68) (44) ;(01001101) (115) (77) (4D) ;(11010101) (325) (213) (D5) ; -;15432;(11000101) (305) (197) (C5) ;(00011010) (32) (26) (1A) ;(01100010) (142) (98) (62) ;(01101011) (153) (107) (6B) ;(00100011) (43) (35) (23) ;(11101101) (355) (237) (ED) ;(10110000) (260) (176) (B0) ;(00010010) (22) (18) (12) ; -;15440;(11000001) (301) (193) (C1) ;(11010001) (321) (209) (D1) ;(11100001) (341) (225) (E1) ;(00101011) (53) (43) (2B) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(11001000) (310) (200) (C8) ;(11100101) (345) (229) (E5) ; -;15448;(00011000) (30) (24) (18) ;(11101101) (355) (237) (ED) ;(00110111) (67) (55) (37) ;(00001000) (10) (8) (08) ;(00101010) (52) (42) (2A) ;(01010011) (123) (83) (53) ;(01011100) (134) (92) (5C) ;(11101101) (355) (237) (ED) ; -;15456;(01011011) (133) (91) (5B) ;(10010100) (224) (148) (94) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11101101) (355) (237) (ED) ; -;15464;(01001011) (113) (75) (4B) ;(10011110) (236) (158) (9E) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00011001) (31) (25) (19) ;(00111000) (70) (56) (38) ;(00011101) (35) (29) (1D) ; -;15472;(11101101) (355) (237) (ED) ;(01001011) (113) (75) (4B) ;(10100011) (243) (163) (A3) ;(01011100) (134) (92) (5C) ;(11001101) (315) (205) (CD) ;(10000000) (200) (128) (80) ;(00011001) (31) (25) (19) ;(00101000) (50) (40) (28) ; -;15480;(00000010) (2) (2) (02) ;(00110000) (60) (48) (30) ;(00010010) (22) (18) (12) ;(11100101) (345) (229) (E5) ;(00001000) (10) (8) (08) ;(00111000) (70) (56) (38) ;(00000011) (3) (3) (03) ;(01110010) (162) (114) (72) ; -;15488;(00100011) (43) (35) (23) ;(01110011) (163) (115) (73) ;(00001000) (10) (8) (08) ;(11101101) (355) (237) (ED) ;(01010011) (123) (83) (53) ;(10010110) (226) (150) (96) ;(01011100) (134) (92) (5C) ;(00101010) (52) (42) (2A) ; -;15496;(10011001) (231) (153) (99) ;(01011100) (134) (92) (5C) ;(00011001) (31) (25) (19) ;(11101011) (353) (235) (EB) ;(11100001) (341) (225) (E1) ;(11001101) (315) (205) (CD) ;(00111001) (71) (57) (39) ;(00110010) (62) (50) (32) ; -;15504;(00100011) (43) (35) (23) ;(00001001) (11) (9) (09) ;(00011000) (30) (24) (18) ;(11001111) (317) (207) (CF) ;(00111110) (76) (62) (3E) ;(00100000) (40) (32) (20) ;(11010111) (327) (215) (D7) ;(01111000) (170) (120) (78) ; -;15512;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(00100000) (40) (32) (20) ;(00001000) (10) (8) (08) ;(00010001) (21) (17) (11) ;(10001001) (211) (137) (89) ;(00111001) (71) (57) (39) ;(11001101) (315) (205) (CD) ; -;15520;(00010011) (23) (19) (13) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00010101) (25) (21) (15) ;(11000011) (303) (195) (C3) ;(01000011) (103) (67) (43) ;(00010011) (23) (19) (13) ;(01111110) (176) (126) (7E) ; -;15528;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001000) (310) (200) (C8) ;(11001101) (315) (205) (CD) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11111110) (376) (254) (FE) ;(00010101) (25) (21) (15) ; -;15536;(11010000) (320) (208) (D0) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(11011000) (330) (216) (D8) ;(11000011) (303) (195) (C3) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11001101) (315) (205) (CD) ; -;15544;(10011001) (231) (153) (99) ;(00011110) (36) (30) (1E) ;(01111000) (170) (120) (78) ;(11111110) (376) (254) (FE) ;(01000000) (100) (64) (40) ;(00011000) (30) (24) (18) ;(00001011) (13) (11) (0B) ;(11001101) (315) (205) (CD) ; -;15552;(11001101) (315) (205) (CD) ;(00111100) (74) (60) (3C) ;(01111000) (170) (120) (78) ;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000100) (4) (4) (04) ;(01111001) (171) (121) (79) ; -;15560;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ;(11011000) (330) (216) (D8) ;(11001111) (317) (207) (CF) ;(00001010) (12) (10) (0A) ;(11001101) (315) (205) (CD) ;(00000111) (7) (7) (07) ;(00100011) (43) (35) (23) ; -;15568;(01111010) (172) (122) (7A) ;(10000011) (203) (131) (83) ;(11010000) (320) (208) (D0) ;(11001111) (317) (207) (CF) ;(00001010) (12) (10) (0A) ;(01010111) (127) (87) (57) ;(01111000) (170) (120) (78) ;(10110001) (261) (177) (B1) ; -;15576;(01111010) (172) (122) (7A) ;(11000010) (302) (194) (C2) ;(00000001) (1) (1) (01) ;(00010111) (27) (23) (17) ;(11001111) (317) (207) (CF) ;(00010111) (27) (23) (17) ;(01001011) (113) (75) (4B) ;(00000110) (6) (6) (06) ; -;15584;(01010011) (123) (83) (53) ;(00000100) (4) (4) (04) ;(01010000) (120) (80) (50) ;(00000010) (2) (2) (02) ;(00000000) (0) (0) (00) ;(11100001) (341) (225) (E1) ;(11001001) (311) (201) (C9) ;(00100001) (41) (33) (21) ; -;15592;(00001000) (10) (8) (08) ;(01011100) (134) (92) (5C) ;(01110101) (165) (117) (75) ;(01111110) (176) (126) (7E) ;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(00101000) (50) (40) (28) ;(00000100) (4) (4) (04) ; -;15600;(11111110) (376) (254) (FE) ;(00100000) (40) (32) (20) ;(00111000) (70) (56) (38) ;(11110111) (367) (247) (F7) ;(11000011) (303) (195) (C3) ;(10110101) (265) (181) (B5) ;(00010000) (20) (16) (10) ;(11111111) (377) (255) (FF) ; -;15608;(11111111) (377) (255) (FF) ;(11101100) (354) (236) (EC) ;(11101101) (355) (237) (ED) ;(11100101) (345) (229) (E5) ;(11110111) (367) (247) (F7) ;(11110000) (360) (240) (F0) ;(11100001) (341) (225) (E1) ;(11001010) (312) (202) (CA) ; +;0;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;8;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ; +;16;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;24;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;32;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;40;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;48;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;56;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;64;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ; +;72;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;80;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;88;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;96;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;104;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;112;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;120;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;128;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;136;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;144;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;152;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;160;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ; +;168;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ; +;176;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;184;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;192;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;200;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;208;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;216;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ; +;224;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;232;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;240;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;248;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;256;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;264;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;272;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;280;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;288;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ; +;296;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;304;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ; +;312;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;320;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;328;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;336;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;344;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;352;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;360;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;368;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;376;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ; +;384;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;392;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;400;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;408;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;416;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;424;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;432;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;440;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;448;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ; +;456;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;464;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;472;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;480;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;488;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;496;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;504;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;512;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;520;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;528;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;536;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;544;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;552;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;560;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;568;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ; +;576;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ; +;584;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(10110000) (260) (176) (B0) ;(10100000) (240) (160) (A0) ; +;592;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ; +;600;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;624;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;632;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;640;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;648;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;656;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;664;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ; +;672;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;680;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;688;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;696;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;704;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;712;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;720;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;728;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ; +;736;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;744;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;752;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;760;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;768;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;776;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;784;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;792;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ; +;800;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;808;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;816;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;824;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;832;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;848;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;856;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;864;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;872;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;880;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;888;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;896;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;904;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ; +;912;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;920;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;928;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;936;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;944;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;952;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;960;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;968;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;976;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;984;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;992;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ; +;1000;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ; +;1008;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;1016;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ; +;1024;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;1032;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;1040;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;1048;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;1056;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;1064;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;1072;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;1080;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;1088;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;1096;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ; +;1104;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;1112;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;1120;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;1128;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ; +;1136;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;1144;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ; +;1152;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;1160;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ; +;1168;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ; +;1176;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1184;(10000000) (200) (128) (80) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;1192;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;1200;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;1208;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;1216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ; +;1224;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ; +;1232;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;1240;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;1248;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ; +;1256;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;1264;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1272;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ; +;1280;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(01100000) (140) (96) (60) ; +;1288;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ; +;1296;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;1304;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;1312;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;1320;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;1328;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;1336;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;1344;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1352;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;1360;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;1368;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;1376;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;1384;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;1392;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;1400;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;1408;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;1416;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;1424;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;1432;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;1440;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ; +;1448;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;1456;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;1464;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;1472;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ; +;1480;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;1488;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;1496;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;1504;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ; +;1512;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;1520;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;1528;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;1536;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ; +;1544;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;1552;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;1560;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;1568;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;1576;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;1584;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;1592;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ; +;1600;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;1608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;1616;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;1624;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;1632;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;1640;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;1648;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ; +;1656;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;1664;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;1672;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ; +;1680;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;1688;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;1696;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;1704;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;1712;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;1720;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;1728;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;1736;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;1744;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ; +;1752;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;1760;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;1768;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;1776;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;1784;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;1792;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;1800;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;1808;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;1816;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;1824;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;1832;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;1840;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;1848;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;1856;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;1864;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;1872;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;1880;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;1888;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;1896;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;1904;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;1912;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ; +;1920;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;1928;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;1936;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;1944;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;1952;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;1960;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;1968;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;1976;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;1984;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;1992;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ; +;2000;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;2008;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;2016;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;2024;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ; +;2032;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;2040;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;2048;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;2056;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;2064;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;2072;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;2080;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2088;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ; +;2096;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;2104;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2112;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;2120;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;2128;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;2136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;2144;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;2152;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;2160;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;2168;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;2176;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;2184;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;2192;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;2200;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ; +;2208;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;2216;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;2224;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ; +;2232;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;2240;(10000000) (200) (128) (80) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;2248;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;2256;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;2264;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ; +;2272;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ; +;2280;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;2288;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;2296;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;2304;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;2312;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;2320;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;2328;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;2336;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;2344;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;2352;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;2360;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;2368;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;2376;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;2384;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;2392;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;2400;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ; +;2408;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;2416;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ; +;2424;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;2432;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;2440;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;2448;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;2456;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;2464;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;2472;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;2480;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;2488;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;2496;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;2504;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;2512;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;2520;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;2528;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;2536;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;2544;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;2552;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ; +;2560;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;2568;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;2576;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;2584;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;2592;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;2600;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2608;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;2616;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ; +;2624;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;2632;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;2640;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;2648;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;2656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;2664;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ; +;2672;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ; +;2680;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;2688;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;2696;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;2704;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;2712;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;2720;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;2728;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11010000) (320) (208) (D0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;2736;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;2744;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;2752;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ; +;2760;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;2768;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;2776;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;2784;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;2792;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;2800;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;2808;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;2816;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;2824;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;2832;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ; +;2840;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;2848;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;2856;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;2864;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ; +;2872;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;2880;(10010000) (220) (144) (90) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11100000) (340) (224) (E0) ; +;2888;(11110000) (360) (240) (F0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;2896;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;2904;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;2912;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;2920;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;2928;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;2936;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;2944;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ; +;2952;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;2960;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;2968;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;2976;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ; +;2984;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;2992;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;3000;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;3008;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;3016;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;3024;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;3032;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;3040;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;3048;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ; +;3056;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;3064;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;3072;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;3080;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;3088;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;3096;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;3104;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;3112;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ; +;3120;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;3128;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ; +;3136;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;3144;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;3152;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;3160;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;3168;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10110000) (260) (176) (B0) ; +;3176;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ; +;3184;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;3192;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ; +;3200;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;3208;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ; +;3216;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;3224;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;3232;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;3240;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;3248;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;3256;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ; +;3264;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;3272;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;3280;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;3288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;3296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ; +;3304;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;3312;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;3320;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(10110000) (260) (176) (B0) ; +;3328;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;3336;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;3344;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;3352;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;3360;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ; +;3368;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3376;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ; +;3384;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;3392;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;3400;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ; +;3408;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ; +;3416;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ; +;3424;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;3432;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;3440;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;3448;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;3456;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3464;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;3472;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;3480;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;3488;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;3496;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;3504;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;3512;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;3520;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;3528;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;3536;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;3544;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;3552;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;3560;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;3568;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ; +;3576;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;3584;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;3592;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;3600;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;3608;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;3616;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;3624;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ; +;3632;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;3640;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;3648;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ; +;3656;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3664;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;3672;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;3680;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;3688;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;3696;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;3704;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;3712;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;3720;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ; +;3728;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;3736;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;3744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;3752;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;3760;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;3768;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;3776;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;3784;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;3792;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;3800;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;3808;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;3816;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ; +;3824;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ; +;3832;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;3840;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;3848;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ; +;3856;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;3864;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;3872;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;3880;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;3888;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;3896;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;3904;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;3912;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;3920;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;3928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;3936;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;3944;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;3952;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ; +;3960;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ; +;3968;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;3976;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;3984;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ; +;3992;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;4000;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;4008;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ; +;4016;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;4024;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;4032;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;4040;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;4048;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;4056;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;4064;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;4072;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;4080;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ; +;4088;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;4096;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;4104;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;4112;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;4120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;4128;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;4136;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;4144;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;4152;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;4160;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;4168;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;4176;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;4184;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;4192;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;4200;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;4208;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;4216;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;4224;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;4232;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ; +;4240;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;4248;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;4256;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;4264;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ; +;4272;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;4280;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;4288;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;4296;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;4304;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;4312;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;4320;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;4328;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ; +;4336;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;4344;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;4352;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ; +;4360;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;4368;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;4376;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;4384;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;4392;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;4400;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;4408;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;4416;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;4424;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;4432;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;4440;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;4448;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;4456;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;4464;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;4472;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;4480;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;4488;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;4496;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;4504;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;4512;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;4520;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;4528;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;4536;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;4544;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;4552;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;4560;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4568;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ; +;4576;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;4584;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;4592;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ; +;4600;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;4608;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;4616;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;4624;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;4632;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;4640;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;4648;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;4656;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;4664;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;4672;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;4680;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ; +;4688;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;4696;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;4704;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;4712;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;4720;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;4728;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;4736;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ; +;4744;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;4752;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;4760;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;4768;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;4776;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;4784;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;4792;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;4800;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;4808;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;4816;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;4824;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;4832;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;4840;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ; +;4848;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;4856;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4864;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;4872;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;4880;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;4888;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;4896;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;4904;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ; +;4912;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;4920;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;4928;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;4936;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4944;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;4952;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;4960;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;4968;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;4976;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;4984;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;4992;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;5000;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;5008;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5016;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;5024;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5032;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;5040;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ; +;5048;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;5056;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;5064;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5072;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5080;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;5088;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5096;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;5104;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5112;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5120;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ; +;5128;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;5136;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5144;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5152;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5160;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5168;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5176;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ; +;5184;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;5192;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;5200;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;5208;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5216;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;5224;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ; +;5232;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5240;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;5248;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;5256;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;5264;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;5272;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;5280;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;5288;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5296;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;5304;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ; +;5312;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5320;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;5328;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;5336;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;5344;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ; +;5352;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;5360;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5368;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5376;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ; +;5384;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5392;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ; +;5400;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;5408;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;5416;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;5424;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;5432;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;5440;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;5448;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ; +;5456;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;5464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;5472;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;5480;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;5488;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;5496;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ; +;5504;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5512;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;5520;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;5528;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;5536;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;5544;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;5552;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;5560;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;5568;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5576;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5584;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ; +;5592;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;5600;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;5608;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;5616;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5624;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ; +;5632;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5640;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;5648;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5656;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;5664;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;5672;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;5680;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;5688;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;5696;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;5704;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;5712;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;5720;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;5728;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;5736;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ; +;5744;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;5752;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ; +;5760;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ; +;5768;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;5776;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;5784;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;5792;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;5800;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;5808;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;5816;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;5824;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;5832;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;5840;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;5848;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;5856;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;5864;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;5872;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;5880;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;5888;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;5896;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;5904;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5912;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;5920;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;5928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;5936;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;5944;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;5952;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;5960;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;5968;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;5976;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;5984;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;5992;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;6000;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6008;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;6016;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;6024;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;6032;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ; +;6040;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;6048;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;6056;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;6064;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ; +;6072;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;6080;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;6088;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;6096;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;6104;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;6112;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;6120;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;6128;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;6136;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;6144;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;6152;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;6160;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;6168;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;6176;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;6184;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;6192;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;6200;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;6208;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ; +;6216;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;6224;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;6232;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;6240;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;6248;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;6256;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ; +;6264;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;6272;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ; +;6280;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ; +;6288;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ; +;6296;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;6304;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;6312;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;6320;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;6328;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;6336;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;6344;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ; +;6352;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;6360;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;6368;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;6376;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;6384;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;6392;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;6400;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;6408;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;6416;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ; +;6424;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ; +;6432;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ; +;6440;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;6448;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;6456;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;6464;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;6472;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ; +;6480;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;6488;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;6496;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;6504;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;6512;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;6520;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;6528;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;6536;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6544;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;6552;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;6560;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;6568;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;6576;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;6584;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;6592;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;6600;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;6608;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;6616;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;6624;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;6632;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;6640;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;6648;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;6656;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;6664;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;6672;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;6680;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;6688;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;6696;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;6704;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ; +;6712;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;6720;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;6728;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(10010000) (220) (144) (90) ; +;6736;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ; +;6744;(10010000) (220) (144) (90) ;(10010000) (220) (144) (90) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;6752;(01000000) (100) (64) (40) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;6760;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;6768;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;6776;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ; +;6784;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6792;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;6800;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;6808;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;6816;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ; +;6824;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;6832;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ; +;6840;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ; +;6848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;6856;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;6864;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;6872;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;6880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6888;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6896;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ; +;6904;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6912;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;6920;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;6928;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;6936;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ; +;6944;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;6952;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;6960;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;6968;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ; +;6976;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ; +;6984;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;6992;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;7000;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ; +;7008;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7016;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;7024;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;7032;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;7040;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;7048;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;7056;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;7064;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;7072;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;7080;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;7088;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;7096;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ; +;7104;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;7112;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;7120;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;7128;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;7136;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;7144;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;7152;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;7160;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;7168;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;7176;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;7184;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;7192;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;7200;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;7208;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;7216;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;7224;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;7232;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;7240;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;7248;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;7256;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;7264;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;7272;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;7280;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;7288;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;7296;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;7304;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;7312;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;7320;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;7328;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;7336;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ; +;7344;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;7352;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;7360;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;7368;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;7376;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;7384;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;7392;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;7400;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;7408;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;7416;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ; +;7424;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;7432;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;7440;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;7448;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;7456;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;7464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7472;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;7480;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;7488;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;7496;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;7504;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;7512;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;7520;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;7528;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;7536;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;7544;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ; +;7552;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;7560;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;7568;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;7576;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;7584;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;7592;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;7600;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;7608;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;7616;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;7624;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ; +;7632;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ; +;7640;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;7648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ; +;7656;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;7664;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;7672;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;7680;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;7688;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ; +;7696;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;7704;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;7712;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;7720;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;7728;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;7736;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;7744;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ; +;7752;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;7760;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;7768;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;7776;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;7784;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;7792;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ; +;7800;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;7808;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ; +;7816;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;7824;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;7832;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;7840;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;7848;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ; +;7856;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;7864;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;7872;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;7880;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;7888;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;7896;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ; +;7904;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;7912;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ; +;7920;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;7928;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;7936;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;7944;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;7952;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;7960;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;7968;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;7976;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;7984;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;7992;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;8000;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;8008;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ; +;8016;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;8024;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;8032;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;8040;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;8048;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;8056;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;8064;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;8072;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;8080;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8088;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;8096;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;8104;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;8112;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;8120;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;8128;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;8136;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;8144;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;8152;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;8160;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;8168;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;8176;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;8184;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;8192;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;8200;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ; +;8208;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;8216;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;8224;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;8232;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;8240;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;8248;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;8256;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;8264;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;8272;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;8280;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;8288;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;8296;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;8304;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;8312;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;8320;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ; +;8328;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;8336;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;8344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;8352;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(10110000) (260) (176) (B0) ; +;8360;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ; +;8368;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;8376;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;8384;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;8392;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;8400;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;8408;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;8416;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;8424;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;8432;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;8440;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;8448;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;8456;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;8464;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;8472;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;8480;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;8488;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ; +;8496;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;8504;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;8512;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;8520;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;8528;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;8536;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;8544;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ; +;8552;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10000000) (200) (128) (80) ; +;8560;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;8568;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;8576;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;8584;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;8592;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;8600;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;8608;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;8616;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;8624;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;8632;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;8640;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;8648;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;8656;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;8664;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ; +;8672;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;8680;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;8688;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ; +;8696;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;8704;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;8712;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ; +;8720;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;8728;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;8736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8744;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;8752;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;8760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;8768;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ; +;8776;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;8784;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ; +;8792;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(10010000) (220) (144) (90) ; +;8800;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;8808;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(10010000) (220) (144) (90) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ; +;8816;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ; +;8824;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;8832;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ; +;8840;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;8848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;8856;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8864;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ; +;8872;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;8880;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ; +;8888;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;8896;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;8904;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;8912;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;8920;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;8928;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;8936;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;8944;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;8952;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;8960;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;8968;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;8976;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;8984;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;8992;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;9000;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;9008;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9016;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ; +;9024;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;9032;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;9040;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;9048;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9056;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9064;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;9072;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;9080;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;9088;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;9096;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;9104;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;9112;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9120;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9128;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9136;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;9144;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;9152;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;9160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9168;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;9176;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;9184;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9192;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;9200;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;9208;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;9216;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9224;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;9232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;9240;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;9248;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;9256;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;9264;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;9272;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9280;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;9288;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;9296;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;9304;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;9312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;9320;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ; +;9328;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;9336;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;9344;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9352;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;9360;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;9368;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9376;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;9384;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;9392;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;9400;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ; +;9408;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(01000000) (100) (64) (40) ; +;9416;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ; +;9424;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;9432;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;9440;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ; +;9448;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;9456;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;9464;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ; +;9472;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ; +;9480;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;9488;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;9496;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;9504;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;9512;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;9520;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;9528;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ; +;9536;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ; +;9544;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ; +;9552;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;9560;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;9568;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;9576;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;9584;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;9592;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9600;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;9608;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;9616;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;9624;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;9632;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(10000000) (200) (128) (80) ;(10100000) (240) (160) (A0) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;9640;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;9648;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9656;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;9664;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;9672;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;9680;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;9688;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;9696;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;9704;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;9712;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;9720;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;9728;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;9736;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9744;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;9752;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ; +;9760;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;9768;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;9776;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;9784;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;9792;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;9800;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;9808;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;9816;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;9832;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;9840;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;9848;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;9856;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;9864;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;9872;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;9880;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;9888;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ; +;9896;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;9904;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;9912;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;9920;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;9928;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;9936;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;9944;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;9952;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;9960;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ; +;9968;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;9976;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;9984;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ; +;9992;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;10000;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;10008;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;10016;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ; +;10024;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;10032;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ; +;10040;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;10048;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;10056;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;10064;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;10072;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;10080;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ; +;10088;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;10096;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;10104;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;10112;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;10120;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;10128;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;10136;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;10144;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;10152;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;10160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;10176;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ; +;10184;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;10192;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10200;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10208;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;10216;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ; +;10224;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;10232;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ; +;10240;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;10248;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;10256;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;10264;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;10272;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;10280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;10288;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;10296;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ; +;10304;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;10312;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10320;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;10328;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10336;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;10344;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ; +;10352;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10360;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;10368;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ; +;10376;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;10384;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10392;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;10400;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;10408;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;10416;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;10424;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;10432;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;10440;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;10448;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;10456;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ; +;10464;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;10472;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;10480;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ; +;10488;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;10496;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10504;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ; +;10512;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10520;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;10528;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;10536;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;10544;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;10552;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ; +;10560;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;10568;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;10576;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;10584;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;10592;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;10600;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;10608;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;10616;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;10624;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;10632;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;10640;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ; +;10648;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10656;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;10664;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10672;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;10680;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ; +;10688;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;10696;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;10704;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;10712;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;10720;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;10728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;10736;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;10744;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;10752;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;10760;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ; +;10768;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;10776;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10784;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;10792;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;10800;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;10808;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10816;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;10824;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;10832;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;10840;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ; +;10848;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;10856;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ; +;10864;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10872;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ; +;10880;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;10888;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;10896;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;10904;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;10912;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;10920;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;10928;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;10936;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;10944;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;10952;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ; +;10960;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;10968;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ; +;10976;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;10984;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;10992;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;11000;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;11008;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;11016;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;11024;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;11032;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;11040;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;11048;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;11056;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;11064;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;11072;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;11080;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;11088;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;11096;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11104;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;11112;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;11120;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;11128;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ; +;11136;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;11144;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;11152;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;11160;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;11168;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;11176;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;11184;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;11192;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;11200;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;11208;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;11216;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;11224;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;11232;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;11240;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;11248;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;11256;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ; +;11264;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;11272;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;11280;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;11288;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;11296;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;11304;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;11312;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;11320;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;11328;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;11336;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;11344;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;11352;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;11360;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11368;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;11376;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;11384;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;11392;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;11400;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;11408;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ; +;11416;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;11424;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;11432;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ; +;11440;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;11448;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;11456;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;11464;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;11472;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;11480;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;11488;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;11496;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;11504;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;11512;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;11520;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;11528;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ; +;11536;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;11544;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;11552;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ; +;11560;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ; +;11568;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;11576;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;11584;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;11592;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;11600;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ; +;11608;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;11616;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;11624;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;11632;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;11640;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;11648;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;11656;(10000000) (200) (128) (80) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;11664;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ;(01110000) (160) (112) (70) ; +;11672;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;11680;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;11688;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;11696;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ; +;11704;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;11712;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ; +;11720;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;11728;(10010000) (220) (144) (90) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;11736;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;11744;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;11752;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;11760;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;11768;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;11776;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;11784;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;11792;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;11800;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ; +;11808;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;11816;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ; +;11824;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;11832;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;11840;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;11848;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ; +;11856;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ; +;11864;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;11872;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;11880;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11100000) (340) (224) (E0) ; +;11888;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ; +;11896;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;11904;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;11912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;11920;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;11928;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ; +;11936;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;11944;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;11952;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;11960;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;11968;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10110000) (260) (176) (B0) ; +;11976;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;11984;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ; +;11992;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ; +;12000;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;12008;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;12016;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;12024;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ; +;12032;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;12040;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;12048;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ; +;12056;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;12064;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;12072;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;12080;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;12088;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;12096;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;12104;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;12112;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;12120;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ; +;12128;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;12136;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12144;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;12152;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +;12160;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;12168;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;12176;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ; +;12184;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;12192;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;12200;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;12208;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01110000) (160) (112) (70) ; +;12216;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ; +;12224;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ; +;12232;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;12240;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;12248;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;12256;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;12264;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;12272;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;12280;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;12288;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;12296;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;12304;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;12312;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;12320;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ; +;12328;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;12336;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;12344;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;12352;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ; +;12360;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ; +;12368;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ; +;12376;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;12384;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ; +;12392;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;12400;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;12408;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ; +;12416;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ; +;12424;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;12432;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;12440;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;12448;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;12456;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;12464;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;12472;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;12480;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;12488;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;12496;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;12504;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ; +;12512;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;12520;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;12528;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ; +;12536;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;12544;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;12552;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ; +;12560;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;12568;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;12576;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;12584;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;12592;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ; +;12600;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;12608;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;12616;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ; +;12624;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ; +;12632;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ; +;12640;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;12648;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;12656;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;12664;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ; +;12672;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;12680;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;12688;(10000000) (200) (128) (80) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;12696;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;12704;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ; +;12712;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;12720;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;12728;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;12736;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;12744;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;12752;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;12760;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ; +;12768;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;12776;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ; +;12784;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;12792;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;12800;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;12808;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;12816;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;12824;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;12832;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;12840;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;12848;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;12856;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;12864;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;12872;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;12880;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(10000000) (200) (128) (80) ; +;12888;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;12896;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;12904;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ; +;12912;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;12920;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;12928;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;12936;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ; +;12944;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;12952;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;12960;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;12968;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;12976;(10000000) (200) (128) (80) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;12984;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;12992;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ; +;13000;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ; +;13008;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(01000000) (100) (64) (40) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ; +;13016;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;13024;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;13032;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;13040;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;13048;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;13056;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ; +;13064;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ; +;13072;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ; +;13080;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;13088;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ; +;13096;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ; +;13104;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;13112;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;13120;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ; +;13128;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ; +;13136;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ; +;13144;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00110000) (60) (48) (30) ; +;13152;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ; +;13160;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;13168;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13176;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;13184;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;13192;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;13200;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;13208;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ; +;13216;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;13224;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ; +;13232;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ; +;13240;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;13248;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ; +;13256;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;13264;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;13272;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;13280;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;13288;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ; +;13296;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ; +;13304;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;13312;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;13320;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ; +;13328;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;13336;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;13344;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;13352;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;13360;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;13368;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ; +;13376;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;13384;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;13392;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;13400;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ; +;13408;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;13416;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;13424;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;13432;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;13440;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;13448;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;13456;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;13464;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ; +;13472;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;13480;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;13488;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;13496;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;13504;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;13512;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;13520;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(10000000) (200) (128) (80) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ; +;13528;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(10000000) (200) (128) (80) ; +;13536;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;13544;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;13552;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;13560;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;13568;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;13576;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;13584;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ; +;13592;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;13600;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ; +;13608;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;13616;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;13624;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;13632;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;13640;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ; +;13648;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;13656;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;13664;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ; +;13672;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;13680;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;13688;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;13696;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ; +;13704;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ; +;13712;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;13720;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;13728;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;13736;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;13744;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ; +;13752;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ; +;13760;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;13768;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;13776;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;13784;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;13792;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10010000) (220) (144) (90) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;13800;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;13808;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;13816;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;13824;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;13832;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;13840;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ; +;13848;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;13856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;13864;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;13872;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;13880;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;13888;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ; +;13896;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ; +;13904;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;13912;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;13920;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ; +;13928;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;13936;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;13944;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ; +;13952;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(01010000) (120) (80) (50) ; +;13960;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ; +;13968;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ; +;13976;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ; +;13984;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ; +;13992;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;14000;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;14008;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14016;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;14024;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;14032;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ; +;14040;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(10010000) (220) (144) (90) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ; +;14048;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ; +;14056;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ; +;14064;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;14072;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14080;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ; +;14088;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;14096;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14104;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ; +;14112;(00110000) (60) (48) (30) ;(10000000) (200) (128) (80) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;14120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ; +;14128;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;14136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;14144;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;14152;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;14160;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ; +;14168;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ; +;14176;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(10010000) (220) (144) (90) ;(10100000) (240) (160) (A0) ; +;14184;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ; +;14192;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ; +;14200;(01110000) (160) (112) (70) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ; +;14208;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14216;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;14224;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ; +;14232;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;14240;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;14248;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;14256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;14264;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;14272;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ; +;14280;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ; +;14288;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ; +;14296;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;14304;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ; +;14312;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;14320;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14328;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14336;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ; +;14344;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(11110000) (360) (240) (F0) ; +;14352;(10010000) (220) (144) (90) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ; +;14360;(01100000) (140) (96) (60) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ; +;14368;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ; +;14376;(01100000) (140) (96) (60) ;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ;(01100000) (140) (96) (60) ;(10100000) (240) (160) (A0) ;(10110000) (260) (176) (B0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14384;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;14392;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;14400;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;14408;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ; +;14416;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;14424;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;14432;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;14440;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;14448;(00000000) (0) (0) (00) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ; +;14456;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ; +;14464;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11010000) (320) (208) (D0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14472;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;14480;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;14488;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;14496;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14504;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14512;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;14520;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;14528;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;14536;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ; +;14544;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(10110000) (260) (176) (B0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;14552;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;14560;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ; +;14568;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;14576;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ; +;14584;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;14592;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(10000000) (200) (128) (80) ; +;14600;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ; +;14608;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;14616;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ; +;14624;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;14632;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14640;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ; +;14648;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ; +;14656;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01100000) (140) (96) (60) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;14664;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;14672;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ; +;14680;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;14688;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;14696;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ; +;14704;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(10000000) (200) (128) (80) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ; +;14712;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ; +;14720;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;14728;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ; +;14736;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ; +;14744;(01110000) (160) (112) (70) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ; +;14752;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;14760;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14768;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14776;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ; +;14784;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ; +;14792;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;14800;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ; +;14808;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;14816;(00010000) (20) (16) (10) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;14824;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;14832;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(01110000) (160) (112) (70) ; +;14840;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;14848;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;14856;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ; +;14864;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;14872;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ; +;14880;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ; +;14888;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;14896;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(10110000) (260) (176) (B0) ; +;14904;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ; +;14912;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ; +;14920;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ; +;14928;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;14936;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ; +;14944;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ; +;14952;(10100000) (240) (160) (A0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14960;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;14968;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ; +;14976;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(11010000) (320) (208) (D0) ;(00000000) (0) (0) (00) ; +;14984;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;14992;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;15000;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(10010000) (220) (144) (90) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;15008;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15016;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(10100000) (240) (160) (A0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15024;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;15032;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;15040;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;15048;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;15056;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;15064;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ; +;15072;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ; +;15080;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ; +;15088;(00010000) (20) (16) (10) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(10100000) (240) (160) (A0) ; +;15096;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;15104;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;15112;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(01100000) (140) (96) (60) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ; +;15120;(10100000) (240) (160) (A0) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;15128;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;15136;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;15144;(10010000) (220) (144) (90) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11100000) (340) (224) (E0) ; +;15152;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;15160;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;15168;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ; +;15176;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ; +;15184;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;15192;(11010000) (320) (208) (D0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ; +;15200;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ; +;15208;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ; +;15216;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ; +;15224;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(10110000) (260) (176) (B0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ; +;15232;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ; +;15240;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(10100000) (240) (160) (A0) ;(11000000) (300) (192) (C0) ; +;15248;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ; +;15256;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ; +;15264;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ; +;15272;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;15280;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(11000000) (300) (192) (C0) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;15288;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ; +;15296;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ; +;15304;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ; +;15312;(01000000) (100) (64) (40) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;15320;(00110000) (60) (48) (30) ;(10110000) (260) (176) (B0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;15328;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ; +;15336;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ; +;15344;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;15352;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11010000) (320) (208) (D0) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(11110000) (360) (240) (F0) ; +;15360;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ; +;15368;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ; +;15376;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;15384;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ; +;15392;(00110000) (60) (48) (30) ;(11010000) (320) (208) (D0) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;15400;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ; +;15408;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(10100000) (240) (160) (A0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;15416;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; +;15424;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ; +;15432;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00100000) (40) (32) (20) ;(11100000) (340) (224) (E0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ; +;15440;(11000000) (300) (192) (C0) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ;(11000000) (300) (192) (C0) ;(11100000) (340) (224) (E0) ; +;15448;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(11100000) (340) (224) (E0) ; +;15456;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(11010000) (320) (208) (D0) ;(11100000) (340) (224) (E0) ; +;15464;(01000000) (100) (64) (40) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ; +;15472;(11100000) (340) (224) (E0) ;(01000000) (100) (64) (40) ;(10100000) (240) (160) (A0) ;(01010000) (120) (80) (50) ;(11000000) (300) (192) (C0) ;(10000000) (200) (128) (80) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; +;15480;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;15488;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01010000) (120) (80) (50) ;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ; +;15496;(10010000) (220) (144) (90) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ; +;15504;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(11010000) (320) (208) (D0) ;(01110000) (160) (112) (70) ; +;15512;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(10000000) (200) (128) (80) ;(00110000) (60) (48) (30) ;(11000000) (300) (192) (C0) ; +;15520;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ; +;15528;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ; +;15536;(11010000) (320) (208) (D0) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ; +;15544;(10010000) (220) (144) (90) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(01000000) (100) (64) (40) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ; +;15552;(11000000) (300) (192) (C0) ;(00110000) (60) (48) (30) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ; +;15560;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ; +;15568;(01110000) (160) (112) (70) ;(10000000) (200) (128) (80) ;(11010000) (320) (208) (D0) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(10110000) (260) (176) (B0) ; +;15576;(01110000) (160) (112) (70) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(11000000) (300) (192) (C0) ;(00010000) (20) (16) (10) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15584;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ;(00100000) (40) (32) (20) ; +;15592;(00000000) (0) (0) (00) ;(01010000) (120) (80) (50) ;(01110000) (160) (112) (70) ;(01110000) (160) (112) (70) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;15600;(11110000) (360) (240) (F0) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(11110000) (360) (240) (F0) ;(11000000) (300) (192) (C0) ;(10110000) (260) (176) (B0) ;(00010000) (20) (16) (10) ;(11110000) (360) (240) (F0) ; +;15608;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11100000) (340) (224) (E0) ;(11110000) (360) (240) (F0) ;(11110000) (360) (240) (F0) ;(11100000) (340) (224) (E0) ;(11000000) (300) (192) (C0) ; ;15616;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; ;15624;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;15632;(00000000) (0) (0) (00) ;(00100100) (44) (36) (24) ;(00100100) (44) (36) (24) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;15640;(00000000) (0) (0) (00) ;(00100100) (44) (36) (24) ;(01111110) (176) (126) (7E) ;(00100100) (44) (36) (24) ;(00100100) (44) (36) (24) ;(01111110) (176) (126) (7E) ;(00100100) (44) (36) (24) ;(00000000) (0) (0) (00) ; -;15648;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00101000) (50) (40) (28) ;(00111110) (76) (62) (3E) ;(00001010) (12) (10) (0A) ;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ; -;15656;(00000000) (0) (0) (00) ;(01100010) (142) (98) (62) ;(01100100) (144) (100) (64) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00100110) (46) (38) (26) ;(01000110) (106) (70) (46) ;(00000000) (0) (0) (00) ; -;15664;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00101010) (52) (42) (2A) ;(01000100) (104) (68) (44) ;(00111010) (72) (58) (3A) ;(00000000) (0) (0) (00) ; -;15672;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;15680;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ; +;15632;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15640;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;15648;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15656;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15664;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15672;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15680;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; ;15688;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; -;15696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010100) (24) (20) (14) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(00010100) (24) (20) (14) ;(00000000) (0) (0) (00) ; -;15704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ; -;15712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ; -;15720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;15728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00000000) (0) (0) (00) ; -;15736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; -;15744;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000110) (106) (70) (46) ;(01001010) (112) (74) (4A) ;(01010010) (122) (82) (52) ;(01100010) (142) (98) (62) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15752;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(00101000) (50) (40) (28) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ; -;15760;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(00000010) (2) (2) (02) ;(00111100) (74) (60) (3C) ;(01000000) (100) (64) (40) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;15768;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(00001100) (14) (12) (0C) ;(00000010) (2) (2) (02) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15776;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00011000) (30) (24) (18) ;(00101000) (50) (40) (28) ;(01001000) (110) (72) (48) ;(01111110) (176) (126) (7E) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ; -;15784;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(01000000) (100) (64) (40) ;(01111100) (174) (124) (7C) ;(00000010) (2) (2) (02) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15792;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000000) (100) (64) (40) ;(01111100) (174) (124) (7C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15800;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(00000010) (2) (2) (02) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;15808;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15816;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111110) (76) (62) (3E) ;(00000010) (2) (2) (02) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; +;15696;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;15704;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15712;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ; +;15720;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15728;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;15736;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;15744;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01100000) (140) (96) (60) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15752;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15760;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;15768;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15776;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15784;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15792;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15800;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;15808;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15816;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; ;15824;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; ;15832;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ; -;15840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00001000) (10) (8) (08) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ; -;15848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;15856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00001000) (10) (8) (08) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;15864;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ; -;15872;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01001010) (112) (74) (4A) ;(01010110) (126) (86) (56) ;(01011110) (136) (94) (5E) ;(01000000) (100) (64) (40) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15880;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01111110) (176) (126) (7E) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;15888;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(01000010) (102) (66) (42) ;(01111100) (174) (124) (7C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01111100) (174) (124) (7C) ;(00000000) (0) (0) (00) ; -;15896;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15904;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000100) (104) (68) (44) ;(01111000) (170) (120) (78) ;(00000000) (0) (0) (00) ; -;15912;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(01000000) (100) (64) (40) ;(01111100) (174) (124) (7C) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;15920;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(01000000) (100) (64) (40) ;(01111100) (174) (124) (7C) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; -;15928;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000000) (100) (64) (40) ;(01001110) (116) (78) (4E) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15936;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01111110) (176) (126) (7E) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;15944;(00000000) (0) (0) (00) ;(00111110) (76) (62) (3E) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00111110) (76) (62) (3E) ;(00000000) (0) (0) (00) ; -;15952;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ;(00000010) (2) (2) (02) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;15960;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01001000) (110) (72) (48) ;(01110000) (160) (112) (70) ;(01001000) (110) (72) (48) ;(01000100) (104) (68) (44) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;15968;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;15976;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01100110) (146) (102) (66) ;(01011010) (132) (90) (5A) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;15984;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01100010) (142) (98) (62) ;(01010010) (122) (82) (52) ;(01001010) (112) (74) (4A) ;(01000110) (106) (70) (46) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;15992;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16000;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01111100) (174) (124) (7C) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; -;16008;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01010010) (122) (82) (52) ;(01001010) (112) (74) (4A) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16016;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01111100) (174) (124) (7C) ;(01000100) (104) (68) (44) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;16024;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000000) (100) (64) (40) ;(00111100) (74) (60) (3C) ;(00000010) (2) (2) (02) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16032;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;16040;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16048;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00000000) (0) (0) (00) ; -;16056;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01000010) (102) (66) (42) ;(01011010) (132) (90) (5A) ;(00100100) (44) (36) (24) ;(00000000) (0) (0) (00) ; -;16064;(00000000) (0) (0) (00) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(00000000) (0) (0) (00) ; -;16072;(00000000) (0) (0) (00) ;(10000010) (202) (130) (82) ;(01000100) (104) (68) (44) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;16080;(00000000) (0) (0) (00) ;(01111110) (176) (126) (7E) ;(00000100) (4) (4) (04) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;16088;(00000000) (0) (0) (00) ;(00001110) (16) (14) (0E) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ; -;16096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00001000) (10) (8) (08) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ; +;15840;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15848;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15856;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;15864;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;15872;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15880;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15888;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;15896;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15904;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;15912;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;15920;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15928;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15936;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15944;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15952;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;15960;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15968;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;15976;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15984;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;15992;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16000;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16008;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16016;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16024;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16032;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16040;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16048;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16056;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;16064;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16072;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16080;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16088;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16096;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; ;16104;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; -;16112;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(01010100) (124) (84) (54) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;16120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; -;16128;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100010) (42) (34) (22) ;(01111000) (170) (120) (78) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; -;16136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16144;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00111100) (74) (60) (3C) ;(00100010) (42) (34) (22) ;(00100010) (42) (34) (22) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00011100) (34) (28) (1C) ;(00000000) (0) (0) (00) ; -;16160;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000100) (104) (68) (44) ;(01111000) (170) (120) (78) ;(01000000) (100) (64) (40) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; -;16176;(00000000) (0) (0) (00) ;(00001100) (14) (12) (0C) ;(00010000) (20) (16) (10) ;(00011000) (30) (24) (18) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;16184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; -;16192;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; -;16200;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; -;16208;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ; -;16216;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00101000) (50) (40) (28) ;(00100100) (44) (36) (24) ;(00000000) (0) (0) (00) ; -;16224;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00000000) (0) (0) (00) ; -;16232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01101000) (150) (104) (68) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(00000000) (0) (0) (00) ; -;16240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; -;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; -;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01111000) (170) (120) (78) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; -;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00000110) (6) (6) (06) ; -;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; -;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000000) (100) (64) (40) ;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(01111000) (170) (120) (78) ;(00000000) (0) (0) (00) ; -;16288;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00000000) (0) (0) (00) ; -;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; -;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; -;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(00101000) (50) (40) (28) ;(00000000) (0) (0) (00) ; -;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00101000) (50) (40) (28) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; -;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; -;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01111100) (174) (124) (7C) ;(00000000) (0) (0) (00) ; -;16344;(00000000) (0) (0) (00) ;(00001110) (16) (14) (0E) ;(00001000) (10) (8) (08) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ; -;16352;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ; -;16360;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; -;16368;(00000000) (0) (0) (00) ;(00010100) (24) (20) (14) ;(00101000) (50) (40) (28) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16376;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(10011001) (231) (153) (99) ;(10100001) (241) (161) (A1) ;(10100001) (241) (161) (A1) ;(10011001) (231) (153) (99) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ; +;16112;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(01010000) (120) (80) (50) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ; +;16128;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16144;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16160;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16176;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;16192;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16200;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16208;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ; +;16216;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;16224;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01100000) (140) (96) (60) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00000000) (0) (0) (00) ; +;16240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01110000) (160) (112) (70) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16288;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ; +;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(01010000) (120) (80) (50) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00100000) (40) (32) (20) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ; +;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ; +;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16360;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16368;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16376;(00110000) (60) (48) (30) ;(01000000) (100) (64) (40) ;(10010000) (220) (144) (90) ;(10100000) (240) (160) (A0) ;(10100000) (240) (160) (A0) ;(10010000) (220) (144) (90) ;(01000000) (100) (64) (40) ;(00110000) (60) (48) (30) ; +------------------------------------------------+ @@ -8690,128 +10814,130 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci +-----------------------+------------------------+ ; Routing Resource Type ; Usage ; +-----------------------+------------------------+ -; Block interconnects ; 272 / 71,559 ( < 1 % ) ; -; C16 interconnects ; 4 / 2,597 ( < 1 % ) ; -; C4 interconnects ; 129 / 46,848 ( < 1 % ) ; -; Direct links ; 7 / 71,559 ( < 1 % ) ; +; Block interconnects ; 233 / 71,559 ( < 1 % ) ; +; C16 interconnects ; 3 / 2,597 ( < 1 % ) ; +; C4 interconnects ; 99 / 46,848 ( < 1 % ) ; +; Direct links ; 11 / 71,559 ( < 1 % ) ; ; Global clocks ; 1 / 20 ( 5 % ) ; -; Local interconnects ; 39 / 24,624 ( < 1 % ) ; -; R24 interconnects ; 8 / 2,496 ( < 1 % ) ; -; R4 interconnects ; 213 / 62,424 ( < 1 % ) ; +; Local interconnects ; 37 / 24,624 ( < 1 % ) ; +; R24 interconnects ; 6 / 2,496 ( < 1 % ) ; +; R4 interconnects ; 159 / 62,424 ( < 1 % ) ; +-----------------------+------------------------+ ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 5.56) ; Number of LABs (Total = 9) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 5 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 1 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 0.44) ; Number of LABs (Total = 9) ; ++------------------------------------+-----------------------------+ +; 1 Clock ; 4 ; ++------------------------------------+-----------------------------+ + + +---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 4.58) ; Number of LABs (Total = 12) ; -+--------------------------------------------+------------------------------+ -; 1 ; 8 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 1 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 2 ; -+--------------------------------------------+------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 9.78) ; Number of LABs (Total = 9) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 5 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 1 ; +; 25 ; 0 ; +; 26 ; 1 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 1 ; ++---------------------------------------------+-----------------------------+ -+-------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 0.33) ; Number of LABs (Total = 12) ; -+------------------------------------+------------------------------+ -; 1 Clock ; 4 ; -+------------------------------------+------------------------------+ ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 3.44) ; Number of LABs (Total = 9) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 6 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; ++-------------------------------------------------+-----------------------------+ -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.75) ; Number of LABs (Total = 12) ; -+---------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 8 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -; 17 ; 0 ; -; 18 ; 0 ; -; 19 ; 0 ; -; 20 ; 0 ; -; 21 ; 0 ; -; 22 ; 0 ; -; 23 ; 1 ; -; 24 ; 0 ; -; 25 ; 0 ; -; 26 ; 0 ; -; 27 ; 0 ; -; 28 ; 1 ; -; 29 ; 0 ; -; 30 ; 1 ; -+---------------------------------------------+------------------------------+ - - -+--------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 2.75) ; Number of LABs (Total = 12) ; -+-------------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 9 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 2 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 1 ; -+-------------------------------------------------+------------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 3.50) ; Number of LABs (Total = 12) ; -+---------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 9 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 1 ; -+---------------------------------------------+------------------------------+ ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.33) ; Number of LABs (Total = 9) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 3 ; +; 3 ; 4 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; ++---------------------------------------------+-----------------------------+ +------------------------------------------+ @@ -9562,26 +11688,6 @@ IO_000042 : Inapplicable +---------------------------+--------+ -+--------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Summary ; -+--------------------------------------------------------------------------------+ -+--------------------------------------------------------------------------------+ - -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. - - -+--------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+--------------------------------------------------------------------------------+ -Source Register : address[0] -Destination Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Delay Added in ns : 0.035 -+--------------------------------------------------------------------------------+ - -Note: This table only shows the top 1 path(s) that have the largest delay added for hold. - - +-----------------+ ; Fitter Messages ; +-----------------+ @@ -9590,6 +11696,11 @@ Info (119006): Selected device EP4CE22F17C6 for design "spectrum" Info (21077): Core supply voltage is 1.2V Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C +Info (119042): Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled + Info (119043): Atom "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled + Info (119043): Atom "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled + Info (119043): Atom "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled + Info (119043): Atom "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices @@ -9768,11 +11879,11 @@ Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 + Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.20 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation @@ -9783,10 +11894,10 @@ Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings - Info: Peak virtual memory: 595 megabytes - Info: Processing ended: Wed Mar 30 13:12:20 2022 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Peak virtual memory: 594 megabytes + Info: Processing ended: Wed Mar 30 13:47:16 2022 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 +----------------------------+ diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index a90c61d..c441fa4 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Wed Mar 30 13:12:20 2022 +Fitter Status : Successful - Wed Mar 30 13:47:16 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 55 / 22,320 ( < 1 % ) - Total combinational functions : 52 / 22,320 ( < 1 % ) +Total logic elements : 50 / 22,320 ( < 1 % ) + Total combinational functions : 48 / 22,320 ( < 1 % ) Dedicated logic registers : 38 / 22,320 ( < 1 % ) Total registers : 38 Total pins : 9 / 154 ( 6 % ) Total virtual pins : 0 -Total memory bits : 131,072 / 608,256 ( 22 % ) +Total memory bits : 98,304 / 608,256 ( 16 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Total PLLs : 0 / 4 ( 0 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index 5937fc4..ebddc8e 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Wed Mar 30 13:12:28 2022 +Wed Mar 30 13:47:24 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,20 +40,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Wed Mar 30 13:12:28 2022 ; +; Flow Status ; Successful - Wed Mar 30 13:47:24 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 55 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 52 / 22,320 ( < 1 % ) ; +; Total logic elements ; 50 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 48 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; ; Total registers ; 38 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 131,072 / 608,256 ( 22 % ) ; +; Total memory bits ; 98,304 / 608,256 ( 16 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/30/2022 13:12:12 ; +; Start date & time ; 03/30/2022 13:47:07 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164863513225804 +Value : 0.164863722728310 Default Value : -- Entity Name : -- Section Id : -- @@ -97,6 +97,18 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_NAME +Value : RAM: 2-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : IP_TOOL_VERSION Value : 13.1 Default Value : -- @@ -121,6 +133,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : MISC_FILE +Value : ram16_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Value : 1.2V Default Value : -- @@ -158,40 +176,40 @@ Section Id : -- ; Flow Elapsed Time ; +--------------------------------------------------------------------------------+ Module Name : Analysis & Synthesis -Elapsed Time : 00:00:02 +Elapsed Time : 00:00:01 Average Processors Used : 1.0 -Peak Virtual Memory : 381 MB -Total CPU Time (on all processors) : 00:00:01 +Peak Virtual Memory : 384 MB +Total CPU Time (on all processors) : 00:00:02 Module Name : Fitter -Elapsed Time : 00:00:06 +Elapsed Time : 00:00:07 Average Processors Used : 1.0 -Peak Virtual Memory : 595 MB +Peak Virtual Memory : 594 MB Total CPU Time (on all processors) : 00:00:06 Module Name : Assembler -Elapsed Time : 00:00:02 +Elapsed Time : 00:00:01 Average Processors Used : 1.0 -Peak Virtual Memory : 385 MB +Peak Virtual Memory : 375 MB Total CPU Time (on all processors) : 00:00:01 Module Name : TimeQuest Timing Analyzer Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 407 MB +Peak Virtual Memory : 419 MB Total CPU Time (on all processors) : 00:00:02 Module Name : EDA Netlist Writer -Elapsed Time : 00:00:01 +Elapsed Time : 00:00:00 Average Processors Used : 1.0 -Peak Virtual Memory : 331 MB +Peak Virtual Memory : 339 MB Total CPU Time (on all processors) : 00:00:01 Module Name : Total -Elapsed Time : 00:00:13 +Elapsed Time : 00:00:11 Average Processors Used : -- Peak Virtual Memory : -- -Total CPU Time (on all processors) : 00:00:11 +Total CPU Time (on all processors) : 00:00:12 +--------------------------------------------------------------------------------+ diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 29a146b..da050ee 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index c1ced8f..fadd9c0 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Wed Mar 30 13:12:13 2022 +Wed Mar 30 13:47:09 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -15,12 +15,18 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 7. Analysis & Synthesis Resource Utilization by Entity 8. Analysis & Synthesis RAM Summary 9. Analysis & Synthesis IP Cores Summary - 10. General Register Statistics - 11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated - 12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component - 13. altsyncram Parameter Settings by Entity Instance - 14. Elapsed Time Per Partition - 15. Analysis & Synthesis Messages + 10. Registers Removed During Synthesis + 11. Removed Registers Triggering Further Register Optimizations + 12. General Register Statistics + 13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated + 14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated + 15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component + 16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component + 17. altsyncram Parameter Settings by Entity Instance + 18. Port Connectivity Checks: "ram16:ram0" + 19. Port Connectivity Checks: "rom0:rom" + 20. Elapsed Time Per Partition + 21. Analysis & Synthesis Messages @@ -46,18 +52,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ; +; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 54 ; -; Total combinational functions ; 52 ; +; Total logic elements ; 50 ; +; Total combinational functions ; 48 ; ; Dedicated logic registers ; 38 ; ; Total registers ; 38 ; ; Total pins ; 9 ; ; Total virtual pins ; 0 ; -; Total memory bits ; 131,072 ; +; Total memory bits ; 98,304 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+--------------------------------------------+ @@ -405,12 +411,24 @@ File Type : User Verilog HDL File File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v Library : +File Name with User-Entered Path : led_patterns.mif +Used in Netlist : yes +File Type : User Memory Initialization File +File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif +Library : + File Name with User-Entered Path : rom0.v Used in Netlist : yes File Type : User Wizard-Generated File File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v Library : +File Name with User-Entered Path : ram16.v +Used in Netlist : yes +File Type : User Wizard-Generated File +File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v +Library : + File Name with User-Entered Path : altsyncram.tdf Used in Netlist : yes File Type : Megafunction @@ -488,6 +506,18 @@ Used in Netlist : yes File Type : Auto-Generated Megafunction File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf Library : + +File Name with User-Entered Path : db/altsyncram_bui2.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf +Library : + +File Name with User-Entered Path : db/decode_jsa.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf +Library : +--------------------------------------------------------------------------------+ @@ -497,16 +527,16 @@ Library : +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ -; Estimated Total logic elements ; 54 ; +; Estimated Total logic elements ; 50 ; ; ; ; -; Total combinational functions ; 52 ; +; Total combinational functions ; 48 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 10 ; -; -- <=2 input functions ; 34 ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 35 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 20 ; +; -- normal mode ; 16 ; ; -- arithmetic mode ; 32 ; ; ; ; ; Total registers ; 38 ; @@ -514,12 +544,12 @@ Library : ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 9 ; -; Total memory bits ; 131072 ; +; Total memory bits ; 98304 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 54 ; -; Total fan-out ; 473 ; -; Average fan-out ; 3.81 ; +; Maximum fan-out ; 50 ; +; Total fan-out ; 401 ; +; Average fan-out ; 3.46 ; +---------------------------------------------+----------------+ @@ -527,9 +557,9 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 52 (44) +LC Combinationals : 48 (44) LC Registers : 38 (36) -Memory Bits : 131072 +Memory Bits : 98304 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -538,10 +568,46 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work +Compilation Hierarchy Node : |ram16:ram0| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 32768 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram16:ram0 +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 32768 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_bui2:auto_generated| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 32768 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated +Library Name : work + Compilation Hierarchy Node : |rom0:rom| -LC Combinationals : 8 (0) +LC Combinationals : 4 (0) LC Registers : 2 (0) -Memory Bits : 131072 +Memory Bits : 65536 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -551,9 +617,9 @@ Full Hierarchy Name : |spectrum|rom0:rom Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 8 (0) +LC Combinationals : 4 (0) LC Registers : 2 (0) -Memory Bits : 131072 +Memory Bits : 65536 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -563,9 +629,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| -LC Combinationals : 8 (0) +LC Combinationals : 4 (0) LC Registers : 2 (2) -Memory Bits : 131072 +Memory Bits : 65536 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -575,7 +641,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |mux_3nb:mux2| -LC Combinationals : 8 (8) +LC Combinationals : 4 (4) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -593,6 +659,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------+ +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : True Dual Port +Port A Depth : 16384 +Port A Width : 8 +Port B Depth : 16384 +Port B Width : 8 +Size : 131072 +MIF : led_patterns.mif + Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Type : AUTO Mode : ROM @@ -609,6 +685,14 @@ MIF : ./rom/gw03.hex +--------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------------------------------------------------------------------------------+ +Vendor : Altera +IP Core Name : RAM: 2-PORT +Version : 13.1 +Release Date : N/A +License Type : N/A +Entity Instance : |spectrum|ram16:ram0 +IP Include File : /home/benny/work/fpga/projects/ram16.v + Vendor : Altera IP Core Name : ROM: 1-PORT Version : 13.1 @@ -620,6 +704,42 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++------------------------------------------------------------------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++------------------------------------------------------------------------------------------------+----------------------------------------+ +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ; +; address[0] ; Merged with A[0] ; +; address[1] ; Merged with A[1] ; +; address[2] ; Merged with A[2] ; +; address[3] ; Merged with A[3] ; +; address[4] ; Merged with A[4] ; +; address[5] ; Merged with A[5] ; +; address[6] ; Merged with A[6] ; +; address[7] ; Merged with A[7] ; +; address[8] ; Merged with A[8] ; +; address[9] ; Merged with A[9] ; +; address[10] ; Merged with A[10] ; +; address[11] ; Merged with A[11] ; +; address[12] ; Merged with A[12] ; +; address[13] ; Merged with A[13] ; +; A[14,15] ; Lost fanout ; +; Total Number of Removed Registers = 18 ; ; ++------------------------------------------------------------------------------------------------+----------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++--------------------------------------------------------------------------------+ +Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] +Reason for Removal : Stuck at GNDdue to stuck port data_in +Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ++--------------------------------------------------------------------------------+ + + + +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ @@ -646,6 +766,17 @@ To : - ++--------------------------------------------------------------------------------+ +; Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated ; ++--------------------------------------------------------------------------------+ +Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS +Value : NORMAL_COMPILATION +From : - +To : - ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; +--------------------------------------------------------------------------------+ @@ -861,24 +992,312 @@ Type : Untyped Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". -+--------------------------------------------------------------------------------------+ -; altsyncram Parameter Settings by Entity Instance ; -+-------------------------------------------+------------------------------------------+ -; Name ; Value ; -+-------------------------------------------+------------------------------------------+ -; Number of entity instances ; 1 ; -; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; ROM ; -; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 16384 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -+-------------------------------------------+------------------------------------------+ ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component ; ++--------------------------------------------------------------------------------+ +Parameter Name : BYTE_SIZE_BLOCK +Value : 8 +Type : Untyped + +Parameter Name : AUTO_CARRY_CHAINS +Value : ON +Type : AUTO_CARRY + +Parameter Name : IGNORE_CARRY_BUFFERS +Value : OFF +Type : IGNORE_CARRY + +Parameter Name : AUTO_CASCADE_CHAINS +Value : ON +Type : AUTO_CASCADE + +Parameter Name : IGNORE_CASCADE_BUFFERS +Value : OFF +Type : IGNORE_CASCADE + +Parameter Name : WIDTH_BYTEENA +Value : 1 +Type : Untyped + +Parameter Name : OPERATION_MODE +Value : BIDIR_DUAL_PORT +Type : Untyped + +Parameter Name : WIDTH_A +Value : 8 +Type : Signed Integer + +Parameter Name : WIDTHAD_A +Value : 14 +Type : Signed Integer + +Parameter Name : NUMWORDS_A +Value : 16384 +Type : Signed Integer + +Parameter Name : OUTDATA_REG_A +Value : CLOCK0 +Type : Untyped + +Parameter Name : ADDRESS_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : INDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_B +Value : 8 +Type : Signed Integer + +Parameter Name : WIDTHAD_B +Value : 14 +Type : Signed Integer + +Parameter Name : NUMWORDS_B +Value : 16384 +Type : Signed Integer + +Parameter Name : INDATA_REG_B +Value : CLOCK0 +Type : Untyped + +Parameter Name : WRCONTROL_WRADDRESS_REG_B +Value : CLOCK0 +Type : Untyped + +Parameter Name : RDCONTROL_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : ADDRESS_REG_B +Value : CLOCK0 +Type : Untyped + +Parameter Name : OUTDATA_REG_B +Value : CLOCK0 +Type : Untyped + +Parameter Name : BYTEENA_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : INDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : ADDRESS_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : RDCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_BYTEENA_A +Value : 1 +Type : Signed Integer + +Parameter Name : WIDTH_BYTEENA_B +Value : 1 +Type : Signed Integer + +Parameter Name : RAM_BLOCK_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : BYTE_SIZE +Value : 8 +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS +Value : DONT_CARE +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_A +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_B +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : INIT_FILE +Value : led_patterns.mif +Type : Untyped + +Parameter Name : INIT_FILE_LAYOUT +Value : PORT_A +Type : Untyped + +Parameter Name : MAXIMUM_DEPTH +Value : 0 +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_B +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_B +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_A +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_B +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : ENABLE_ECC +Value : FALSE +Type : Untyped + +Parameter Name : ECC_PIPELINE_STAGE_ENABLED +Value : FALSE +Type : Untyped + +Parameter Name : WIDTH_ECCSTATUS +Value : 3 +Type : Untyped + +Parameter Name : DEVICE_FAMILY +Value : Cyclone IV E +Type : Untyped + +Parameter Name : CBXI_PARAMETER +Value : altsyncram_bui2 +Type : Untyped ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+--------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+--------------------------------------------+ +; Number of entity instances ; 2 ; +; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; ROM ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 16384 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; ram16:ram0|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 16384 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 16384 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; CLOCK0 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+--------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Port Connectivity Checks: "ram16:ram0" ; ++--------------------------------------------------------------------------------+ +Port : address_a +Type : Input +Severity : Warning +Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. + +Port : address_a[13..3] +Type : Input +Severity : Info +Details : Stuck at GND + +Port : q_a[7..4] +Type : Output +Severity : Info +Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. + +Port : wren_a +Type : Input +Severity : Warning +Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. + +Port : wren_a[-1] +Type : Input +Severity : Info +Details : Stuck at GND + +Port : data_b +Type : Input +Severity : Info +Details : Stuck at GND + +Port : q_b +Type : Output +Severity : Info +Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. + +Port : wren_b +Type : Input +Severity : Warning +Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. + +Port : wren_b[-1] +Type : Input +Severity : Info +Details : Stuck at GND ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Port Connectivity Checks: "rom0:rom" ; ++--------------------------------------------------------------------------------+ +Port : q[3..0] +Type : Output +Severity : Info +Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. ++--------------------------------------------------------------------------------+ + +-------------------------------+ @@ -896,16 +1315,20 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:12:11 2022 + Info: Processing started: Wed Mar 30 13:47:07 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12023): Found entity 1: spectrum Info (12021): Found 1 design units, including 1 entities, in source file rom0.v Info (12023): Found entity 1: rom0 +Info (12021): Found 1 design units, including 1 entities, in source file ram16.v + Info (12023): Found entity 1: ram16 Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22) -Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14) +Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22) +Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14) +Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16) Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" @@ -933,17 +1356,78 @@ Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf Info (12023): Found entity 1: mux_3nb Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2" +Info (12128): Elaborating entity "ram16" for hierarchy "ram16:ram0" +Info (12128): Elaborating entity "altsyncram" for hierarchy "ram16:ram0|altsyncram:altsyncram_component" +Info (12130): Elaborated megafunction instantiation "ram16:ram0|altsyncram:altsyncram_component" +Info (12133): Instantiated megafunction "ram16:ram0|altsyncram:altsyncram_component" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "clock_enable_input_a" = "BYPASS" + Info (12134): Parameter "clock_enable_input_b" = "BYPASS" + Info (12134): Parameter "clock_enable_output_a" = "BYPASS" + Info (12134): Parameter "clock_enable_output_b" = "BYPASS" + Info (12134): Parameter "indata_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "led_patterns.mif" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "16384" + Info (12134): Parameter "numwords_b" = "16384" + Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_aclr_b" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "CLOCK0" + Info (12134): Parameter "outdata_reg_b" = "CLOCK0" + Info (12134): Parameter "power_up_uninitialized" = "FALSE" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" + Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" + Info (12134): Parameter "widthad_a" = "14" + Info (12134): Parameter "widthad_b" = "14" + Info (12134): Parameter "width_a" = "8" + Info (12134): Parameter "width_b" = "8" + Info (12134): Parameter "width_byteena_a" = "1" + Info (12134): Parameter "width_byteena_b" = "1" + Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf + Info (12023): Found entity 1: altsyncram_bui2 +Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf + Info (12023): Found entity 1: decode_jsa +Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2" +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14" + Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10" + Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11" +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (286030): Timing-Driven Synthesis is running +Info (17049): 2 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1 input pins Info (21059): Implemented 8 output pins - Info (21061): Implemented 54 logic cells - Info (21064): Implemented 16 RAM segments -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 392 megabytes - Info: Processing ended: Wed Mar 30 13:12:13 2022 + Info (21061): Implemented 50 logic cells + Info (21064): Implemented 12 RAM segments +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings + Info: Peak virtual memory: 388 megabytes + Info: Processing ended: Wed Mar 30 13:47:09 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 3445a44..6e13905 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Wed Mar 30 13:12:13 2022 +Analysis & Synthesis Status : Successful - Wed Mar 30 13:47:09 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 54 - Total combinational functions : 52 +Total logic elements : 50 + Total combinational functions : 48 Dedicated logic registers : 38 Total registers : 38 Total pins : 9 Total virtual pins : 0 -Total memory bits : 131,072 +Total memory bits : 98,304 Embedded Multiplier 9-bit elements : 0 Total PLLs : 0 diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 442db49..f1de4ae 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 511d49e..74f236f 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Wed Mar 30 13:12:26 2022 +Wed Mar 30 13:47:22 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -133,7 +133,7 @@ Targets : { CLOCK_50 } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 358.68 MHz +Fmax : 355.62 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -152,8 +152,8 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.788 -End Point TNS : -88.557 +Slack : -1.812 +End Point TNS : -85.179 +--------------------------------------------------------------------------------+ @@ -162,7 +162,7 @@ End Point TNS : -88.557 ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.260 +Slack : 0.343 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -185,7 +185,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -110.836 +End Point TNS : -119.480 +--------------------------------------------------------------------------------+ @@ -193,310 +193,40 @@ End Point TNS : -110.836 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.788 -From Node : counter[14] -To Node : address[13] +Slack : -1.812 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.788 -From Node : counter[14] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.720 - -Slack : -1.781 -From Node : counter[13] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.781 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.713 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.125 Data Delay : 2.616 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Slack : -1.811 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.124 Data Delay : 2.616 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -1.811 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.124 Data Delay : 2.616 -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Slack : -1.811 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.124 Data Delay : 2.616 Slack : -1.756 @@ -571,527 +301,797 @@ Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.616 -Slack : -1.705 -From Node : counter[6] -To Node : address[13] +Slack : -1.506 +From Node : counter[2] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.637 +Data Delay : 2.438 -Slack : -1.705 -From Node : counter[6] -To Node : address[12] +Slack : -1.501 +From Node : counter[15] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[11] +Slack : -1.501 +From Node : counter[15] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[10] +Slack : -1.501 +From Node : counter[15] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[9] +Slack : -1.501 +From Node : counter[15] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[8] +Slack : -1.501 +From Node : counter[15] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[7] +Slack : -1.501 +From Node : counter[15] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[6] +Slack : -1.501 +From Node : counter[15] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[5] +Slack : -1.501 +From Node : counter[15] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[4] +Slack : -1.501 +From Node : counter[15] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[3] +Slack : -1.501 +From Node : counter[15] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[2] +Slack : -1.501 +From Node : counter[15] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.705 -From Node : counter[6] -To Node : address[1] +Slack : -1.501 +From Node : counter[15] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.637 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.698 -From Node : counter[7] -To Node : address[13] +Slack : -1.501 +From Node : counter[15] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.786 -Slack : -1.698 -From Node : counter[7] -To Node : address[12] +Slack : -1.499 +From Node : counter[14] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[11] +Slack : -1.499 +From Node : counter[14] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[10] +Slack : -1.499 +From Node : counter[14] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[9] +Slack : -1.499 +From Node : counter[14] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[8] +Slack : -1.499 +From Node : counter[14] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[7] +Slack : -1.499 +From Node : counter[14] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[6] +Slack : -1.499 +From Node : counter[14] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[5] +Slack : -1.499 +From Node : counter[14] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[4] +Slack : -1.499 +From Node : counter[14] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[3] +Slack : -1.499 +From Node : counter[14] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[2] +Slack : -1.499 +From Node : counter[14] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.698 -From Node : counter[7] -To Node : address[1] +Slack : -1.499 +From Node : counter[14] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.630 +Clock Skew : 0.290 +Data Delay : 2.784 -Slack : -1.691 +Slack : -1.499 +From Node : counter[14] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.290 +Data Delay : 2.784 + +Slack : -1.455 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.139 +Data Delay : 2.344 + +Slack : -1.436 +From Node : A[0] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.077 +Data Delay : 2.354 + +Slack : -1.428 From Node : counter[1] -To Node : address[13] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.623 +Data Delay : 2.360 -Slack : -1.691 +Slack : -1.424 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.138 +Data Delay : 2.314 + +Slack : -1.423 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.141 +Data Delay : 2.310 + +Slack : -1.423 +From Node : counter[0] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.355 + +Slack : -1.418 +From Node : A[0] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.077 +Data Delay : 2.336 + +Slack : -1.406 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.142 +Data Delay : 2.292 + +Slack : -1.401 From Node : counter[1] -To Node : address[12] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[11] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[10] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[9] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[8] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[7] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[6] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[5] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[4] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[3] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[2] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.691 +Slack : -1.401 From Node : counter[1] -To Node : address[1] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.623 +Clock Skew : 0.289 +Data Delay : 2.685 -Slack : -1.684 +Slack : -1.401 +From Node : counter[1] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.685 + +Slack : -1.399 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.137 +Data Delay : 2.290 + +Slack : -1.394 From Node : counter[0] -To Node : address[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[11] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[5] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[2] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.684 +Slack : -1.394 From Node : counter[0] -To Node : address[1] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.616 +Clock Skew : 0.289 +Data Delay : 2.678 -Slack : -1.673 -From Node : counter[5] -To Node : address[13] +Slack : -1.391 +From Node : counter[4] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.605 +Data Delay : 2.323 -Slack : -1.673 -From Node : counter[5] -To Node : address[12] +Slack : -1.390 +From Node : counter[2] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.605 +Data Delay : 2.322 -Slack : -1.673 -From Node : counter[5] -To Node : address[11] +Slack : -1.385 +From Node : counter[0] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.605 +Data Delay : 2.317 -Slack : -1.673 -From Node : counter[5] -To Node : address[10] +Slack : -1.384 +From Node : counter[2] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.605 +Data Delay : 2.316 -Slack : -1.673 -From Node : counter[5] -To Node : address[9] +Slack : -1.382 +From Node : counter[1] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.063 -Data Delay : 2.605 +Data Delay : 2.314 -Slack : -1.673 -From Node : counter[5] -To Node : address[8] +Slack : -1.369 +From Node : counter[21] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.605 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.369 +From Node : counter[21] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.076 +Data Delay : 2.288 + +Slack : -1.367 +From Node : counter[6] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 + +Slack : -1.367 +From Node : counter[6] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.651 +--------------------------------------------------------------------------------+ @@ -1099,132 +1099,24 @@ Data Delay : 2.605 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.260 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.343 +From Node : A[0] +To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.824 - -Slack : 0.260 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.824 - -Slack : 0.267 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.831 - -Slack : 0.319 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.883 - -Slack : 0.339 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.903 - -Slack : 0.344 -From Node : address[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.076 +Clock Skew : 0.077 Data Delay : 0.577 -Slack : 0.345 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.909 - -Slack : 0.346 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.910 - -Slack : 0.355 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.919 - Slack : 0.360 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.924 - -Slack : 0.361 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.580 -Slack : 0.364 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.928 - -Slack : 0.365 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.929 - -Slack : 0.373 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 0.937 - Slack : 0.375 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] @@ -1243,13 +1135,13 @@ Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.610 -Slack : 0.408 -From Node : address[13] -To Node : address[13] +Slack : 0.394 +From Node : A[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.077 Data Delay : 0.628 Slack : 0.484 @@ -1270,68 +1162,50 @@ Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.071 -Slack : 0.526 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.554 +From Node : A[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.090 +Clock Skew : 0.077 +Data Delay : 0.788 -Slack : 0.537 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 0.555 +From Node : A[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.109 +Clock Skew : 0.077 +Data Delay : 0.789 -Slack : 0.545 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Slack : 0.555 +From Node : A[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.125 +Clock Skew : 0.077 +Data Delay : 0.789 -Slack : 0.546 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 0.555 +From Node : A[2] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.118 - -Slack : 0.552 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.116 - -Slack : 0.552 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.132 +Clock Skew : 0.077 +Data Delay : 0.789 Slack : 0.556 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +From Node : A[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.128 +Clock Skew : 0.077 +Data Delay : 0.790 Slack : 0.556 From Node : counter[14] @@ -1343,22 +1217,22 @@ Clock Skew : 0.062 Data Delay : 0.775 Slack : 0.556 -From Node : counter[10] -To Node : counter[10] +From Node : counter[6] +To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.775 +Clock Skew : 0.063 +Data Delay : 0.776 -Slack : 0.556 -From Node : counter[8] -To Node : counter[8] +Slack : 0.557 +From Node : A[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.775 +Clock Skew : 0.077 +Data Delay : 0.791 Slack : 0.557 From Node : counter[12] @@ -1369,14 +1243,14 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.776 -Slack : 0.557 -From Node : counter[6] -To Node : counter[6] +Slack : 0.558 +From Node : A[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.776 +Clock Skew : 0.077 +Data Delay : 0.792 Slack : 0.558 From Node : counter[16] @@ -1396,6 +1270,15 @@ Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.792 +Slack : 0.559 +From Node : A[5] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.793 + Slack : 0.559 From Node : counter[17] To Node : counter[17] @@ -1411,36 +1294,45 @@ To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.778 - -Slack : 0.560 -From Node : counter[13] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.779 -Slack : 0.560 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.779 - -Slack : 0.560 +Slack : 0.559 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.779 +Slack : 0.560 +From Node : A[11] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.794 + +Slack : 0.560 +From Node : counter[5] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.780 + +Slack : 0.560 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.780 + Slack : 0.561 From Node : counter[18] To Node : counter[18] @@ -1450,42 +1342,6 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.780 -Slack : 0.561 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.780 - -Slack : 0.561 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.780 - -Slack : 0.562 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.781 - -Slack : 0.563 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.135 - Slack : 0.563 From Node : counter[19] To Node : counter[19] @@ -1496,62 +1352,26 @@ Clock Skew : 0.062 Data Delay : 0.782 Slack : 0.567 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.139 - -Slack : 0.568 -From Node : address[4] -To Node : address[4] +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.788 +Data Delay : 0.787 -Slack : 0.569 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.149 - -Slack : 0.569 -From Node : address[12] -To Node : address[12] +Slack : 0.567 +From Node : counter[8] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.789 - -Slack : 0.569 -From Node : address[6] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.789 - -Slack : 0.569 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.789 +Data Delay : 0.787 Slack : 0.570 -From Node : address[7] -To Node : address[7] +From Node : counter[0] +To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -1559,8 +1379,8 @@ Clock Skew : 0.063 Data Delay : 0.790 Slack : 0.571 -From Node : address[10] -To Node : address[10] +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -1568,103 +1388,40 @@ Clock Skew : 0.063 Data Delay : 0.791 Slack : 0.571 -From Node : counter[0] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.790 - -Slack : 0.572 -From Node : address[8] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.792 - -Slack : 0.573 -From Node : address[5] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.793 - -Slack : 0.573 From Node : counter[1] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.791 + +Slack : 0.572 +From Node : counter[11] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 Clock Skew : 0.062 +Data Delay : 0.791 + +Slack : 0.572 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 Data Delay : 0.792 -Slack : 0.574 -From Node : address[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.793 - -Slack : 0.574 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.146 - -Slack : 0.574 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.138 - -Slack : 0.574 -From Node : address[11] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.794 - -Slack : 0.574 -From Node : address[9] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.794 - -Slack : 0.574 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.793 - Slack : 0.579 -From Node : address[1] -To Node : address[1] +From Node : A[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.799 +Clock Skew : 0.077 +Data Delay : 0.813 Slack : 0.579 From Node : counter[18] @@ -1684,33 +1441,6 @@ Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.166 -Slack : 0.582 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.154 - -Slack : 0.584 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.385 -Data Delay : 1.156 - -Slack : 0.591 -From Node : address[3] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.811 - Slack : 0.593 From Node : counter[17] To Node : counter[20] @@ -1729,176 +1459,50 @@ Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.180 -Slack : 0.600 -From Node : address[10] +Slack : 0.603 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.026 +Data Delay : 0.816 + +Slack : 0.604 +From Node : A[1] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.180 +Clock Skew : 0.026 +Data Delay : 0.817 -Slack : 0.601 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.681 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.165 +Clock Skew : -0.037 +Data Delay : 0.831 -Slack : 0.611 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Slack : 0.685 +From Node : A[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.191 +Clock Skew : -0.037 +Data Delay : 0.835 -Slack : 0.624 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Slack : 0.687 +From Node : A[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.204 - -Slack : 0.628 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.208 - -Slack : 0.629 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.209 - -Slack : 0.632 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.212 - -Slack : 0.635 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.199 - -Slack : 0.636 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.216 - -Slack : 0.637 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.201 - -Slack : 0.641 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.205 - -Slack : 0.641 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.205 - -Slack : 0.642 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.222 - -Slack : 0.650 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.214 - -Slack : 0.650 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.230 - -Slack : 0.663 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.243 - -Slack : 0.672 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.236 - -Slack : 0.675 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.255 - -Slack : 0.677 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.241 +Clock Skew : 0.077 +Data Delay : 0.921 Slack : 0.689 From Node : counter[16] @@ -1918,41 +1522,104 @@ Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.276 -Slack : 0.707 +Slack : 0.703 From Node : counter[15] -To Node : counter[20] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.292 +Clock Skew : 0.062 +Data Delay : 0.922 -Slack : 0.709 -From Node : counter[15] -To Node : counter[21] +Slack : 0.703 +From Node : counter[13] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.294 +Clock Skew : 0.062 +Data Delay : 0.922 -Slack : 0.787 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Slack : 0.717 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.358 +Clock Skew : 0.026 +Data Delay : 0.930 -Slack : 0.790 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.721 +From Node : A[0] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.377 -Data Delay : 1.354 +Clock Skew : 0.026 +Data Delay : 0.934 + +Slack : 0.742 +From Node : A[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.892 + +Slack : 0.746 +From Node : A[1] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.980 + +Slack : 0.753 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.903 + +Slack : 0.754 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.904 + +Slack : 0.767 +From Node : A[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.917 + +Slack : 0.779 +From Node : A[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.929 + +Slack : 0.784 +From Node : A[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.037 +Data Delay : 0.934 Slack : 0.799 From Node : counter[14] @@ -1972,32 +1639,365 @@ Relationship : 0.000 Clock Skew : 0.428 Data Delay : 1.386 -Slack : 0.808 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Slack : 0.829 +From Node : A[2] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.388 +Clock Skew : 0.077 +Data Delay : 1.063 -Slack : 0.808 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Slack : 0.829 +From Node : A[4] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.379 +Clock Skew : 0.077 +Data Delay : 1.063 -Slack : 0.810 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Slack : 0.830 +From Node : A[12] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.393 -Data Delay : 1.390 +Clock Skew : 0.077 +Data Delay : 1.064 + +Slack : 0.830 +From Node : A[6] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.064 + +Slack : 0.831 +From Node : A[10] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.065 + +Slack : 0.831 +From Node : counter[6] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.051 + +Slack : 0.831 +From Node : counter[14] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.050 + +Slack : 0.831 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.050 + +Slack : 0.832 +From Node : counter[20] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.066 + +Slack : 0.833 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.052 + +Slack : 0.833 +From Node : counter[4] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.053 + +Slack : 0.833 +From Node : counter[2] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.053 + +Slack : 0.835 +From Node : counter[18] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.054 + +Slack : 0.842 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.062 + +Slack : 0.843 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.062 + +Slack : 0.844 +From Node : A[7] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.078 + +Slack : 0.845 +From Node : A[3] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.079 + +Slack : 0.845 +From Node : counter[1] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.065 + +Slack : 0.846 +From Node : A[5] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.080 + +Slack : 0.846 +From Node : A[7] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.080 + +Slack : 0.847 +From Node : A[11] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.081 + +Slack : 0.847 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.067 + +Slack : 0.847 +From Node : counter[3] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.067 + +Slack : 0.847 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.066 + +Slack : 0.847 +From Node : A[3] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.081 + +Slack : 0.847 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.067 + +Slack : 0.848 +From Node : A[5] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.082 + +Slack : 0.848 +From Node : counter[0] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.068 + +Slack : 0.849 +From Node : counter[15] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.434 + +Slack : 0.849 +From Node : A[11] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.083 + +Slack : 0.849 +From Node : counter[5] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.069 + +Slack : 0.849 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.069 + +Slack : 0.849 +From Node : counter[17] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.068 + +Slack : 0.850 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.070 + +Slack : 0.851 +From Node : counter[15] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.436 + +Slack : 0.858 +From Node : counter[9] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.078 + +Slack : 0.859 +From Node : counter[11] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.078 + +Slack : 0.859 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.079 + +Slack : 0.861 +From Node : counter[11] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.080 + +Slack : 0.861 +From Node : counter[7] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.081 +--------------------------------------------------------------------------------+ @@ -2019,7 +2019,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 @@ -2027,7 +2027,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2035,7 +2035,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2043,7 +2043,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2051,7 +2051,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2059,7 +2059,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 @@ -2067,7 +2067,111 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2133,46 +2237,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -2237,37 +2301,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -2.174 +Slack : -1.000 Actual Width : 1.000 -Required Width : 3.174 +Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : A[0] Slack : -1.000 Actual Width : 1.000 @@ -2275,7 +2315,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[0] +Target : A[10] Slack : -1.000 Actual Width : 1.000 @@ -2283,7 +2323,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[10] +Target : A[11] Slack : -1.000 Actual Width : 1.000 @@ -2291,7 +2331,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[11] +Target : A[12] Slack : -1.000 Actual Width : 1.000 @@ -2299,7 +2339,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[12] +Target : A[13] Slack : -1.000 Actual Width : 1.000 @@ -2307,7 +2347,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[13] +Target : A[1] Slack : -1.000 Actual Width : 1.000 @@ -2315,7 +2355,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[1] +Target : A[2] Slack : -1.000 Actual Width : 1.000 @@ -2323,7 +2363,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[2] +Target : A[3] Slack : -1.000 Actual Width : 1.000 @@ -2331,7 +2371,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[3] +Target : A[4] Slack : -1.000 Actual Width : 1.000 @@ -2339,7 +2379,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[4] +Target : A[5] Slack : -1.000 Actual Width : 1.000 @@ -2347,7 +2387,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[5] +Target : A[6] Slack : -1.000 Actual Width : 1.000 @@ -2355,7 +2395,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[6] +Target : A[7] Slack : -1.000 Actual Width : 1.000 @@ -2363,7 +2403,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[7] +Target : A[8] Slack : -1.000 Actual Width : 1.000 @@ -2371,15 +2411,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[8] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[9] +Target : A[9] Slack : -1.000 Actual Width : 1.000 @@ -2579,7 +2611,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 @@ -2595,15 +2627,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 @@ -2619,15 +2643,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : -0.011 -Actual Width : 0.219 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 @@ -2635,7 +2651,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 @@ -2643,7 +2659,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -0.010 Actual Width : 0.220 @@ -2651,7 +2667,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : -0.010 Actual Width : 0.220 @@ -2661,14 +2701,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 @@ -2683,15 +2715,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 @@ -2699,7 +2723,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -0.007 Actual Width : 0.223 @@ -2707,15 +2739,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.007 Actual Width : 0.223 @@ -2731,7 +2755,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.007 Actual Width : 0.223 @@ -2747,39 +2771,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.006 Actual Width : 0.224 @@ -2795,7 +2787,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -0.006 Actual Width : 0.224 @@ -2803,7 +2795,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : 0.000 +Actual Width : 0.230 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +--------------------------------------------------------------------------------+ @@ -2813,64 +2813,64 @@ Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_g +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 10.470 -Fall : 10.183 +Rise : 10.303 +Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 8.036 -Fall : 8.004 +Rise : 7.474 +Fall : 7.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.982 -Fall : 7.929 +Rise : 7.915 +Fall : 7.923 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 8.151 -Fall : 8.115 +Rise : 7.907 +Fall : 7.878 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 7.654 -Fall : 7.638 +Rise : 7.123 +Fall : 7.073 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.866 -Fall : 7.844 +Rise : 8.891 +Fall : 8.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 10.470 -Fall : 10.183 +Rise : 10.303 +Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 8.654 -Fall : 8.642 +Rise : 8.706 +Fall : 8.626 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 9.306 -Fall : 9.035 +Rise : 9.651 +Fall : 9.302 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2882,64 +2882,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.669 -Fall : 6.608 +Rise : 6.895 +Fall : 6.842 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 7.397 -Fall : 7.346 +Rise : 7.233 +Fall : 7.193 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.524 -Fall : 7.491 +Rise : 7.656 +Fall : 7.659 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.479 -Fall : 7.390 +Rise : 7.648 +Fall : 7.616 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.669 -Fall : 6.608 +Rise : 6.895 +Fall : 6.842 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.067 -Fall : 7.031 +Rise : 8.165 +Fall : 8.150 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.908 -Fall : 9.604 +Rise : 9.531 +Fall : 9.293 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.824 -Fall : 7.751 +Rise : 8.085 +Fall : 8.027 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.799 -Fall : 8.511 +Rise : 9.079 +Fall : 8.736 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2955,7 +2955,7 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 395.73 MHz +Fmax : 395.1 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -2968,8 +2968,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.527 -End Point TNS : -72.611 +Slack : -1.531 +End Point TNS : -69.352 +--------------------------------------------------------------------------------+ @@ -2978,7 +2978,7 @@ End Point TNS : -72.611 ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.255 +Slack : 0.299 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -3001,7 +3001,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -110.824 +End Point TNS : -119.478 +--------------------------------------------------------------------------------+ @@ -3009,310 +3009,40 @@ End Point TNS : -110.824 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.527 -From Node : counter[14] -To Node : address[13] +Slack : -1.531 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.527 -From Node : counter[14] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.466 - -Slack : -1.520 -From Node : counter[13] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.520 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.459 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.116 Data Delay : 2.353 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Slack : -1.531 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.116 Data Delay : 2.353 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -1.531 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.116 Data Delay : 2.353 -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Slack : -1.531 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 +Clock Skew : -0.116 Data Delay : 2.353 Slack : -1.484 @@ -3387,527 +3117,797 @@ Relationship : 1.000 Clock Skew : -0.069 Data Delay : 2.353 -Slack : -1.448 -From Node : counter[6] -To Node : address[13] +Slack : -1.265 +From Node : counter[15] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.265 +From Node : counter[15] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.522 + +Slack : -1.264 +From Node : counter[14] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.264 +From Node : counter[14] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.262 +Data Delay : 2.521 + +Slack : -1.221 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.132 +Data Delay : 2.109 + +Slack : -1.200 +From Node : counter[2] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.056 -Data Delay : 2.387 +Data Delay : 2.139 -Slack : -1.448 -From Node : counter[6] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.448 -From Node : counter[6] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.387 - -Slack : -1.442 -From Node : counter[7] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.442 -From Node : counter[7] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.381 - -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[11] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[5] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[2] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.431 +Slack : -1.177 From Node : counter[1] -To Node : address[1] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.370 +Clock Skew : 0.261 +Data Delay : 2.433 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[11] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[7] +To Node : A[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[5] +To Node : A[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[2] +To Node : A[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.425 +Slack : -1.170 From Node : counter[0] -To Node : address[1] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.364 +Clock Skew : 0.261 +Data Delay : 2.426 -Slack : -1.423 -From Node : counter[5] -To Node : address[13] +Slack : -1.169 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.362 +Clock Skew : -0.130 +Data Delay : 2.059 -Slack : -1.423 -From Node : counter[5] -To Node : address[12] +Slack : -1.169 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.362 +Clock Skew : -0.133 +Data Delay : 2.056 -Slack : -1.423 -From Node : counter[5] -To Node : address[11] +Slack : -1.168 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.362 +Clock Skew : -0.131 +Data Delay : 2.057 -Slack : -1.423 -From Node : counter[5] -To Node : address[10] +Slack : -1.157 +From Node : A[0] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.362 +Clock Skew : -0.068 +Data Delay : 2.084 -Slack : -1.423 -From Node : counter[5] -To Node : address[9] +Slack : -1.145 +From Node : A[0] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 2.362 +Clock Skew : -0.068 +Data Delay : 2.072 -Slack : -1.423 -From Node : counter[5] -To Node : address[8] +Slack : -1.144 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.136 +Data Delay : 2.028 + +Slack : -1.144 +From Node : counter[6] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.144 +From Node : counter[6] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.400 + +Slack : -1.139 +From Node : counter[1] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.056 -Data Delay : 2.362 +Data Delay : 2.078 + +Slack : -1.137 +From Node : counter[4] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.137 +From Node : counter[4] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.261 +Data Delay : 2.393 + +Slack : -1.131 +From Node : counter[21] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.067 +Data Delay : 2.059 +--------------------------------------------------------------------------------+ @@ -3915,157 +3915,49 @@ Data Delay : 2.362 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.255 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.299 +From Node : A[0] +To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.761 - -Slack : 0.255 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.761 - -Slack : 0.261 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.767 - -Slack : 0.300 -From Node : address[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.067 +Clock Skew : 0.068 Data Delay : 0.511 -Slack : 0.312 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.818 - -Slack : 0.319 +Slack : 0.320 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.519 -Slack : 0.329 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.835 - Slack : 0.334 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.840 - -Slack : 0.335 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.841 - -Slack : 0.335 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.069 Data Delay : 0.547 -Slack : 0.341 +Slack : 0.340 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.540 +Data Delay : 0.539 -Slack : 0.344 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 0.352 +From Node : A[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.850 - -Slack : 0.346 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.852 - -Slack : 0.353 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.859 - -Slack : 0.354 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.860 - -Slack : 0.357 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 0.863 - -Slack : 0.365 -From Node : address[13] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 +Clock Skew : 0.068 Data Delay : 0.564 Slack : 0.425 @@ -4087,94 +3979,112 @@ Clock Skew : 0.384 Data Delay : 0.960 Slack : 0.498 -From Node : counter[10] -To Node : counter[10] +From Node : A[4] +To Node : A[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.698 +Clock Skew : 0.068 +Data Delay : 0.710 Slack : 0.499 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +From Node : A[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.005 +Clock Skew : 0.068 +Data Delay : 0.711 Slack : 0.499 +From Node : A[6] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.711 + +Slack : 0.499 +From Node : A[2] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.711 + +Slack : 0.500 +From Node : A[7] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.712 + +Slack : 0.500 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.699 -Slack : 0.499 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.699 - -Slack : 0.499 +Slack : 0.500 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.699 -Slack : 0.500 +Slack : 0.501 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.700 -Slack : 0.500 +Slack : 0.501 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.700 -Slack : 0.502 -From Node : counter[17] -To Node : counter[17] +Slack : 0.501 +From Node : counter[20] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.702 +Clock Skew : 0.069 +Data Delay : 0.714 Slack : 0.502 -From Node : counter[13] -To Node : counter[13] +From Node : A[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.702 +Clock Skew : 0.068 +Data Delay : 0.714 Slack : 0.502 -From Node : counter[7] -To Node : counter[7] +From Node : A[3] +To Node : A[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.702 +Clock Skew : 0.068 +Data Delay : 0.714 Slack : 0.502 From Node : counter[4] @@ -4182,70 +4092,79 @@ To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.503 +From Node : A[5] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.715 + +Slack : 0.503 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.702 -Slack : 0.502 +Slack : 0.503 From Node : counter[2] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.702 -Slack : 0.502 -From Node : counter[20] -To Node : counter[20] +Slack : 0.504 +From Node : A[11] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.714 +Data Delay : 0.716 -Slack : 0.503 +Slack : 0.504 From Node : counter[18] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.703 -Slack : 0.503 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.703 - -Slack : 0.504 +Slack : 0.505 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.704 -Slack : 0.504 -From Node : counter[15] -To Node : counter[15] +Slack : 0.505 +From Node : counter[5] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.704 -Slack : 0.504 +Slack : 0.505 From Node : counter[3] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.704 Slack : 0.509 @@ -4257,72 +4176,45 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.037 -Slack : 0.511 -From Node : address[4] -To Node : address[4] +Slack : 0.510 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.710 +Data Delay : 0.709 -Slack : 0.512 -From Node : address[12] -To Node : address[12] +Slack : 0.510 +From Node : counter[8] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.711 +Data Delay : 0.709 -Slack : 0.512 -From Node : address[6] -To Node : address[6] +Slack : 0.514 +From Node : counter[11] +To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.711 +Data Delay : 0.713 -Slack : 0.512 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.711 - -Slack : 0.513 -From Node : address[7] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.712 - -Slack : 0.513 +Slack : 0.514 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.713 -Slack : 0.514 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.026 - Slack : 0.515 -From Node : address[10] -To Node : address[10] +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -4330,41 +4222,14 @@ Clock Skew : 0.055 Data Delay : 0.714 Slack : 0.515 -From Node : address[8] -To Node : address[8] +From Node : counter[7] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.714 -Slack : 0.515 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.715 - -Slack : 0.515 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.715 - -Slack : 0.516 -From Node : address[5] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.715 - Slack : 0.516 From Node : counter[18] To Node : counter[21] @@ -4374,32 +4239,14 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.044 -Slack : 0.517 -From Node : address[11] -To Node : address[11] +Slack : 0.516 +From Node : counter[1] +To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.716 - -Slack : 0.517 -From Node : address[9] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.716 - -Slack : 0.518 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.038 +Data Delay : 0.715 Slack : 0.519 From Node : counter[17] @@ -4410,32 +4257,14 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.047 -Slack : 0.522 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.521 +From Node : A[9] +To Node : A[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.028 - -Slack : 0.524 -From Node : address[1] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.723 - -Slack : 0.525 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.037 +Clock Skew : 0.068 +Data Delay : 0.733 Slack : 0.526 From Node : counter[17] @@ -4446,167 +4275,23 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.054 -Slack : 0.527 -From Node : address[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +Slack : 0.562 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.726 +Clock Skew : 0.021 +Data Delay : 0.752 -Slack : 0.527 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.047 - -Slack : 0.532 -From Node : address[3] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.731 - -Slack : 0.537 -From Node : address[4] +Slack : 0.563 +From Node : A[1] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.057 - -Slack : 0.541 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.047 - -Slack : 0.542 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.054 - -Slack : 0.544 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.056 - -Slack : 0.544 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.056 - -Slack : 0.554 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.066 - -Slack : 0.558 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.070 - -Slack : 0.559 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.343 -Data Delay : 1.071 - -Slack : 0.567 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.073 - -Slack : 0.570 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.090 - -Slack : 0.581 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.101 - -Slack : 0.592 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.112 - -Slack : 0.596 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.116 - -Slack : 0.597 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.117 - -Slack : 0.598 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.104 +Clock Skew : 0.021 +Data Delay : 0.753 Slack : 0.601 From Node : counter[16] @@ -4617,60 +4302,6 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.129 -Slack : 0.602 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.122 - -Slack : 0.602 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.122 - -Slack : 0.603 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.109 - -Slack : 0.607 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.113 - -Slack : 0.607 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.113 - -Slack : 0.608 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.128 - Slack : 0.608 From Node : counter[16] To Node : counter[21] @@ -4680,77 +4311,86 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.136 -Slack : 0.615 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.625 +From Node : A[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.121 +Clock Skew : 0.068 +Data Delay : 0.837 -Slack : 0.616 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Slack : 0.639 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.136 +Clock Skew : -0.039 +Data Delay : 0.769 -Slack : 0.617 +Slack : 0.642 +From Node : A[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.039 +Data Delay : 0.772 + +Slack : 0.644 From Node : counter[15] -To Node : counter[20] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.145 +Clock Skew : 0.055 +Data Delay : 0.843 -Slack : 0.624 -From Node : counter[15] -To Node : counter[21] +Slack : 0.645 +From Node : counter[13] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.152 +Clock Skew : 0.055 +Data Delay : 0.844 -Slack : 0.628 -From Node : address[3] +Slack : 0.666 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.021 +Data Delay : 0.856 + +Slack : 0.670 +From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.148 +Clock Skew : 0.021 +Data Delay : 0.860 -Slack : 0.633 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.678 +From Node : A[1] +To Node : A[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.139 +Clock Skew : 0.068 +Data Delay : 0.890 -Slack : 0.635 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.695 +From Node : A[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.337 -Data Delay : 1.141 - -Slack : 0.638 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.351 -Data Delay : 1.158 +Clock Skew : -0.039 +Data Delay : 0.825 Slack : 0.696 From Node : counter[14] @@ -4761,6 +4401,15 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.224 +Slack : 0.702 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.039 +Data Delay : 0.832 + Slack : 0.703 From Node : counter[14] To Node : counter[21] @@ -4770,50 +4419,401 @@ Relationship : 0.000 Clock Skew : 0.384 Data Delay : 1.231 -Slack : 0.711 -From Node : counter[13] -To Node : counter[20] +Slack : 0.707 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.239 +Clock Skew : -0.039 +Data Delay : 0.837 Slack : 0.718 -From Node : counter[13] -To Node : counter[21] +From Node : A[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.384 -Data Delay : 1.246 +Clock Skew : -0.039 +Data Delay : 0.848 + +Slack : 0.731 +From Node : A[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.039 +Data Delay : 0.861 + +Slack : 0.735 +From Node : A[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.039 +Data Delay : 0.865 + +Slack : 0.742 +From Node : A[4] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.954 Slack : 0.743 +From Node : A[12] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.955 + +Slack : 0.743 +From Node : A[6] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.955 + +Slack : 0.744 +From Node : A[2] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.956 + +Slack : 0.744 From Node : counter[6] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.943 -Slack : 0.743 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.943 - -Slack : 0.743 +Slack : 0.744 From Node : counter[14] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 Data Delay : 0.943 + +Slack : 0.745 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.944 + +Slack : 0.746 +From Node : counter[20] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.959 + +Slack : 0.746 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.945 + +Slack : 0.747 +From Node : A[10] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.959 + +Slack : 0.747 +From Node : counter[4] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.946 + +Slack : 0.748 +From Node : counter[2] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.749 +From Node : counter[18] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.948 + +Slack : 0.749 +From Node : A[7] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.961 + +Slack : 0.751 +From Node : A[3] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.963 + +Slack : 0.751 +From Node : counter[1] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.752 +From Node : A[5] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.964 + +Slack : 0.752 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.753 +From Node : A[11] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.965 + +Slack : 0.753 +From Node : counter[0] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.952 + +Slack : 0.754 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.754 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.754 +From Node : counter[3] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.755 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.953 + +Slack : 0.756 +From Node : A[7] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.968 + +Slack : 0.756 +From Node : counter[15] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.284 + +Slack : 0.758 +From Node : A[3] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.970 + +Slack : 0.758 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.759 +From Node : A[5] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.971 + +Slack : 0.759 +From Node : counter[17] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.760 +From Node : A[11] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.972 + +Slack : 0.760 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.959 + +Slack : 0.761 +From Node : counter[5] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.761 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.763 +From Node : counter[11] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.962 + +Slack : 0.763 +From Node : counter[15] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.291 + +Slack : 0.764 +From Node : counter[9] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.963 + +Slack : 0.764 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.963 + +Slack : 0.770 +From Node : A[9] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.982 + +Slack : 0.770 +From Node : counter[11] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.969 +--------------------------------------------------------------------------------+ @@ -4835,7 +4835,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 @@ -4843,7 +4843,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4851,7 +4851,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4859,7 +4859,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4867,7 +4867,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4875,7 +4875,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 @@ -4883,7 +4883,111 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4949,46 +5053,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - Slack : -2.174 Actual Width : 1.000 Required Width : 3.174 @@ -5053,37 +5117,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -2.174 +Slack : -1.000 Actual Width : 1.000 -Required Width : 3.174 +Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : -2.174 -Actual Width : 1.000 -Required Width : 3.174 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : A[0] Slack : -1.000 Actual Width : 1.000 @@ -5091,7 +5131,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[0] +Target : A[10] Slack : -1.000 Actual Width : 1.000 @@ -5099,7 +5139,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[10] +Target : A[11] Slack : -1.000 Actual Width : 1.000 @@ -5107,7 +5147,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[11] +Target : A[12] Slack : -1.000 Actual Width : 1.000 @@ -5115,7 +5155,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[12] +Target : A[13] Slack : -1.000 Actual Width : 1.000 @@ -5123,7 +5163,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[13] +Target : A[1] Slack : -1.000 Actual Width : 1.000 @@ -5131,7 +5171,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[1] +Target : A[2] Slack : -1.000 Actual Width : 1.000 @@ -5139,7 +5179,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[2] +Target : A[3] Slack : -1.000 Actual Width : 1.000 @@ -5147,7 +5187,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[3] +Target : A[4] Slack : -1.000 Actual Width : 1.000 @@ -5155,7 +5195,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[4] +Target : A[5] Slack : -1.000 Actual Width : 1.000 @@ -5163,7 +5203,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[5] +Target : A[6] Slack : -1.000 Actual Width : 1.000 @@ -5171,7 +5211,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[6] +Target : A[7] Slack : -1.000 Actual Width : 1.000 @@ -5179,7 +5219,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[7] +Target : A[8] Slack : -1.000 Actual Width : 1.000 @@ -5187,15 +5227,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[8] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[9] +Target : A[9] Slack : -1.000 Actual Width : 1.000 @@ -5389,6 +5421,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 @@ -5403,7 +5443,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Slack : -0.011 Actual Width : 0.219 @@ -5413,13 +5461,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -0.011 -Actual Width : 0.219 +Slack : -0.010 +Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 @@ -5427,23 +5475,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -0.010 Actual Width : 0.220 @@ -5453,14 +5485,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 @@ -5475,15 +5499,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : -0.010 -Actual Width : 0.220 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 @@ -5491,7 +5507,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.009 Actual Width : 0.221 @@ -5499,23 +5515,47 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 -Slack : -0.009 -Actual Width : 0.221 +Slack : -0.008 +Actual Width : 0.222 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 -Slack : -0.009 -Actual Width : 0.221 +Slack : -0.008 +Actual Width : 0.222 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.007 Actual Width : 0.223 @@ -5531,7 +5571,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.007 Actual Width : 0.223 @@ -5541,38 +5589,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Slack : -0.007 -Actual Width : 0.223 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 @@ -5581,14 +5597,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -Slack : -0.006 -Actual Width : 0.224 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - Slack : -0.006 Actual Width : 0.224 Required Width : 0.230 @@ -5603,23 +5611,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 -Slack : -0.006 -Actual Width : 0.224 +Slack : -0.002 +Actual Width : 0.228 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : -0.005 -Actual Width : 0.225 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +--------------------------------------------------------------------------------+ @@ -5629,64 +5629,64 @@ Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_g +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 9.439 -Fall : 8.980 +Rise : 9.271 +Fall : 8.853 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 7.273 -Fall : 7.194 +Rise : 6.755 +Fall : 6.657 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.209 -Fall : 7.095 +Rise : 7.164 +Fall : 7.086 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.387 -Fall : 7.257 +Rise : 7.155 +Fall : 7.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.922 -Fall : 6.837 +Rise : 6.435 +Fall : 6.313 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.090 -Fall : 6.963 +Rise : 8.039 +Fall : 7.928 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.439 -Fall : 8.980 +Rise : 9.271 +Fall : 8.853 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.889 -Fall : 7.717 +Rise : 7.923 +Fall : 7.721 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.347 -Fall : 7.950 +Rise : 8.704 +Fall : 8.167 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5698,64 +5698,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.027 -Fall : 5.921 +Rise : 6.217 +Fall : 6.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.683 -Fall : 6.586 +Rise : 6.524 +Fall : 6.427 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.797 -Fall : 6.677 +Rise : 6.917 +Fall : 6.838 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 6.758 -Fall : 6.608 +Rise : 6.908 +Fall : 6.793 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.027 -Fall : 5.921 +Rise : 6.217 +Fall : 6.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.376 -Fall : 6.259 +Rise : 7.382 +Fall : 7.269 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.947 -Fall : 8.480 +Rise : 8.568 +Fall : 8.173 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.114 -Fall : 6.908 +Rise : 7.330 +Fall : 7.173 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 7.910 -Fall : 7.506 +Rise : 8.145 +Fall : 7.660 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5772,8 +5772,8 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.529 -End Point TNS : -18.538 +Slack : -0.444 +End Point TNS : -17.149 +--------------------------------------------------------------------------------+ @@ -5782,7 +5782,7 @@ End Point TNS : -18.538 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.123 +Slack : 0.178 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -5805,7 +5805,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -93.684 +End Point TNS : -99.404 +--------------------------------------------------------------------------------+ @@ -5813,905 +5813,905 @@ End Point TNS : -93.684 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.529 -From Node : counter[14] -To Node : address[13] +Slack : -0.444 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[14] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.529 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.479 - -Slack : -0.489 -From Node : counter[6] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[6] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.489 -From Node : counter[7] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.439 - -Slack : -0.486 -From Node : counter[1] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 +Clock Skew : -0.077 +Data Delay : 1.376 -Slack : -0.486 -From Node : counter[1] -To Node : address[5] +Slack : -0.424 +From Node : counter[2] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.436 +Data Delay : 1.374 -Slack : -0.486 -From Node : counter[1] -To Node : address[4] +Slack : -0.423 +From Node : A[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[1] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 +Clock Skew : -0.075 +Data Delay : 1.357 -Slack : -0.486 -From Node : counter[1] -To Node : address[1] +Slack : -0.411 +From Node : A[0] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 +Clock Skew : -0.075 +Data Delay : 1.345 -Slack : -0.486 -From Node : counter[0] -To Node : address[13] +Slack : -0.411 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 +Clock Skew : -0.076 +Data Delay : 1.344 -Slack : -0.486 -From Node : counter[0] -To Node : address[12] +Slack : -0.407 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.486 -From Node : counter[0] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.436 - -Slack : -0.479 -From Node : counter[5] -To Node : address[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 - -Slack : -0.479 -From Node : counter[5] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.429 +Clock Skew : -0.079 +Data Delay : 1.337 -Slack : -0.446 -From Node : address[13] +Slack : -0.401 +From Node : A[13] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.122 -Data Delay : 1.577 +Clock Skew : -0.081 +Data Delay : 1.329 -Slack : -0.443 -From Node : counter[11] -To Node : address[13] +Slack : -0.394 +From Node : A[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.075 +Data Delay : 1.328 + +Slack : -0.385 +From Node : A[0] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.045 +Data Delay : 1.327 + +Slack : -0.380 +From Node : counter[15] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.380 +From Node : counter[15] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.521 + +Slack : -0.377 +From Node : counter[0] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.327 -Slack : -0.443 -From Node : counter[11] -To Node : address[12] +Slack : -0.375 +From Node : counter[1] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.325 -Slack : -0.443 -From Node : counter[11] -To Node : address[11] +Slack : -0.374 +From Node : counter[14] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.374 +From Node : counter[14] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.154 +Data Delay : 1.515 + +Slack : -0.360 +From Node : counter[2] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.310 -Slack : -0.443 -From Node : counter[11] -To Node : address[10] +Slack : -0.356 +From Node : counter[2] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.306 -Slack : -0.443 -From Node : counter[11] -To Node : address[9] +Slack : -0.356 +From Node : counter[4] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.306 -Slack : -0.443 -From Node : counter[11] -To Node : address[8] +Slack : -0.355 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.078 +Data Delay : 1.232 + +Slack : -0.355 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.078 +Data Delay : 1.232 + +Slack : -0.355 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.078 +Data Delay : 1.232 + +Slack : -0.354 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.077 +Data Delay : 1.232 + +Slack : -0.350 +From Node : counter[21] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.350 +From Node : counter[21] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.293 + +Slack : -0.345 +From Node : counter[1] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.295 -Slack : -0.443 -From Node : counter[11] -To Node : address[7] +Slack : -0.345 +From Node : counter[0] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.393 +Data Delay : 1.295 -Slack : -0.443 -From Node : counter[11] -To Node : address[6] +Slack : -0.336 +From Node : counter[20] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.393 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.336 +From Node : counter[20] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.044 +Data Delay : 1.279 + +Slack : -0.334 +From Node : A[0] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.045 +Data Delay : 1.276 + +Slack : -0.326 +From Node : counter[1] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.326 +From Node : counter[1] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.466 + +Slack : -0.325 +From Node : counter[0] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.325 +From Node : counter[0] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.465 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 +--------------------------------------------------------------------------------+ @@ -6719,123 +6719,15 @@ Data Delay : 1.393 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.123 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 0.178 +From Node : A[0] +To Node : A[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.446 - -Slack : 0.124 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.446 - -Slack : 0.128 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.451 - -Slack : 0.159 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.482 - -Slack : 0.173 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.496 - -Slack : 0.177 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.500 - -Slack : 0.177 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.500 - -Slack : 0.179 -From Node : address[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.044 +Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.180 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.503 - -Slack : 0.182 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.505 - -Slack : 0.184 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.507 - -Slack : 0.185 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.508 - -Slack : 0.188 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.511 - Slack : 0.193 From Node : counter[0] To Node : counter[0] @@ -6845,31 +6737,31 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.196 +Slack : 0.195 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.316 +Data Delay : 0.315 -Slack : 0.197 +Slack : 0.196 From Node : counter[21] To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.044 +Clock Skew : 0.045 Data Delay : 0.325 -Slack : 0.217 -From Node : address[13] -To Node : address[13] +Slack : 0.208 +From Node : A[13] +To Node : A[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.045 Data Delay : 0.337 Slack : 0.261 @@ -6890,132 +6782,60 @@ Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.582 -Slack : 0.276 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 0.296 +From Node : A[12] +To Node : A[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.603 - -Slack : 0.277 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.599 - -Slack : 0.281 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.608 - -Slack : 0.288 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.611 - -Slack : 0.293 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.620 - -Slack : 0.294 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.621 - -Slack : 0.295 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.416 +Clock Skew : 0.045 +Data Delay : 0.425 Slack : 0.296 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +From Node : A[6] +To Node : A[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.619 +Clock Skew : 0.045 +Data Delay : 0.425 Slack : 0.296 +From Node : A[4] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.425 + +Slack : 0.296 +From Node : A[2] +To Node : A[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.425 + +Slack : 0.297 +From Node : A[7] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.426 + +Slack : 0.297 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.417 - -Slack : 0.296 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.417 - -Slack : 0.297 -From Node : address[13] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.417 -Slack : 0.297 -From Node : counter[16] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.418 - -Slack : 0.297 -From Node : counter[14] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.418 - -Slack : 0.297 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.418 - Slack : 0.297 From Node : counter[6] To Node : counter[6] @@ -7025,18 +6845,54 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.418 -Slack : 0.297 -From Node : counter[4] -To Node : counter[4] +Slack : 0.298 +From Node : A[10] +To Node : A[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.045 +Data Delay : 0.427 + +Slack : 0.298 +From Node : A[5] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.427 + +Slack : 0.298 +From Node : A[3] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.427 + +Slack : 0.298 +From Node : counter[16] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 Data Delay : 0.418 Slack : 0.298 -From Node : counter[13] -To Node : counter[13] +From Node : counter[14] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.418 + +Slack : 0.298 +From Node : counter[4] +To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -7061,95 +6917,77 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.419 -Slack : 0.299 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.633 - -Slack : 0.299 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.299 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.299 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.299 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.299 +Slack : 0.298 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.044 +Clock Skew : 0.045 Data Delay : 0.427 -Slack : 0.300 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 0.299 +From Node : A[11] +To Node : A[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.627 +Clock Skew : 0.045 +Data Delay : 0.428 + +Slack : 0.299 +From Node : counter[5] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 Slack : 0.300 +From Node : counter[18] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.300 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.301 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 Data Delay : 0.421 -Slack : 0.301 -From Node : address[6] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 0.303 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.628 +Clock Skew : 0.037 +Data Delay : 0.424 Slack : 0.303 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +From Node : counter[8] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.630 +Clock Skew : 0.037 +Data Delay : 0.424 Slack : 0.304 From Node : counter[1] @@ -7161,49 +6999,13 @@ Clock Skew : 0.037 Data Delay : 0.425 Slack : 0.305 -From Node : address[4] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.639 - -Slack : 0.305 -From Node : address[12] -To Node : address[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.425 - -Slack : 0.305 -From Node : address[6] -To Node : address[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.425 - -Slack : 0.305 -From Node : address[4] -To Node : address[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.425 - -Slack : 0.305 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.425 +Clock Skew : 0.037 +Data Delay : 0.426 Slack : 0.305 From Node : counter[0] @@ -7215,17 +7017,8 @@ Clock Skew : 0.037 Data Delay : 0.426 Slack : 0.306 -From Node : address[1] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.229 -Data Delay : 0.639 - -Slack : 0.306 -From Node : address[8] -To Node : address[8] +From Node : counter[11] +To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 @@ -7233,76 +7026,40 @@ Clock Skew : 0.036 Data Delay : 0.426 Slack : 0.306 -From Node : address[7] -To Node : address[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.426 - -Slack : 0.306 -From Node : counter[5] -To Node : counter[5] +From Node : counter[7] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.427 -Slack : 0.307 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.634 - -Slack : 0.307 -From Node : address[10] -To Node : address[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.427 - -Slack : 0.307 -From Node : address[9] -To Node : address[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.427 - -Slack : 0.307 -From Node : address[5] -To Node : address[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.427 - Slack : 0.308 -From Node : address[11] -To Node : address[11] +From Node : A[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.428 +Clock Skew : 0.030 +Data Delay : 0.442 -Slack : 0.311 -From Node : address[1] -To Node : address[1] +Slack : 0.309 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.431 +Clock Skew : 0.029 +Data Delay : 0.442 + +Slack : 0.310 +From Node : A[9] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.439 Slack : 0.314 From Node : counter[18] @@ -7322,24 +7079,6 @@ Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.635 -Slack : 0.318 -From Node : address[3] -To Node : address[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.438 - -Slack : 0.319 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.642 - Slack : 0.326 From Node : counter[17] To Node : counter[20] @@ -7349,15 +7088,6 @@ Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.644 -Slack : 0.327 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.661 - Slack : 0.329 From Node : counter[17] To Node : counter[21] @@ -7367,158 +7097,68 @@ Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.647 -Slack : 0.334 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.359 +From Node : A[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.657 +Clock Skew : -0.012 +Data Delay : 0.451 -Slack : 0.338 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.361 +From Node : A[8] +To Node : A[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.660 +Clock Skew : 0.045 +Data Delay : 0.490 -Slack : 0.340 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.362 +From Node : A[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.662 +Clock Skew : -0.012 +Data Delay : 0.454 -Slack : 0.341 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Slack : 0.372 +From Node : counter[15] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.664 +Clock Skew : 0.036 +Data Delay : 0.492 -Slack : 0.342 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Slack : 0.372 +From Node : counter[13] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.664 +Clock Skew : 0.036 +Data Delay : 0.492 -Slack : 0.342 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.229 -Data Delay : 0.675 - -Slack : 0.344 -From Node : address[8] +Slack : 0.373 +From Node : A[0] To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.678 +Clock Skew : 0.030 +Data Delay : 0.507 -Slack : 0.346 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Slack : 0.376 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.680 - -Slack : 0.346 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.680 - -Slack : 0.346 -From Node : address[8] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.680 - -Slack : 0.348 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.682 - -Slack : 0.348 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.682 - -Slack : 0.353 -From Node : address[2] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.676 - -Slack : 0.354 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.688 - -Slack : 0.355 -From Node : address[3] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.689 - -Slack : 0.355 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.678 - -Slack : 0.371 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.705 +Clock Skew : 0.029 +Data Delay : 0.509 Slack : 0.378 From Node : counter[16] @@ -7538,86 +7178,446 @@ Relationship : 0.000 Clock Skew : 0.234 Data Delay : 0.699 -Slack : 0.392 +Slack : 0.390 +From Node : A[1] +To Node : A[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.519 + +Slack : 0.395 +From Node : A[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.487 + +Slack : 0.404 +From Node : A[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.496 + +Slack : 0.405 +From Node : A[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.497 + +Slack : 0.413 +From Node : A[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.505 + +Slack : 0.414 +From Node : A[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.506 + +Slack : 0.419 +From Node : A[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : -0.012 +Data Delay : 0.511 + +Slack : 0.444 +From Node : counter[14] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.762 + +Slack : 0.445 +From Node : A[12] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.574 + +Slack : 0.445 +From Node : A[6] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.574 + +Slack : 0.445 +From Node : A[4] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.574 + +Slack : 0.445 +From Node : A[2] +To Node : A[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.574 + +Slack : 0.446 +From Node : counter[6] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.446 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.566 + +Slack : 0.447 +From Node : counter[20] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.576 + +Slack : 0.447 +From Node : counter[2] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.447 +From Node : A[10] +To Node : A[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.576 + +Slack : 0.447 +From Node : counter[4] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.447 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.567 + +Slack : 0.447 +From Node : counter[14] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.567 + +Slack : 0.447 +From Node : counter[14] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.765 + +Slack : 0.449 +From Node : counter[18] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.569 + +Slack : 0.452 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.573 + +Slack : 0.453 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.573 + +Slack : 0.455 +From Node : A[7] +To Node : A[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.584 + +Slack : 0.456 +From Node : A[5] +To Node : A[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.585 + +Slack : 0.456 +From Node : A[3] +To Node : A[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.585 + +Slack : 0.456 +From Node : counter[3] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.577 + +Slack : 0.456 +From Node : counter[1] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.577 + +Slack : 0.457 +From Node : A[11] +To Node : A[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.586 + +Slack : 0.457 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.578 + +Slack : 0.458 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : A[7] +To Node : A[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.587 + +Slack : 0.458 +From Node : counter[0] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.579 + +Slack : 0.459 +From Node : A[5] +To Node : A[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.588 + +Slack : 0.459 +From Node : A[3] +To Node : A[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.588 + +Slack : 0.459 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.580 + +Slack : 0.459 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.580 + +Slack : 0.460 +From Node : A[11] +To Node : A[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.589 + +Slack : 0.460 +From Node : counter[5] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.581 + +Slack : 0.461 +From Node : counter[17] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.461 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.582 + +Slack : 0.463 +From Node : A[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.029 +Data Delay : 0.596 + +Slack : 0.463 +From Node : counter[9] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.584 + +Slack : 0.464 +From Node : counter[11] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.584 + +Slack : 0.464 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.585 + +Slack : 0.464 From Node : counter[15] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.234 -Data Delay : 0.710 +Data Delay : 0.782 -Slack : 0.395 -From Node : counter[15] -To Node : counter[21] +Slack : 0.465 +From Node : A[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.713 +Clock Skew : 0.034 +Data Delay : 0.603 -Slack : 0.414 -From Node : address[10] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Slack : 0.467 +From Node : A[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.219 -Data Delay : 0.737 - -Slack : 0.417 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.739 - -Slack : 0.417 -From Node : address[11] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.744 - -Slack : 0.428 -From Node : address[9] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.755 - -Slack : 0.434 -From Node : address[12] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.223 -Data Delay : 0.761 - -Slack : 0.435 -From Node : address[5] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.230 -Data Delay : 0.769 - -Slack : 0.437 -From Node : address[7] -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.218 -Data Delay : 0.759 +Clock Skew : 0.034 +Data Delay : 0.605 +--------------------------------------------------------------------------------+ @@ -7639,7 +7639,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[0] +Target : A[0] Slack : -1.000 Actual Width : 1.000 @@ -7647,7 +7647,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[10] +Target : A[10] Slack : -1.000 Actual Width : 1.000 @@ -7655,7 +7655,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[11] +Target : A[11] Slack : -1.000 Actual Width : 1.000 @@ -7663,7 +7663,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[12] +Target : A[12] Slack : -1.000 Actual Width : 1.000 @@ -7671,7 +7671,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[13] +Target : A[13] Slack : -1.000 Actual Width : 1.000 @@ -7679,7 +7679,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[1] +Target : A[1] Slack : -1.000 Actual Width : 1.000 @@ -7687,7 +7687,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[2] +Target : A[2] Slack : -1.000 Actual Width : 1.000 @@ -7695,7 +7695,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[3] +Target : A[3] Slack : -1.000 Actual Width : 1.000 @@ -7703,7 +7703,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[4] +Target : A[4] Slack : -1.000 Actual Width : 1.000 @@ -7711,7 +7711,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[5] +Target : A[5] Slack : -1.000 Actual Width : 1.000 @@ -7719,7 +7719,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[6] +Target : A[6] Slack : -1.000 Actual Width : 1.000 @@ -7727,7 +7727,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[7] +Target : A[7] Slack : -1.000 Actual Width : 1.000 @@ -7735,7 +7735,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[8] +Target : A[8] Slack : -1.000 Actual Width : 1.000 @@ -7743,7 +7743,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : address[9] +Target : A[9] Slack : -1.000 Actual Width : 1.000 @@ -7921,6 +7921,166 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~portb_datain_reg0 + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7937,62 +8097,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -8057,46 +8161,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -8161,37 +8225,21 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period +Slack : -0.292 +Actual Width : -0.062 +Required Width : 0.230 +Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_address_reg0 -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period +Slack : -0.292 +Actual Width : -0.062 +Required Width : 0.230 +Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 @@ -8199,7 +8247,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 @@ -8207,15 +8255,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 @@ -8239,31 +8279,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.291 Actual Width : -0.061 @@ -8273,6 +8289,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + Slack : -0.291 Actual Width : -0.061 Required Width : 0.230 @@ -8289,21 +8313,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 -Slack : -0.291 -Actual Width : -0.061 +Slack : -0.290 +Actual Width : -0.060 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : -0.291 -Actual Width : -0.061 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : -0.290 Actual Width : -0.060 @@ -8311,7 +8327,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 @@ -8319,31 +8335,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 @@ -8361,30 +8353,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : -0.290 -Actual Width : -0.060 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - Slack : -0.290 Actual Width : -0.060 Required Width : 0.230 @@ -8399,7 +8367,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -0.290 Actual Width : -0.060 @@ -8417,13 +8385,45 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Slack : -0.290 -Actual Width : -0.060 +Slack : -0.289 +Actual Width : -0.059 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : -0.289 +Actual Width : -0.059 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : -0.289 +Actual Width : -0.059 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : -0.288 +Actual Width : -0.058 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : -0.287 +Actual Width : -0.057 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a0 +--------------------------------------------------------------------------------+ @@ -8433,64 +8433,64 @@ Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_g +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.420 -Fall : 6.381 +Rise : 6.337 +Fall : 6.302 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.683 -Fall : 4.845 +Rise : 4.384 +Fall : 4.484 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.677 -Fall : 4.744 +Rise : 4.664 +Fall : 4.798 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.731 -Fall : 4.868 +Rise : 4.639 +Fall : 4.768 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.431 -Fall : 4.553 +Rise : 4.160 +Fall : 4.243 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.571 -Fall : 4.688 +Rise : 5.127 +Fall : 5.334 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 6.420 -Fall : 6.381 +Rise : 6.337 +Fall : 6.302 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 5.002 -Fall : 5.185 +Rise : 5.006 +Fall : 5.199 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.766 -Fall : 5.661 +Rise : 5.916 +Fall : 5.799 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8502,64 +8502,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.891 +Rise : 4.024 +Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.313 -Fall : 4.443 +Rise : 4.238 +Fall : 4.332 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.345 -Fall : 4.444 +Rise : 4.506 +Fall : 4.633 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.324 -Fall : 4.427 +Rise : 4.483 +Fall : 4.604 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.891 +Rise : 4.024 +Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.100 -Fall : 4.147 +Rise : 4.709 +Fall : 4.829 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 6.088 -Fall : 5.971 +Rise : 5.876 +Fall : 5.767 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 4.510 -Fall : 4.644 +Rise : 4.659 +Fall : 4.810 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.471 -Fall : 5.290 +Rise : 5.589 +Fall : 5.444 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8576,32 +8576,32 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -1.788 -Hold : 0.123 +Setup : -1.812 +Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : CLOCK_50 -Setup : -1.788 -Hold : 0.123 +Setup : -1.812 +Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : Design-wide TNS -Setup : -88.557 +Setup : -85.179 Hold : 0.0 Recovery : 0.0 Removal : 0.0 -Minimum Pulse Width : -110.836 +Minimum Pulse Width : -119.48 Clock : CLOCK_50 -Setup : -88.557 +Setup : -85.179 Hold : 0.000 Recovery : N/A Removal : N/A -Minimum Pulse Width : -110.836 +Minimum Pulse Width : -119.480 +--------------------------------------------------------------------------------+ @@ -8611,64 +8611,64 @@ Minimum Pulse Width : -110.836 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 10.470 -Fall : 10.183 +Rise : 10.303 +Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 8.036 -Fall : 8.004 +Rise : 7.474 +Fall : 7.437 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 7.982 -Fall : 7.929 +Rise : 7.915 +Fall : 7.923 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 8.151 -Fall : 8.115 +Rise : 7.907 +Fall : 7.878 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 7.654 -Fall : 7.638 +Rise : 7.123 +Fall : 7.073 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.866 -Fall : 7.844 +Rise : 8.891 +Fall : 8.893 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 10.470 -Fall : 10.183 +Rise : 10.303 +Fall : 10.097 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 8.654 -Fall : 8.642 +Rise : 8.706 +Fall : 8.626 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 9.306 -Fall : 9.035 +Rise : 9.651 +Fall : 9.302 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8680,64 +8680,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.891 +Rise : 4.024 +Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.313 -Fall : 4.443 +Rise : 4.238 +Fall : 4.332 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.345 -Fall : 4.444 +Rise : 4.506 +Fall : 4.633 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.324 -Fall : 4.427 +Rise : 4.483 +Fall : 4.604 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.891 +Rise : 4.024 +Fall : 4.101 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.100 -Fall : 4.147 +Rise : 4.709 +Fall : 4.829 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 6.088 -Fall : 5.971 +Rise : 5.876 +Fall : 5.767 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 4.510 -Fall : 4.644 +Rise : 4.659 +Fall : 4.810 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.471 -Fall : 5.290 +Rise : 5.589 +Fall : 5.444 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -9779,7 +9779,7 @@ Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 908 +RR Paths : 864 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9793,7 +9793,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 908 +RR Paths : 864 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9838,8 +9838,8 @@ Setup : 8 Hold : 8 Property : Unconstrained Output Port Paths -Setup : 24 -Hold : 24 +Setup : 16 +Hold : 16 +--------------------------------------------------------------------------------+ @@ -9850,7 +9850,7 @@ Hold : 24 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 13:12:24 2022 + Info: Processing started: Wed Mar 30 13:47:20 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -9867,63 +9867,63 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.788 +Info (332146): Worst-case setup slack is -1.812 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.788 -88.557 CLOCK_50 -Info (332146): Worst-case hold slack is 0.260 + Info (332119): -1.812 -85.179 CLOCK_50 +Info (332146): Worst-case hold slack is 0.343 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.260 0.000 CLOCK_50 + Info (332119): 0.343 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -110.836 CLOCK_50 + Info (332119): -3.000 -119.480 CLOCK_50 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.527 +Info (332146): Worst-case setup slack is -1.531 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.527 -72.611 CLOCK_50 -Info (332146): Worst-case hold slack is 0.255 + Info (332119): -1.531 -69.352 CLOCK_50 +Info (332146): Worst-case hold slack is 0.299 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.255 0.000 CLOCK_50 + Info (332119): 0.299 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -110.824 CLOCK_50 + Info (332119): -3.000 -119.478 CLOCK_50 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -0.529 +Info (332146): Worst-case setup slack is -0.444 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.529 -18.538 CLOCK_50 -Info (332146): Worst-case hold slack is 0.123 + Info (332119): -0.444 -17.149 CLOCK_50 +Info (332146): Worst-case hold slack is 0.178 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.123 0.000 CLOCK_50 + Info (332119): 0.178 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -93.684 CLOCK_50 + Info (332119): -3.000 -99.404 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 407 megabytes - Info: Processing ended: Wed Mar 30 13:12:26 2022 + Info: Peak virtual memory: 419 megabytes + Info: Processing ended: Wed Mar 30 13:47:22 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 25a9c18..354a22c 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -1.788 -TNS : -88.557 +Slack : -1.812 +TNS : -85.179 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.260 +Slack : 0.343 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -110.836 +TNS : -119.480 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -1.527 -TNS : -72.611 +Slack : -1.531 +TNS : -69.352 Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.255 +Slack : 0.299 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -110.824 +TNS : -119.478 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -0.529 -TNS : -18.538 +Slack : -0.444 +TNS : -17.149 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.123 +Slack : 0.178 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -93.684 +TNS : -99.404 ------------------------------------------------------------ diff --git a/ram16.qip b/ram16.qip new file mode 100644 index 0000000..ea3a7fc --- /dev/null +++ b/ram16.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram16.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram16_bb.v"] diff --git a/ram16.v b/ram16.v new file mode 100644 index 0000000..2667602 --- /dev/null +++ b/ram16.v @@ -0,0 +1,244 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram16.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram16 ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock), + .wren_a (wren_a), + .address_b (address_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.init_file = "led_patterns.mif", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 16384, + altsyncram_component.numwords_b = 16384, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 14, + altsyncram_component.widthad_b = 14, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/ram16_bb.v b/ram16_bb.v new file mode 100644 index 0000000..68b8fd6 --- /dev/null +++ b/ram16_bb.v @@ -0,0 +1,180 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram16.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module ram16 ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index 87e1f0e..8137f5d 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:12:28" +// DATE "03/30/2022 13:47:24" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -93,7 +93,6 @@ wire \counter[9]~38 ; wire \counter[10]~39_combout ; wire \counter[10]~40 ; wire \counter[11]~41_combout ; -wire \counter[11]~feeder_combout ; wire \counter[11]~42 ; wire \counter[12]~43_combout ; wire \counter[12]~44 ; @@ -110,83 +109,71 @@ wire \counter[17]~54 ; wire \counter[18]~55_combout ; wire \counter[18]~56 ; wire \counter[19]~57_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \counter[19]~58 ; -wire \counter[20]~59_combout ; -wire \counter[20]~60 ; -wire \counter[21]~61_combout ; -wire \Equal0~7_combout ; -wire \address[0]~39_combout ; -wire \address[1]~13_combout ; wire \Equal0~6_combout ; -wire \address[1]~14 ; -wire \address[2]~15_combout ; -wire \address[2]~16 ; -wire \address[3]~17_combout ; -wire \address[3]~18 ; -wire \address[4]~19_combout ; -wire \address[4]~20 ; -wire \address[5]~21_combout ; -wire \address[5]~22 ; -wire \address[6]~23_combout ; -wire \address[6]~24 ; -wire \address[7]~25_combout ; -wire \address[7]~26 ; -wire \address[8]~27_combout ; -wire \address[8]~28 ; -wire \address[9]~29_combout ; -wire \address[9]~30 ; -wire \address[10]~31_combout ; -wire \address[10]~32 ; -wire \address[11]~33_combout ; -wire \address[11]~34 ; -wire \address[12]~35_combout ; -wire \address[12]~36 ; -wire \address[13]~37_combout ; +wire \A[0]~39_combout ; +wire \A[1]~13_combout ; +wire \A[1]~14 ; +wire \A[2]~15_combout ; +wire \A[2]~16 ; +wire \A[3]~17_combout ; +wire \A[3]~18 ; +wire \A[4]~19_combout ; +wire \A[4]~20 ; +wire \A[5]~21_combout ; +wire \A[5]~22 ; +wire \A[6]~23_combout ; +wire \A[6]~24 ; +wire \A[7]~25_combout ; +wire \A[7]~26 ; +wire \A[8]~27_combout ; +wire \A[8]~28 ; +wire \A[9]~29_combout ; +wire \A[9]~30 ; +wire \A[10]~31_combout ; +wire \A[10]~32 ; +wire \A[11]~33_combout ; +wire \A[11]~34 ; +wire \A[12]~35_combout ; +wire \A[12]~36 ; +wire \A[13]~37_combout ; +wire \~GND~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; wire [21:0] counter; -wire [13:0] address; +wire [15:0] A; wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -196,21 +183,13 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bu wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -230,7 +209,7 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -243,7 +222,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -256,7 +235,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,7 +248,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -282,7 +261,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -295,7 +274,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -308,7 +287,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -321,7 +300,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -355,7 +334,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N2 +// Location: LCCOMB_X30_Y14_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -372,7 +351,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N3 +// Location: FF_X30_Y14_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -391,7 +370,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N12 +// Location: LCCOMB_X30_Y14_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -409,7 +388,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N13 +// Location: FF_X30_Y14_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -428,7 +407,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 +// Location: LCCOMB_X30_Y14_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -446,7 +425,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N15 +// Location: FF_X30_Y14_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -465,7 +444,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N16 +// Location: LCCOMB_X30_Y14_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -483,7 +462,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N17 +// Location: FF_X30_Y14_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -502,7 +481,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N18 +// Location: LCCOMB_X30_Y14_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -520,7 +499,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N19 +// Location: FF_X30_Y14_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -539,7 +518,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N20 +// Location: LCCOMB_X30_Y14_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -557,7 +536,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N21 +// Location: FF_X30_Y14_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -576,7 +555,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X30_Y14_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -594,7 +573,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N23 +// Location: FF_X30_Y14_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -613,7 +592,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N24 +// Location: LCCOMB_X30_Y14_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -631,7 +610,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N25 +// Location: FF_X30_Y14_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -650,7 +629,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N26 +// Location: LCCOMB_X30_Y14_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -668,7 +647,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N27 +// Location: FF_X30_Y14_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -687,7 +666,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N28 +// Location: LCCOMB_X30_Y14_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -705,7 +684,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N29 +// Location: FF_X30_Y14_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -724,7 +703,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N30 +// Location: LCCOMB_X30_Y14_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -742,7 +721,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N31 +// Location: FF_X30_Y14_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -761,45 +740,28 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N0 +// Location: LCCOMB_X30_Y13_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) // \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(counter[11]), - .datab(gnd), + .dataa(gnd), + .datab(counter[11]), .datac(gnd), .datad(vcc), .cin(\counter[10]~40 ), .combout(\counter[11]~41_combout ), .cout(\counter[11]~42 )); // synopsys translate_off -defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \counter[11]~feeder ( -// Equation(s): -// \counter[11]~feeder_combout = \counter[11]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\counter[11]~41_combout ), - .cin(gnd), - .combout(\counter[11]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \counter[11]~feeder .lut_mask = 16'hFF00; -defparam \counter[11]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N5 +// Location: FF_X30_Y13_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~feeder_combout ), + .d(\counter[11]~41_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -815,7 +777,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N2 +// Location: LCCOMB_X30_Y13_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -833,7 +795,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N3 +// Location: FF_X30_Y13_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -852,25 +814,25 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N4 +// Location: LCCOMB_X30_Y13_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) // \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) - .dataa(gnd), - .datab(counter[13]), + .dataa(counter[13]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[12]~44 ), .combout(\counter[13]~45_combout ), .cout(\counter[13]~46 )); // synopsys translate_off -defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N5 +// Location: FF_X30_Y13_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -889,7 +851,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N6 +// Location: LCCOMB_X30_Y13_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -907,7 +869,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N7 +// Location: FF_X30_Y13_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -926,25 +888,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N8 +// Location: LCCOMB_X30_Y13_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(gnd), - .datab(counter[15]), + .dataa(counter[15]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .lut_mask = 16'hA50A; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N9 +// Location: FF_X30_Y13_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -963,7 +925,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N10 +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -981,7 +943,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N11 +// Location: FF_X30_Y13_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -1000,7 +962,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N12 +// Location: LCCOMB_X30_Y13_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -1018,7 +980,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N13 +// Location: FF_X30_Y13_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -1037,7 +999,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N14 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1055,7 +1017,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N15 +// Location: FF_X30_Y13_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1074,7 +1036,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N16 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1092,7 +1054,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N17 +// Location: FF_X30_Y13_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1111,109 +1073,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N28 -cycloneive_lcell_comb \Equal0~5 ( -// Equation(s): -// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - - .dataa(counter[17]), - .datab(counter[19]), - .datac(counter[18]), - .datad(counter[16]), - .cin(gnd), - .combout(\Equal0~5_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~5 .lut_mask = 16'h0001; -defparam \Equal0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \Equal0~0 ( -// Equation(s): -// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(counter[2]), - .datad(counter[3]), - .cin(gnd), - .combout(\Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~0 .lut_mask = 16'h0001; -defparam \Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) - - .dataa(counter[6]), - .datab(counter[7]), - .datac(counter[5]), - .datad(counter[4]), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \Equal0~2 ( -// Equation(s): -// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - - .dataa(counter[8]), - .datab(counter[11]), - .datac(counter[10]), - .datad(counter[9]), - .cin(gnd), - .combout(\Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~2 .lut_mask = 16'h0001; -defparam \Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \Equal0~3 ( -// Equation(s): -// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - - .dataa(counter[14]), - .datab(counter[13]), - .datac(counter[15]), - .datad(counter[12]), - .cin(gnd), - .combout(\Equal0~3_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~3 .lut_mask = 16'h0001; -defparam \Equal0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \Equal0~4 ( -// Equation(s): -// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - - .dataa(\Equal0~0_combout ), - .datab(\Equal0~1_combout ), - .datac(\Equal0~2_combout ), - .datad(\Equal0~3_combout ), - .cin(gnd), - .combout(\Equal0~4_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~4 .lut_mask = 16'h8000; -defparam \Equal0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 +// Location: LCCOMB_X30_Y13_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1231,7 +1091,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N19 +// Location: FF_X30_Y13_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1250,7 +1110,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N20 +// Location: LCCOMB_X30_Y13_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1267,7 +1127,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N21 +// Location: FF_X30_Y13_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1286,78 +1146,109 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \Equal0~7 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~7_combout = (!counter[21] & !counter[20]) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(counter[20]), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), - .combout(\Equal0~7_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h000F; -defparam \Equal0~7 .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \address[0]~39 ( +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Equal0~5_combout ), - .datab(\Equal0~4_combout ), - .datac(address[0]), - .datad(\Equal0~7_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), - .combout(\address[0]~39_combout ), + .combout(\Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \address[0]~39 .lut_mask = 16'h78F0; -defparam \address[0]~39 .sum_lutc_input = "datac"; +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N31 -dffeas \address[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(address[0]), - .prn(vcc)); -// synopsys translate_off -defparam \address[0] .is_wysiwyg = "true"; -defparam \address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \address[1]~13 ( +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) -// \address[1]~14 = CARRY((address[0] & address[1])) +// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) - .dataa(address[0]), - .datab(address[1]), - .datac(gnd), - .datad(vcc), + .dataa(counter[6]), + .datab(counter[4]), + .datac(counter[7]), + .datad(counter[5]), .cin(gnd), - .combout(\address[1]~13_combout ), - .cout(\address[1]~14 )); + .combout(\Equal0~1_combout ), + .cout()); // synopsys translate_off -defparam \address[1]~13 .lut_mask = 16'h6688; -defparam \address[1]~13 .sum_lutc_input = "datac"; +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N26 +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) + + .dataa(counter[10]), + .datab(counter[9]), + .datac(counter[8]), + .datad(counter[11]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) + + .dataa(counter[14]), + .datab(counter[15]), + .datac(counter[13]), + .datad(counter[12]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): // \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) @@ -1374,489 +1265,27 @@ defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \address[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~13_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[1]), - .prn(vcc)); -// synopsys translate_off -defparam \address[1] .is_wysiwyg = "true"; -defparam \address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \address[2]~15 ( +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \A[0]~39 ( // Equation(s): -// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) -// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) - - .dataa(gnd), - .datab(address[2]), - .datac(gnd), - .datad(vcc), - .cin(\address[1]~14 ), - .combout(\address[2]~15_combout ), - .cout(\address[2]~16 )); -// synopsys translate_off -defparam \address[2]~15 .lut_mask = 16'h3C3F; -defparam \address[2]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N3 -dffeas \address[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[2]), - .prn(vcc)); -// synopsys translate_off -defparam \address[2] .is_wysiwyg = "true"; -defparam \address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \address[3]~17 ( -// Equation(s): -// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) -// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) - - .dataa(gnd), - .datab(address[3]), - .datac(gnd), - .datad(vcc), - .cin(\address[2]~16 ), - .combout(\address[3]~17_combout ), - .cout(\address[3]~18 )); -// synopsys translate_off -defparam \address[3]~17 .lut_mask = 16'hC30C; -defparam \address[3]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N5 -dffeas \address[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[3]~17_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[3]), - .prn(vcc)); -// synopsys translate_off -defparam \address[3] .is_wysiwyg = "true"; -defparam \address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \address[4]~19 ( -// Equation(s): -// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) -// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) - - .dataa(address[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[3]~18 ), - .combout(\address[4]~19_combout ), - .cout(\address[4]~20 )); -// synopsys translate_off -defparam \address[4]~19 .lut_mask = 16'h5A5F; -defparam \address[4]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N7 -dffeas \address[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[4]~19_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[4]), - .prn(vcc)); -// synopsys translate_off -defparam \address[4] .is_wysiwyg = "true"; -defparam \address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \address[5]~21 ( -// Equation(s): -// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) -// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) - - .dataa(gnd), - .datab(address[5]), - .datac(gnd), - .datad(vcc), - .cin(\address[4]~20 ), - .combout(\address[5]~21_combout ), - .cout(\address[5]~22 )); -// synopsys translate_off -defparam \address[5]~21 .lut_mask = 16'hC30C; -defparam \address[5]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \address[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[5]), - .prn(vcc)); -// synopsys translate_off -defparam \address[5] .is_wysiwyg = "true"; -defparam \address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \address[6]~23 ( -// Equation(s): -// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) -// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) - - .dataa(address[6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[5]~22 ), - .combout(\address[6]~23_combout ), - .cout(\address[6]~24 )); -// synopsys translate_off -defparam \address[6]~23 .lut_mask = 16'h5A5F; -defparam \address[6]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \address[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[6]~23_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[6]), - .prn(vcc)); -// synopsys translate_off -defparam \address[6] .is_wysiwyg = "true"; -defparam \address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \address[7]~25 ( -// Equation(s): -// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) -// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) - - .dataa(address[7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[6]~24 ), - .combout(\address[7]~25_combout ), - .cout(\address[7]~26 )); -// synopsys translate_off -defparam \address[7]~25 .lut_mask = 16'hA50A; -defparam \address[7]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N13 -dffeas \address[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[7]~25_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[7]), - .prn(vcc)); -// synopsys translate_off -defparam \address[7] .is_wysiwyg = "true"; -defparam \address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \address[8]~27 ( -// Equation(s): -// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) -// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) - - .dataa(gnd), - .datab(address[8]), - .datac(gnd), - .datad(vcc), - .cin(\address[7]~26 ), - .combout(\address[8]~27_combout ), - .cout(\address[8]~28 )); -// synopsys translate_off -defparam \address[8]~27 .lut_mask = 16'h3C3F; -defparam \address[8]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \address[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[8]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[8]), - .prn(vcc)); -// synopsys translate_off -defparam \address[8] .is_wysiwyg = "true"; -defparam \address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \address[9]~29 ( -// Equation(s): -// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) -// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) - - .dataa(gnd), - .datab(address[9]), - .datac(gnd), - .datad(vcc), - .cin(\address[8]~28 ), - .combout(\address[9]~29_combout ), - .cout(\address[9]~30 )); -// synopsys translate_off -defparam \address[9]~29 .lut_mask = 16'hC30C; -defparam \address[9]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \address[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[9]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[9]), - .prn(vcc)); -// synopsys translate_off -defparam \address[9] .is_wysiwyg = "true"; -defparam \address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \address[10]~31 ( -// Equation(s): -// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) -// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) - - .dataa(gnd), - .datab(address[10]), - .datac(gnd), - .datad(vcc), - .cin(\address[9]~30 ), - .combout(\address[10]~31_combout ), - .cout(\address[10]~32 )); -// synopsys translate_off -defparam \address[10]~31 .lut_mask = 16'h3C3F; -defparam \address[10]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N19 -dffeas \address[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[10]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[10]), - .prn(vcc)); -// synopsys translate_off -defparam \address[10] .is_wysiwyg = "true"; -defparam \address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \address[11]~33 ( -// Equation(s): -// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) -// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) - - .dataa(gnd), - .datab(address[11]), - .datac(gnd), - .datad(vcc), - .cin(\address[10]~32 ), - .combout(\address[11]~33_combout ), - .cout(\address[11]~34 )); -// synopsys translate_off -defparam \address[11]~33 .lut_mask = 16'hC30C; -defparam \address[11]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N21 -dffeas \address[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[11]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[11]), - .prn(vcc)); -// synopsys translate_off -defparam \address[11] .is_wysiwyg = "true"; -defparam \address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \address[12]~35 ( -// Equation(s): -// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) -// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) - - .dataa(address[12]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[11]~34 ), - .combout(\address[12]~35_combout ), - .cout(\address[12]~36 )); -// synopsys translate_off -defparam \address[12]~35 .lut_mask = 16'h5A5F; -defparam \address[12]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \address[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[12]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[12]), - .prn(vcc)); -// synopsys translate_off -defparam \address[12] .is_wysiwyg = "true"; -defparam \address[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \address[13]~37 ( -// Equation(s): -// \address[13]~37_combout = \address[12]~36 $ (!address[13]) +// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(address[13]), - .cin(\address[12]~36 ), - .combout(\address[13]~37_combout ), - .cout()); -// synopsys translate_off -defparam \address[13]~37 .lut_mask = 16'hF00F; -defparam \address[13]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N25 -dffeas \address[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[13]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[13]), - .prn(vcc)); -// synopsys translate_off -defparam \address[13] .is_wysiwyg = "true"; -defparam \address[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(address[13]), + .datac(A[0]), + .datad(\Equal0~6_combout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .combout(\A[0]~39_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[0]~39 .lut_mask = 16'h0FF0; +defparam \A[0]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( +// Location: FF_X30_Y14_N1 +dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .d(\A[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1865,626 +1294,787 @@ dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .q(A[0]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \A[0] .is_wysiwyg = "true"; +defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y18_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \A[1]~13 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~14 = CARRY((A[1] & A[0])) - .dataa(gnd), - .datab(gnd), + .dataa(A[1]), + .datab(A[0]), .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(vcc), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); + .combout(\A[1]~13_combout ), + .cout(\A[1]~14 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[1]~13 .lut_mask = 16'h6688; +defparam \A[1]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N25 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X29_Y14_N1 +dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\A[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(A[1]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \A[1] .is_wysiwyg = "true"; +defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \A[2]~15 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) +// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) +// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), - .cout()); + .datab(A[2]), + .datac(gnd), + .datad(vcc), + .cin(\A[1]~14 ), + .combout(\A[2]~15_combout ), + .cout(\A[2]~16 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +defparam \A[2]~15 .lut_mask = 16'h3C3F; +defparam \A[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X29_Y14_N3 +dffeas \A[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[2]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(A[2]), + .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +defparam \A[2] .is_wysiwyg = "true"; +defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \A[3]~17 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) +// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) +// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .dataa(gnd), + .datab(A[3]), + .datac(gnd), + .datad(vcc), + .cin(\A[2]~16 ), + .combout(\A[3]~17_combout ), + .cout(\A[3]~18 )); +// synopsys translate_off +defparam \A[3]~17 .lut_mask = 16'hC30C; +defparam \A[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \A[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[3]), + .prn(vcc)); +// synopsys translate_off +defparam \A[3] .is_wysiwyg = "true"; +defparam \A[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \A[4]~19 ( +// Equation(s): +// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) +// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) + + .dataa(A[4]), .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(\A[3]~18 ), + .combout(\A[4]~19_combout ), + .cout(\A[4]~20 )); +// synopsys translate_off +defparam \A[4]~19 .lut_mask = 16'h5A5F; +defparam \A[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \A[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[4]), + .prn(vcc)); +// synopsys translate_off +defparam \A[4] .is_wysiwyg = "true"; +defparam \A[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \A[5]~21 ( +// Equation(s): +// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) +// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) + + .dataa(gnd), + .datab(A[5]), + .datac(gnd), + .datad(vcc), + .cin(\A[4]~20 ), + .combout(\A[5]~21_combout ), + .cout(\A[5]~22 )); +// synopsys translate_off +defparam \A[5]~21 .lut_mask = 16'hC30C; +defparam \A[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \A[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[5]), + .prn(vcc)); +// synopsys translate_off +defparam \A[5] .is_wysiwyg = "true"; +defparam \A[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \A[6]~23 ( +// Equation(s): +// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) +// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) + + .dataa(A[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[5]~22 ), + .combout(\A[6]~23_combout ), + .cout(\A[6]~24 )); +// synopsys translate_off +defparam \A[6]~23 .lut_mask = 16'h5A5F; +defparam \A[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \A[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[6]), + .prn(vcc)); +// synopsys translate_off +defparam \A[6] .is_wysiwyg = "true"; +defparam \A[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \A[7]~25 ( +// Equation(s): +// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) +// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) + + .dataa(A[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[6]~24 ), + .combout(\A[7]~25_combout ), + .cout(\A[7]~26 )); +// synopsys translate_off +defparam \A[7]~25 .lut_mask = 16'hA50A; +defparam \A[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \A[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[7]), + .prn(vcc)); +// synopsys translate_off +defparam \A[7] .is_wysiwyg = "true"; +defparam \A[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \A[8]~27 ( +// Equation(s): +// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) +// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) + + .dataa(A[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[7]~26 ), + .combout(\A[8]~27_combout ), + .cout(\A[8]~28 )); +// synopsys translate_off +defparam \A[8]~27 .lut_mask = 16'h5A5F; +defparam \A[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N15 +dffeas \A[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[8]), + .prn(vcc)); +// synopsys translate_off +defparam \A[8] .is_wysiwyg = "true"; +defparam \A[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \A[9]~29 ( +// Equation(s): +// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) +// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) + + .dataa(gnd), + .datab(A[9]), + .datac(gnd), + .datad(vcc), + .cin(\A[8]~28 ), + .combout(\A[9]~29_combout ), + .cout(\A[9]~30 )); +// synopsys translate_off +defparam \A[9]~29 .lut_mask = 16'hC30C; +defparam \A[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \A[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[9]), + .prn(vcc)); +// synopsys translate_off +defparam \A[9] .is_wysiwyg = "true"; +defparam \A[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \A[10]~31 ( +// Equation(s): +// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) +// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) + + .dataa(gnd), + .datab(A[10]), + .datac(gnd), + .datad(vcc), + .cin(\A[9]~30 ), + .combout(\A[10]~31_combout ), + .cout(\A[10]~32 )); +// synopsys translate_off +defparam \A[10]~31 .lut_mask = 16'h3C3F; +defparam \A[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \A[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[10]), + .prn(vcc)); +// synopsys translate_off +defparam \A[10] .is_wysiwyg = "true"; +defparam \A[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \A[11]~33 ( +// Equation(s): +// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) +// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) + + .dataa(gnd), + .datab(A[11]), + .datac(gnd), + .datad(vcc), + .cin(\A[10]~32 ), + .combout(\A[11]~33_combout ), + .cout(\A[11]~34 )); +// synopsys translate_off +defparam \A[11]~33 .lut_mask = 16'hC30C; +defparam \A[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \A[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[11]), + .prn(vcc)); +// synopsys translate_off +defparam \A[11] .is_wysiwyg = "true"; +defparam \A[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \A[12]~35 ( +// Equation(s): +// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) +// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) + + .dataa(A[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[11]~34 ), + .combout(\A[12]~35_combout ), + .cout(\A[12]~36 )); +// synopsys translate_off +defparam \A[12]~35 .lut_mask = 16'h5A5F; +defparam \A[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \A[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[12]), + .prn(vcc)); +// synopsys translate_off +defparam \A[12] .is_wysiwyg = "true"; +defparam \A[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \A[13]~37 ( +// Equation(s): +// \A[13]~37_combout = \A[12]~36 $ (!A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[13]), + .cin(\A[12]~36 ), + .combout(\A[13]~37_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +defparam \A[13]~37 .lut_mask = 16'hF00F; +defparam \A[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \A[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[13]), + .prn(vcc)); +// synopsys translate_off +defparam \A[13] .is_wysiwyg = "true"; +defparam \A[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 +// Location: M9K_X22_Y13_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -2494,14 +2084,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2540,25 +2130,153 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X23_Y18_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), - .cout()); +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2568,14 +2286,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2614,7 +2332,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X22_Y11_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2624,14 +2342,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2670,81 +2388,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(gnd), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2754,14 +2416,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2800,26 +2462,8 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: LCCOMB_X32_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2828,53 +2472,71 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(vcc), .portare(vcc), @@ -2884,14 +2546,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2930,22 +2592,78 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N12 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index 681ffbf..859d091 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:12:28" +// DATE "03/30/2022 13:47:24" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -93,7 +93,6 @@ wire \counter[9]~38 ; wire \counter[10]~39_combout ; wire \counter[10]~40 ; wire \counter[11]~41_combout ; -wire \counter[11]~feeder_combout ; wire \counter[11]~42 ; wire \counter[12]~43_combout ; wire \counter[12]~44 ; @@ -110,83 +109,71 @@ wire \counter[17]~54 ; wire \counter[18]~55_combout ; wire \counter[18]~56 ; wire \counter[19]~57_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \counter[19]~58 ; -wire \counter[20]~59_combout ; -wire \counter[20]~60 ; -wire \counter[21]~61_combout ; -wire \Equal0~7_combout ; -wire \address[0]~39_combout ; -wire \address[1]~13_combout ; wire \Equal0~6_combout ; -wire \address[1]~14 ; -wire \address[2]~15_combout ; -wire \address[2]~16 ; -wire \address[3]~17_combout ; -wire \address[3]~18 ; -wire \address[4]~19_combout ; -wire \address[4]~20 ; -wire \address[5]~21_combout ; -wire \address[5]~22 ; -wire \address[6]~23_combout ; -wire \address[6]~24 ; -wire \address[7]~25_combout ; -wire \address[7]~26 ; -wire \address[8]~27_combout ; -wire \address[8]~28 ; -wire \address[9]~29_combout ; -wire \address[9]~30 ; -wire \address[10]~31_combout ; -wire \address[10]~32 ; -wire \address[11]~33_combout ; -wire \address[11]~34 ; -wire \address[12]~35_combout ; -wire \address[12]~36 ; -wire \address[13]~37_combout ; +wire \A[0]~39_combout ; +wire \A[1]~13_combout ; +wire \A[1]~14 ; +wire \A[2]~15_combout ; +wire \A[2]~16 ; +wire \A[3]~17_combout ; +wire \A[3]~18 ; +wire \A[4]~19_combout ; +wire \A[4]~20 ; +wire \A[5]~21_combout ; +wire \A[5]~22 ; +wire \A[6]~23_combout ; +wire \A[6]~24 ; +wire \A[7]~25_combout ; +wire \A[7]~26 ; +wire \A[8]~27_combout ; +wire \A[8]~28 ; +wire \A[9]~29_combout ; +wire \A[9]~30 ; +wire \A[10]~31_combout ; +wire \A[10]~32 ; +wire \A[11]~33_combout ; +wire \A[11]~34 ; +wire \A[12]~35_combout ; +wire \A[12]~36 ; +wire \A[13]~37_combout ; +wire \~GND~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; wire [21:0] counter; -wire [13:0] address; +wire [15:0] A; wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -196,21 +183,13 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bu wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -230,7 +209,7 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -243,7 +222,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -256,7 +235,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,7 +248,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -282,7 +261,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -295,7 +274,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -308,7 +287,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -321,7 +300,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -355,7 +334,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N2 +// Location: LCCOMB_X30_Y14_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -372,7 +351,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N3 +// Location: FF_X30_Y14_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -391,7 +370,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N12 +// Location: LCCOMB_X30_Y14_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -409,7 +388,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N13 +// Location: FF_X30_Y14_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -428,7 +407,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 +// Location: LCCOMB_X30_Y14_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -446,7 +425,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N15 +// Location: FF_X30_Y14_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -465,7 +444,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N16 +// Location: LCCOMB_X30_Y14_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -483,7 +462,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N17 +// Location: FF_X30_Y14_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -502,7 +481,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N18 +// Location: LCCOMB_X30_Y14_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -520,7 +499,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N19 +// Location: FF_X30_Y14_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -539,7 +518,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N20 +// Location: LCCOMB_X30_Y14_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -557,7 +536,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N21 +// Location: FF_X30_Y14_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -576,7 +555,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X30_Y14_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -594,7 +573,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N23 +// Location: FF_X30_Y14_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -613,7 +592,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N24 +// Location: LCCOMB_X30_Y14_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -631,7 +610,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N25 +// Location: FF_X30_Y14_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -650,7 +629,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N26 +// Location: LCCOMB_X30_Y14_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -668,7 +647,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N27 +// Location: FF_X30_Y14_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -687,7 +666,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N28 +// Location: LCCOMB_X30_Y14_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -705,7 +684,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N29 +// Location: FF_X30_Y14_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -724,7 +703,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N30 +// Location: LCCOMB_X30_Y14_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -742,7 +721,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N31 +// Location: FF_X30_Y14_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -761,45 +740,28 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N0 +// Location: LCCOMB_X30_Y13_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) // \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(counter[11]), - .datab(gnd), + .dataa(gnd), + .datab(counter[11]), .datac(gnd), .datad(vcc), .cin(\counter[10]~40 ), .combout(\counter[11]~41_combout ), .cout(\counter[11]~42 )); // synopsys translate_off -defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \counter[11]~feeder ( -// Equation(s): -// \counter[11]~feeder_combout = \counter[11]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\counter[11]~41_combout ), - .cin(gnd), - .combout(\counter[11]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \counter[11]~feeder .lut_mask = 16'hFF00; -defparam \counter[11]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N5 +// Location: FF_X30_Y13_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~feeder_combout ), + .d(\counter[11]~41_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -815,7 +777,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N2 +// Location: LCCOMB_X30_Y13_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -833,7 +795,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N3 +// Location: FF_X30_Y13_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -852,25 +814,25 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N4 +// Location: LCCOMB_X30_Y13_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) // \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) - .dataa(gnd), - .datab(counter[13]), + .dataa(counter[13]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[12]~44 ), .combout(\counter[13]~45_combout ), .cout(\counter[13]~46 )); // synopsys translate_off -defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N5 +// Location: FF_X30_Y13_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -889,7 +851,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N6 +// Location: LCCOMB_X30_Y13_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -907,7 +869,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N7 +// Location: FF_X30_Y13_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -926,25 +888,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N8 +// Location: LCCOMB_X30_Y13_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(gnd), - .datab(counter[15]), + .dataa(counter[15]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .lut_mask = 16'hA50A; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N9 +// Location: FF_X30_Y13_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -963,7 +925,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N10 +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -981,7 +943,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N11 +// Location: FF_X30_Y13_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -1000,7 +962,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N12 +// Location: LCCOMB_X30_Y13_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -1018,7 +980,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N13 +// Location: FF_X30_Y13_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -1037,7 +999,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N14 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1055,7 +1017,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N15 +// Location: FF_X30_Y13_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1074,7 +1036,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N16 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1092,7 +1054,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N17 +// Location: FF_X30_Y13_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1111,109 +1073,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N28 -cycloneive_lcell_comb \Equal0~5 ( -// Equation(s): -// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - - .dataa(counter[17]), - .datab(counter[19]), - .datac(counter[18]), - .datad(counter[16]), - .cin(gnd), - .combout(\Equal0~5_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~5 .lut_mask = 16'h0001; -defparam \Equal0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \Equal0~0 ( -// Equation(s): -// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(counter[2]), - .datad(counter[3]), - .cin(gnd), - .combout(\Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~0 .lut_mask = 16'h0001; -defparam \Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) - - .dataa(counter[6]), - .datab(counter[7]), - .datac(counter[5]), - .datad(counter[4]), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \Equal0~2 ( -// Equation(s): -// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - - .dataa(counter[8]), - .datab(counter[11]), - .datac(counter[10]), - .datad(counter[9]), - .cin(gnd), - .combout(\Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~2 .lut_mask = 16'h0001; -defparam \Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \Equal0~3 ( -// Equation(s): -// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - - .dataa(counter[14]), - .datab(counter[13]), - .datac(counter[15]), - .datad(counter[12]), - .cin(gnd), - .combout(\Equal0~3_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~3 .lut_mask = 16'h0001; -defparam \Equal0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \Equal0~4 ( -// Equation(s): -// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - - .dataa(\Equal0~0_combout ), - .datab(\Equal0~1_combout ), - .datac(\Equal0~2_combout ), - .datad(\Equal0~3_combout ), - .cin(gnd), - .combout(\Equal0~4_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~4 .lut_mask = 16'h8000; -defparam \Equal0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 +// Location: LCCOMB_X30_Y13_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1231,7 +1091,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N19 +// Location: FF_X30_Y13_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1250,7 +1110,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N20 +// Location: LCCOMB_X30_Y13_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1267,7 +1127,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N21 +// Location: FF_X30_Y13_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1286,78 +1146,109 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \Equal0~7 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~7_combout = (!counter[21] & !counter[20]) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(counter[20]), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), - .combout(\Equal0~7_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h000F; -defparam \Equal0~7 .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \address[0]~39 ( +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Equal0~5_combout ), - .datab(\Equal0~4_combout ), - .datac(address[0]), - .datad(\Equal0~7_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), - .combout(\address[0]~39_combout ), + .combout(\Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \address[0]~39 .lut_mask = 16'h78F0; -defparam \address[0]~39 .sum_lutc_input = "datac"; +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N31 -dffeas \address[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(address[0]), - .prn(vcc)); -// synopsys translate_off -defparam \address[0] .is_wysiwyg = "true"; -defparam \address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \address[1]~13 ( +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) -// \address[1]~14 = CARRY((address[0] & address[1])) +// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) - .dataa(address[0]), - .datab(address[1]), - .datac(gnd), - .datad(vcc), + .dataa(counter[6]), + .datab(counter[4]), + .datac(counter[7]), + .datad(counter[5]), .cin(gnd), - .combout(\address[1]~13_combout ), - .cout(\address[1]~14 )); + .combout(\Equal0~1_combout ), + .cout()); // synopsys translate_off -defparam \address[1]~13 .lut_mask = 16'h6688; -defparam \address[1]~13 .sum_lutc_input = "datac"; +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N26 +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) + + .dataa(counter[10]), + .datab(counter[9]), + .datac(counter[8]), + .datad(counter[11]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) + + .dataa(counter[14]), + .datab(counter[15]), + .datac(counter[13]), + .datad(counter[12]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): // \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) @@ -1374,489 +1265,27 @@ defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \address[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~13_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[1]), - .prn(vcc)); -// synopsys translate_off -defparam \address[1] .is_wysiwyg = "true"; -defparam \address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \address[2]~15 ( +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \A[0]~39 ( // Equation(s): -// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) -// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) - - .dataa(gnd), - .datab(address[2]), - .datac(gnd), - .datad(vcc), - .cin(\address[1]~14 ), - .combout(\address[2]~15_combout ), - .cout(\address[2]~16 )); -// synopsys translate_off -defparam \address[2]~15 .lut_mask = 16'h3C3F; -defparam \address[2]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N3 -dffeas \address[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[2]), - .prn(vcc)); -// synopsys translate_off -defparam \address[2] .is_wysiwyg = "true"; -defparam \address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \address[3]~17 ( -// Equation(s): -// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) -// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) - - .dataa(gnd), - .datab(address[3]), - .datac(gnd), - .datad(vcc), - .cin(\address[2]~16 ), - .combout(\address[3]~17_combout ), - .cout(\address[3]~18 )); -// synopsys translate_off -defparam \address[3]~17 .lut_mask = 16'hC30C; -defparam \address[3]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N5 -dffeas \address[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[3]~17_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[3]), - .prn(vcc)); -// synopsys translate_off -defparam \address[3] .is_wysiwyg = "true"; -defparam \address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \address[4]~19 ( -// Equation(s): -// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) -// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) - - .dataa(address[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[3]~18 ), - .combout(\address[4]~19_combout ), - .cout(\address[4]~20 )); -// synopsys translate_off -defparam \address[4]~19 .lut_mask = 16'h5A5F; -defparam \address[4]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N7 -dffeas \address[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[4]~19_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[4]), - .prn(vcc)); -// synopsys translate_off -defparam \address[4] .is_wysiwyg = "true"; -defparam \address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \address[5]~21 ( -// Equation(s): -// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) -// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) - - .dataa(gnd), - .datab(address[5]), - .datac(gnd), - .datad(vcc), - .cin(\address[4]~20 ), - .combout(\address[5]~21_combout ), - .cout(\address[5]~22 )); -// synopsys translate_off -defparam \address[5]~21 .lut_mask = 16'hC30C; -defparam \address[5]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \address[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[5]), - .prn(vcc)); -// synopsys translate_off -defparam \address[5] .is_wysiwyg = "true"; -defparam \address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \address[6]~23 ( -// Equation(s): -// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) -// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) - - .dataa(address[6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[5]~22 ), - .combout(\address[6]~23_combout ), - .cout(\address[6]~24 )); -// synopsys translate_off -defparam \address[6]~23 .lut_mask = 16'h5A5F; -defparam \address[6]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \address[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[6]~23_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[6]), - .prn(vcc)); -// synopsys translate_off -defparam \address[6] .is_wysiwyg = "true"; -defparam \address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \address[7]~25 ( -// Equation(s): -// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) -// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) - - .dataa(address[7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[6]~24 ), - .combout(\address[7]~25_combout ), - .cout(\address[7]~26 )); -// synopsys translate_off -defparam \address[7]~25 .lut_mask = 16'hA50A; -defparam \address[7]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N13 -dffeas \address[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[7]~25_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[7]), - .prn(vcc)); -// synopsys translate_off -defparam \address[7] .is_wysiwyg = "true"; -defparam \address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \address[8]~27 ( -// Equation(s): -// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) -// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) - - .dataa(gnd), - .datab(address[8]), - .datac(gnd), - .datad(vcc), - .cin(\address[7]~26 ), - .combout(\address[8]~27_combout ), - .cout(\address[8]~28 )); -// synopsys translate_off -defparam \address[8]~27 .lut_mask = 16'h3C3F; -defparam \address[8]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \address[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[8]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[8]), - .prn(vcc)); -// synopsys translate_off -defparam \address[8] .is_wysiwyg = "true"; -defparam \address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \address[9]~29 ( -// Equation(s): -// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) -// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) - - .dataa(gnd), - .datab(address[9]), - .datac(gnd), - .datad(vcc), - .cin(\address[8]~28 ), - .combout(\address[9]~29_combout ), - .cout(\address[9]~30 )); -// synopsys translate_off -defparam \address[9]~29 .lut_mask = 16'hC30C; -defparam \address[9]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \address[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[9]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[9]), - .prn(vcc)); -// synopsys translate_off -defparam \address[9] .is_wysiwyg = "true"; -defparam \address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \address[10]~31 ( -// Equation(s): -// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) -// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) - - .dataa(gnd), - .datab(address[10]), - .datac(gnd), - .datad(vcc), - .cin(\address[9]~30 ), - .combout(\address[10]~31_combout ), - .cout(\address[10]~32 )); -// synopsys translate_off -defparam \address[10]~31 .lut_mask = 16'h3C3F; -defparam \address[10]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N19 -dffeas \address[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[10]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[10]), - .prn(vcc)); -// synopsys translate_off -defparam \address[10] .is_wysiwyg = "true"; -defparam \address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \address[11]~33 ( -// Equation(s): -// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) -// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) - - .dataa(gnd), - .datab(address[11]), - .datac(gnd), - .datad(vcc), - .cin(\address[10]~32 ), - .combout(\address[11]~33_combout ), - .cout(\address[11]~34 )); -// synopsys translate_off -defparam \address[11]~33 .lut_mask = 16'hC30C; -defparam \address[11]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N21 -dffeas \address[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[11]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[11]), - .prn(vcc)); -// synopsys translate_off -defparam \address[11] .is_wysiwyg = "true"; -defparam \address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \address[12]~35 ( -// Equation(s): -// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) -// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) - - .dataa(address[12]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[11]~34 ), - .combout(\address[12]~35_combout ), - .cout(\address[12]~36 )); -// synopsys translate_off -defparam \address[12]~35 .lut_mask = 16'h5A5F; -defparam \address[12]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \address[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[12]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[12]), - .prn(vcc)); -// synopsys translate_off -defparam \address[12] .is_wysiwyg = "true"; -defparam \address[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \address[13]~37 ( -// Equation(s): -// \address[13]~37_combout = \address[12]~36 $ (!address[13]) +// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(address[13]), - .cin(\address[12]~36 ), - .combout(\address[13]~37_combout ), - .cout()); -// synopsys translate_off -defparam \address[13]~37 .lut_mask = 16'hF00F; -defparam \address[13]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N25 -dffeas \address[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[13]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[13]), - .prn(vcc)); -// synopsys translate_off -defparam \address[13] .is_wysiwyg = "true"; -defparam \address[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(address[13]), + .datac(A[0]), + .datad(\Equal0~6_combout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .combout(\A[0]~39_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[0]~39 .lut_mask = 16'h0FF0; +defparam \A[0]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( +// Location: FF_X30_Y14_N1 +dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .d(\A[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1865,626 +1294,787 @@ dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .q(A[0]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \A[0] .is_wysiwyg = "true"; +defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y18_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \A[1]~13 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~14 = CARRY((A[1] & A[0])) - .dataa(gnd), - .datab(gnd), + .dataa(A[1]), + .datab(A[0]), .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(vcc), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); + .combout(\A[1]~13_combout ), + .cout(\A[1]~14 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[1]~13 .lut_mask = 16'h6688; +defparam \A[1]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N25 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X29_Y14_N1 +dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\A[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(A[1]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \A[1] .is_wysiwyg = "true"; +defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \A[2]~15 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) +// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) +// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), - .cout()); + .datab(A[2]), + .datac(gnd), + .datad(vcc), + .cin(\A[1]~14 ), + .combout(\A[2]~15_combout ), + .cout(\A[2]~16 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +defparam \A[2]~15 .lut_mask = 16'h3C3F; +defparam \A[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X29_Y14_N3 +dffeas \A[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[2]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(A[2]), + .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +defparam \A[2] .is_wysiwyg = "true"; +defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \A[3]~17 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) +// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) +// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .dataa(gnd), + .datab(A[3]), + .datac(gnd), + .datad(vcc), + .cin(\A[2]~16 ), + .combout(\A[3]~17_combout ), + .cout(\A[3]~18 )); +// synopsys translate_off +defparam \A[3]~17 .lut_mask = 16'hC30C; +defparam \A[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \A[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[3]), + .prn(vcc)); +// synopsys translate_off +defparam \A[3] .is_wysiwyg = "true"; +defparam \A[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \A[4]~19 ( +// Equation(s): +// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) +// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) + + .dataa(A[4]), .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(\A[3]~18 ), + .combout(\A[4]~19_combout ), + .cout(\A[4]~20 )); +// synopsys translate_off +defparam \A[4]~19 .lut_mask = 16'h5A5F; +defparam \A[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \A[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[4]), + .prn(vcc)); +// synopsys translate_off +defparam \A[4] .is_wysiwyg = "true"; +defparam \A[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \A[5]~21 ( +// Equation(s): +// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) +// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) + + .dataa(gnd), + .datab(A[5]), + .datac(gnd), + .datad(vcc), + .cin(\A[4]~20 ), + .combout(\A[5]~21_combout ), + .cout(\A[5]~22 )); +// synopsys translate_off +defparam \A[5]~21 .lut_mask = 16'hC30C; +defparam \A[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \A[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[5]), + .prn(vcc)); +// synopsys translate_off +defparam \A[5] .is_wysiwyg = "true"; +defparam \A[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \A[6]~23 ( +// Equation(s): +// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) +// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) + + .dataa(A[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[5]~22 ), + .combout(\A[6]~23_combout ), + .cout(\A[6]~24 )); +// synopsys translate_off +defparam \A[6]~23 .lut_mask = 16'h5A5F; +defparam \A[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \A[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[6]), + .prn(vcc)); +// synopsys translate_off +defparam \A[6] .is_wysiwyg = "true"; +defparam \A[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \A[7]~25 ( +// Equation(s): +// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) +// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) + + .dataa(A[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[6]~24 ), + .combout(\A[7]~25_combout ), + .cout(\A[7]~26 )); +// synopsys translate_off +defparam \A[7]~25 .lut_mask = 16'hA50A; +defparam \A[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \A[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[7]), + .prn(vcc)); +// synopsys translate_off +defparam \A[7] .is_wysiwyg = "true"; +defparam \A[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \A[8]~27 ( +// Equation(s): +// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) +// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) + + .dataa(A[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[7]~26 ), + .combout(\A[8]~27_combout ), + .cout(\A[8]~28 )); +// synopsys translate_off +defparam \A[8]~27 .lut_mask = 16'h5A5F; +defparam \A[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N15 +dffeas \A[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[8]), + .prn(vcc)); +// synopsys translate_off +defparam \A[8] .is_wysiwyg = "true"; +defparam \A[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \A[9]~29 ( +// Equation(s): +// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) +// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) + + .dataa(gnd), + .datab(A[9]), + .datac(gnd), + .datad(vcc), + .cin(\A[8]~28 ), + .combout(\A[9]~29_combout ), + .cout(\A[9]~30 )); +// synopsys translate_off +defparam \A[9]~29 .lut_mask = 16'hC30C; +defparam \A[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \A[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[9]), + .prn(vcc)); +// synopsys translate_off +defparam \A[9] .is_wysiwyg = "true"; +defparam \A[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \A[10]~31 ( +// Equation(s): +// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) +// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) + + .dataa(gnd), + .datab(A[10]), + .datac(gnd), + .datad(vcc), + .cin(\A[9]~30 ), + .combout(\A[10]~31_combout ), + .cout(\A[10]~32 )); +// synopsys translate_off +defparam \A[10]~31 .lut_mask = 16'h3C3F; +defparam \A[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \A[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[10]), + .prn(vcc)); +// synopsys translate_off +defparam \A[10] .is_wysiwyg = "true"; +defparam \A[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \A[11]~33 ( +// Equation(s): +// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) +// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) + + .dataa(gnd), + .datab(A[11]), + .datac(gnd), + .datad(vcc), + .cin(\A[10]~32 ), + .combout(\A[11]~33_combout ), + .cout(\A[11]~34 )); +// synopsys translate_off +defparam \A[11]~33 .lut_mask = 16'hC30C; +defparam \A[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \A[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[11]), + .prn(vcc)); +// synopsys translate_off +defparam \A[11] .is_wysiwyg = "true"; +defparam \A[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \A[12]~35 ( +// Equation(s): +// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) +// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) + + .dataa(A[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[11]~34 ), + .combout(\A[12]~35_combout ), + .cout(\A[12]~36 )); +// synopsys translate_off +defparam \A[12]~35 .lut_mask = 16'h5A5F; +defparam \A[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \A[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[12]), + .prn(vcc)); +// synopsys translate_off +defparam \A[12] .is_wysiwyg = "true"; +defparam \A[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \A[13]~37 ( +// Equation(s): +// \A[13]~37_combout = \A[12]~36 $ (!A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[13]), + .cin(\A[12]~36 ), + .combout(\A[13]~37_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +defparam \A[13]~37 .lut_mask = 16'hF00F; +defparam \A[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \A[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[13]), + .prn(vcc)); +// synopsys translate_off +defparam \A[13] .is_wysiwyg = "true"; +defparam \A[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 +// Location: M9K_X22_Y13_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -2494,14 +2084,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2540,25 +2130,153 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X23_Y18_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), - .cout()); +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2568,14 +2286,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2614,7 +2332,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X22_Y11_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2624,14 +2342,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2670,81 +2388,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(gnd), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2754,14 +2416,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2800,26 +2462,8 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: LCCOMB_X32_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2828,53 +2472,71 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(vcc), .portare(vcc), @@ -2884,14 +2546,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2930,22 +2592,78 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N12 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 77d78f8..bc38df0 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:12:28") + (DATE "03/30/2022 13:47:24") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1517:1517:1517) (1544:1544:1544)) + (PORT i (2068:2068:2068) (2050:2050:2050)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1454:1454:1454) (1428:1428:1428)) + (PORT i (2478:2478:2478) (2480:2480:2480)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1610:1610:1610) (1575:1575:1575)) + (PORT i (2467:2467:2467) (2430:2430:2430)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1039:1039:1039) (1034:1034:1034)) + (PORT i (1746:1746:1746) (1704:1704:1704)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1347:1347:1347) (1342:1342:1342)) + (PORT i (2240:2240:2240) (2238:2238:2238)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1969:1969:1969) (1936:1936:1936)) + (PORT i (1807:1807:1807) (1820:1820:1820)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2280:2280:2280) (2169:2169:2169)) + (PORT i (2185:2185:2185) (2116:2116:2116)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (886:886:886) (919:919:919)) + (PORT i (1193:1193:1193) (1143:1143:1143)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -148,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -177,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -191,7 +191,7 @@ (INSTANCE counter\[2\]\~23) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (300:300:300)) + (PORT datab (228:228:228) (299:299:299)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -205,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -233,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -247,7 +247,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (299:299:299)) + (PORT datab (227:227:227) (301:301:301)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -261,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -275,7 +275,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (309:309:309)) + (PORT datab (228:228:228) (300:300:300)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -289,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -317,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -331,7 +331,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (299:299:299)) + (PORT datab (239:239:239) (308:308:308)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -345,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -359,7 +359,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (305:305:305)) + (PORT dataa (240:240:240) (312:312:312)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -373,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -387,7 +387,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (297:297:297)) + (PORT datab (238:238:238) (307:307:307)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -401,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -415,7 +415,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (228:228:228) (302:302:302)) + (PORT dataa (240:240:240) (312:312:312)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -429,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -443,31 +443,21 @@ (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (680:680:680)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (238:238:238) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (294:294:294) (300:300:300)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -495,7 +485,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -509,9 +499,9 @@ (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (299:299:299)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (379:379:379) (426:426:426)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -523,7 +513,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -551,7 +541,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -565,9 +555,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (299:299:299)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (379:379:379) (426:426:426)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -579,7 +569,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -607,7 +597,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -635,7 +625,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -663,7 +653,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -691,7 +681,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -700,102 +690,6 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (310:310:310)) - (PORT datab (228:228:228) (300:300:300)) - (PORT datac (202:202:202) (274:274:274)) - (PORT datad (207:207:207) (269:269:269)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datab (227:227:227) (300:300:300)) - (PORT datac (201:201:201) (271:271:271)) - (PORT datad (204:204:204) (265:265:265)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (PORT datab (228:228:228) (301:301:301)) - (PORT datac (354:354:354) (389:389:389)) - (PORT datad (204:204:204) (265:265:265)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (311:311:311)) - (PORT datab (239:239:239) (308:308:308)) - (PORT datac (205:205:205) (277:277:277)) - (PORT datad (206:206:206) (268:268:268)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (310:310:310)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (202:202:202) (274:274:274)) - (PORT datad (206:206:206) (268:268:268)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (333:333:333)) - (PORT datab (325:325:325) (332:332:332)) - (PORT datac (313:313:313) (319:319:319)) - (PORT datad (544:544:544) (539:539:539)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE counter\[20\]\~59) @@ -815,7 +709,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1680:1680:1680) (1699:1699:1699)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -838,6 +732,143 @@ (CELL (CELLTYPE "dffeas") (INSTANCE counter\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1680:1680:1680) (1699:1699:1699)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (201:201:201) (271:271:271)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (305:305:305)) + (PORT datab (226:226:226) (298:298:298)) + (PORT datac (200:200:200) (270:270:270)) + (PORT datad (203:203:203) (265:265:265)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (228:228:228) (302:302:302)) + (PORT datac (353:353:353) (392:392:392)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (453:453:453)) + (PORT datab (379:379:379) (422:422:422)) + (PORT datac (533:533:533) (544:544:544)) + (PORT datad (537:537:537) (553:553:553)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (241:241:241) (311:311:311)) + (PORT datac (216:216:216) (283:283:283)) + (PORT datad (206:206:206) (268:268:268)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (368:368:368)) + (PORT datab (323:323:323) (337:337:337)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (586:586:586) (583:583:583)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (842:842:842)) + (PORT datab (861:861:861) (867:867:867)) + (PORT datac (571:571:571) (562:562:562)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (313:313:313)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[0\]) (DELAY (ABSOLUTE (PORT clk (1681:1681:1681) (1700:1700:1700)) @@ -851,52 +882,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) + (INSTANCE A\[1\]\~13) (DELAY (ABSOLUTE - (PORT datac (624:624:624) (648:648:648)) - (PORT datad (603:603:603) (623:623:623)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (593:593:593)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datad (306:306:306) (313:313:313)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1652:1652:1652) (1662:1662:1662)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (318:318:318)) - (PORT datab (237:237:237) (306:306:306)) + (PORT dataa (413:413:413) (463:463:463)) + (PORT datab (575:575:575) (602:602:602)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -905,30 +895,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (681:681:681)) - (PORT datab (627:627:627) (652:652:652)) - (PORT datac (564:564:564) (562:562:562)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[1\]) + (INSTANCE A\[1\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -939,7 +913,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~15) + (INSTANCE A\[2\]\~15) (DELAY (ABSOLUTE (PORT datab (238:238:238) (307:307:307)) @@ -953,12 +927,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -969,10 +943,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[3\]\~17) + (INSTANCE A\[3\]\~17) (DELAY (ABSOLUTE - (PORT datab (257:257:257) (326:326:326)) + (PORT datab (239:239:239) (307:307:307)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -983,12 +957,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[3\]) + (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -999,7 +973,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[4\]\~19) + (INSTANCE A\[4\]\~19) (DELAY (ABSOLUTE (PORT dataa (241:241:241) (313:313:313)) @@ -1013,12 +987,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[4\]) + (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1029,7 +1003,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[5\]\~21) + (INSTANCE A\[5\]\~21) (DELAY (ABSOLUTE (PORT datab (240:240:240) (308:308:308)) @@ -1043,12 +1017,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[5\]) + (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1059,7 +1033,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[6\]\~23) + (INSTANCE A\[6\]\~23) (DELAY (ABSOLUTE (PORT dataa (242:242:242) (315:315:315)) @@ -1073,12 +1047,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[6\]) + (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1089,7 +1063,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[7\]\~25) + (INSTANCE A\[7\]\~25) (DELAY (ABSOLUTE (PORT dataa (242:242:242) (315:315:315)) @@ -1103,12 +1077,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[7\]) + (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1119,12 +1093,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[8\]\~27) + (INSTANCE A\[8\]\~27) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (373:373:373) (423:423:423)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -1133,12 +1107,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[8\]) + (INSTANCE A\[8\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1149,10 +1123,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[9\]\~29) + (INSTANCE A\[9\]\~29) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) + (PORT datab (259:259:259) (329:329:329)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -1163,12 +1137,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[9\]) + (INSTANCE A\[9\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1179,7 +1153,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[10\]\~31) + (INSTANCE A\[10\]\~31) (DELAY (ABSOLUTE (PORT datab (241:241:241) (310:310:310)) @@ -1193,12 +1167,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[10\]) + (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1209,7 +1183,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[11\]\~33) + (INSTANCE A\[11\]\~33) (DELAY (ABSOLUTE (PORT datab (241:241:241) (311:311:311)) @@ -1223,12 +1197,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[11\]) + (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1239,7 +1213,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[12\]\~35) + (INSTANCE A\[12\]\~35) (DELAY (ABSOLUTE (PORT dataa (242:242:242) (314:314:314)) @@ -1253,12 +1227,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[12\]) + (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1269,7 +1243,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[13\]\~37) + (INSTANCE A\[13\]\~37) (DELAY (ABSOLUTE (PORT datad (235:235:235) (292:292:292)) @@ -1280,12 +1254,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[13\]) + (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1681:1681:1681) (1700:1700:1700)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (721:721:721) (723:723:723)) + (PORT ena (740:740:740) (743:743:743)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -1294,73 +1268,13 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (395:395:395) (436:436:436)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (201:201:201) (259:259:259)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1137:1137:1137) (1173:1173:1173)) - (PORT d[1] (1176:1176:1176) (1232:1232:1232)) - (PORT d[2] (1242:1242:1242) (1303:1303:1303)) - (PORT d[3] (1221:1221:1221) (1276:1276:1276)) - (PORT d[4] (1152:1152:1152) (1201:1201:1201)) - (PORT d[5] (1260:1260:1260) (1308:1308:1308)) - (PORT d[6] (1591:1591:1591) (1705:1705:1705)) - (PORT d[7] (1212:1212:1212) (1268:1268:1268)) - (PORT d[8] (1218:1218:1218) (1274:1274:1274)) - (PORT d[9] (1254:1254:1254) (1299:1299:1299)) - (PORT d[10] (1220:1220:1220) (1267:1267:1267)) - (PORT d[11] (1449:1449:1449) (1466:1466:1466)) - (PORT d[12] (1195:1195:1195) (1234:1234:1234)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (965:965:965) (986:986:986)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) ) ) (TIMINGCHECK @@ -1369,413 +1283,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (1070:1070:1070) (1057:1057:1057)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1066:1066:1066) (1108:1108:1108)) - (PORT d[1] (903:903:903) (960:960:960)) - (PORT d[2] (960:960:960) (1018:1018:1018)) - (PORT d[3] (1239:1239:1239) (1281:1281:1281)) - (PORT d[4] (1152:1152:1152) (1192:1192:1192)) - (PORT d[5] (1224:1224:1224) (1264:1264:1264)) - (PORT d[6] (1390:1390:1390) (1523:1523:1523)) - (PORT d[7] (1170:1170:1170) (1209:1209:1209)) - (PORT d[8] (1226:1226:1226) (1271:1271:1271)) - (PORT d[9] (1281:1281:1281) (1333:1333:1333)) - (PORT d[10] (1209:1209:1209) (1251:1251:1251)) - (PORT d[11] (1182:1182:1182) (1215:1215:1215)) - (PORT d[12] (1240:1240:1240) (1281:1281:1281)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (859:859:859) (849:849:849)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (885:885:885) (944:944:944)) - (PORT datac (813:813:813) (791:791:791)) - (PORT datad (568:568:568) (546:546:546)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1358:1358:1358) (1390:1390:1390)) - (PORT d[1] (1429:1429:1429) (1457:1457:1457)) - (PORT d[2] (1457:1457:1457) (1497:1497:1497)) - (PORT d[3] (1164:1164:1164) (1188:1188:1188)) - (PORT d[4] (1495:1495:1495) (1557:1557:1557)) - (PORT d[5] (1763:1763:1763) (1849:1849:1849)) - (PORT d[6] (1169:1169:1169) (1188:1188:1188)) - (PORT d[7] (1246:1246:1246) (1305:1305:1305)) - (PORT d[8] (1752:1752:1752) (1825:1825:1825)) - (PORT d[9] (1142:1142:1142) (1172:1172:1172)) - (PORT d[10] (1313:1313:1313) (1369:1369:1369)) - (PORT d[11] (1131:1131:1131) (1139:1139:1139)) - (PORT d[12] (1168:1168:1168) (1195:1195:1195)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (1021:1021:1021) (1044:1044:1044)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1395:1395:1395) (1437:1437:1437)) - (PORT d[1] (1255:1255:1255) (1322:1322:1322)) - (PORT d[2] (1479:1479:1479) (1521:1521:1521)) - (PORT d[3] (1244:1244:1244) (1292:1292:1292)) - (PORT d[4] (1222:1222:1222) (1273:1273:1273)) - (PORT d[5] (1476:1476:1476) (1561:1561:1561)) - (PORT d[6] (1179:1179:1179) (1243:1243:1243)) - (PORT d[7] (1164:1164:1164) (1224:1224:1224)) - (PORT d[8] (1495:1495:1495) (1577:1577:1577)) - (PORT d[9] (1230:1230:1230) (1283:1283:1283)) - (PORT d[10] (1677:1677:1677) (1744:1744:1744)) - (PORT d[11] (1203:1203:1203) (1262:1262:1262)) - (PORT d[12] (1455:1455:1455) (1512:1512:1512)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (1111:1111:1111) (1127:1127:1127)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (581:581:581)) - (PORT datac (815:815:815) (815:815:815)) - (PORT datad (1247:1247:1247) (1247:1247:1247)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1143:1143:1143) (1193:1193:1193)) - (PORT d[1] (1186:1186:1186) (1252:1252:1252)) - (PORT d[2] (1471:1471:1471) (1533:1533:1533)) - (PORT d[3] (1278:1278:1278) (1335:1335:1335)) - (PORT d[4] (1183:1183:1183) (1244:1244:1244)) - (PORT d[5] (1185:1185:1185) (1237:1237:1237)) - (PORT d[6] (1596:1596:1596) (1726:1726:1726)) - (PORT d[7] (1243:1243:1243) (1300:1300:1300)) - (PORT d[8] (1232:1232:1232) (1284:1284:1284)) - (PORT d[9] (1304:1304:1304) (1372:1372:1372)) - (PORT d[10] (1636:1636:1636) (1650:1650:1650)) - (PORT d[11] (1457:1457:1457) (1491:1491:1491)) - (PORT d[12] (1228:1228:1228) (1274:1274:1274)) + (PORT d[0] (967:967:967) (1018:1018:1018)) + (PORT d[1] (1372:1372:1372) (1392:1392:1392)) + (PORT d[2] (884:884:884) (921:921:921)) + (PORT d[3] (941:941:941) (967:967:967)) + (PORT d[4] (941:941:941) (967:967:967)) + (PORT d[5] (720:720:720) (753:753:753)) + (PORT d[6] (720:720:720) (753:753:753)) + (PORT d[7] (720:720:720) (753:753:753)) + (PORT d[8] (720:720:720) (753:753:753)) + (PORT d[9] (720:720:720) (753:753:753)) + (PORT d[10] (720:720:720) (753:753:753)) + (PORT d[11] (720:720:720) (753:753:753)) + (PORT d[12] (720:720:720) (753:753:753)) (PORT clk (1641:1641:1641) (1668:1668:1668)) ) ) @@ -1785,30 +1308,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1668:1668:1668)) - (PORT d[0] (1114:1114:1114) (1098:1098:1098)) + (PORT clk (1644:1644:1644) (1670:1670:1670)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -1819,61 +1371,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (890:890:890) (939:939:939)) - (PORT d[1] (1164:1164:1164) (1202:1202:1202)) - (PORT d[2] (971:971:971) (1014:1014:1014)) - (PORT d[3] (996:996:996) (1048:1048:1048)) - (PORT d[4] (894:894:894) (953:953:953)) - (PORT d[5] (1145:1145:1145) (1182:1182:1182)) - (PORT d[6] (1364:1364:1364) (1494:1494:1494)) - (PORT d[7] (1170:1170:1170) (1208:1208:1208)) - (PORT d[8] (975:975:975) (1038:1038:1038)) - (PORT d[9] (1019:1019:1019) (1085:1085:1085)) - (PORT d[10] (1404:1404:1404) (1421:1421:1421)) - (PORT d[11] (1181:1181:1181) (1214:1214:1214)) - (PORT d[12] (1214:1214:1214) (1252:1252:1252)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (969:969:969) (990:990:990)) + (PORT clk (1611:1611:1611) (1607:1607:1607)) ) ) (TIMINGCHECK @@ -1882,108 +1384,84 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (848:848:848) (858:858:858)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + (PORT d[0] (949:949:949) (1000:1000:1000)) + (PORT d[1] (1373:1373:1373) (1393:1393:1393)) + (PORT d[2] (907:907:907) (939:939:939)) + (PORT d[3] (1154:1154:1154) (1170:1170:1170)) + (PORT d[4] (893:893:893) (932:932:932)) + (PORT d[5] (1441:1441:1441) (1466:1466:1466)) + (PORT d[6] (1147:1147:1147) (1174:1174:1174)) + (PORT d[7] (1183:1183:1183) (1221:1221:1221)) + (PORT d[8] (1128:1128:1128) (1149:1149:1149)) + (PORT d[9] (1143:1143:1143) (1180:1180:1180)) + (PORT d[10] (1158:1158:1158) (1183:1183:1183)) + (PORT d[11] (1143:1143:1143) (1170:1170:1170)) + (PORT d[12] (1190:1190:1190) (1223:1223:1223)) + (PORT clk (1608:1608:1608) (1604:1604:1604)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) + (HOLD d (posedge clk) (169:169:169)) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) + (PORT clk (1611:1611:1611) (1607:1607:1607)) + (PORT d[0] (817:817:817) (818:818:818)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (1612:1612:1612) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (1612:1612:1612) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1608:1608:1608)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (1612:1612:1612) (1608:1608:1608)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (905:905:905) (961:961:961)) - (PORT datac (835:835:835) (824:824:824)) - (PORT datad (554:554:554) (539:539:539)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (864:864:864) (888:888:888)) - (PORT d[1] (904:904:904) (943:943:943)) - (PORT d[2] (999:999:999) (1044:1044:1044)) - (PORT d[3] (981:981:981) (1012:1012:1012)) - (PORT d[4] (883:883:883) (924:924:924)) - (PORT d[5] (931:931:931) (967:967:967)) - (PORT d[6] (1325:1325:1325) (1435:1435:1435)) - (PORT d[7] (1147:1147:1147) (1173:1173:1173)) - (PORT d[8] (1501:1501:1501) (1549:1549:1549)) - (PORT d[9] (1001:1001:1001) (1049:1049:1049)) - (PORT d[10] (963:963:963) (1003:1003:1003)) - (PORT d[11] (1202:1202:1202) (1209:1209:1209)) - (PORT d[12] (1200:1200:1200) (1222:1222:1222)) + (PORT d[0] (936:936:936) (951:951:951)) (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) @@ -1993,17 +1471,51 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (952:952:952) (1005:1005:1005)) + (PORT d[1] (1106:1106:1106) (1134:1134:1134)) + (PORT d[2] (886:886:886) (926:926:926)) + (PORT d[3] (953:953:953) (973:973:973)) + (PORT d[4] (953:953:953) (973:973:973)) + (PORT d[5] (749:749:749) (791:791:791)) + (PORT d[6] (749:749:749) (791:791:791)) + (PORT d[7] (749:749:749) (791:791:791)) + (PORT d[8] (749:749:749) (791:791:791)) + (PORT d[9] (749:749:749) (791:791:791)) + (PORT d[10] (749:749:749) (791:791:791)) + (PORT d[11] (749:749:749) (791:791:791)) + (PORT d[12] (749:749:749) (791:791:791)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (832:832:832) (824:824:824)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1644:1644:1644) (1671:1671:1671)) @@ -2011,109 +1523,32 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1113:1113:1113) (1125:1125:1125)) - (PORT d[1] (606:606:606) (637:637:637)) - (PORT d[2] (665:665:665) (695:695:695)) - (PORT d[3] (709:709:709) (741:741:741)) - (PORT d[4] (612:612:612) (647:647:647)) - (PORT d[5] (683:683:683) (724:724:724)) - (PORT d[6] (708:708:708) (738:738:738)) - (PORT d[7] (688:688:688) (727:727:727)) - (PORT d[8] (700:700:700) (736:736:736)) - (PORT d[9] (712:712:712) (753:753:753)) - (PORT d[10] (1139:1139:1139) (1140:1140:1140)) - (PORT d[11] (689:689:689) (724:724:724)) - (PORT d[12] (698:698:698) (736:736:736)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (568:568:568) (578:578:578)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) + (PORT clk (1602:1602:1602) (1600:1600:1600)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2124,75 +1559,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (853:853:853)) - (PORT datac (604:604:604) (635:635:635)) - (PORT datad (566:566:566) (544:544:544)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1371:1371:1371) (1392:1392:1392)) - (PORT d[1] (1421:1421:1421) (1436:1436:1436)) - (PORT d[2] (1449:1449:1449) (1476:1476:1476)) - (PORT d[3] (924:924:924) (961:961:961)) - (PORT d[4] (913:913:913) (957:957:957)) - (PORT d[5] (1485:1485:1485) (1575:1575:1575)) - (PORT d[6] (929:929:929) (974:974:974)) - (PORT d[7] (882:882:882) (925:925:925)) - (PORT d[8] (1483:1483:1483) (1569:1569:1569)) - (PORT d[9] (928:928:928) (958:958:958)) - (PORT d[10] (913:913:913) (949:949:949)) - (PORT d[11] (894:894:894) (932:932:932)) - (PORT d[12] (911:911:911) (944:944:944)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (940:940:940) (955:955:955)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) ) ) (TIMINGCHECK @@ -2201,30 +1572,171 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (793:793:793) (817:817:817)) + (PORT d[0] (974:974:974) (1028:1028:1028)) + (PORT d[1] (886:886:886) (928:928:928)) + (PORT d[2] (1182:1182:1182) (1202:1202:1202)) + (PORT d[3] (1153:1153:1153) (1160:1160:1160)) + (PORT d[4] (870:870:870) (911:911:911)) + (PORT d[5] (1436:1436:1436) (1446:1446:1446)) + (PORT d[6] (1183:1183:1183) (1208:1208:1208)) + (PORT d[7] (1185:1185:1185) (1223:1223:1223)) + (PORT d[8] (1334:1334:1334) (1340:1340:1340)) + (PORT d[9] (1147:1147:1147) (1186:1186:1186)) + (PORT d[10] (1167:1167:1167) (1196:1196:1196)) + (PORT d[11] (1154:1154:1154) (1177:1177:1177)) + (PORT d[12] (1176:1176:1176) (1203:1203:1203)) + (PORT clk (1607:1607:1607) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1607:1607:1607)) + (PORT d[0] (823:823:823) (821:821:821)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) + (PORT d[0] (1246:1246:1246) (1257:1257:1257)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (985:985:985) (1031:1031:1031)) + (PORT d[1] (862:862:862) (901:901:901)) + (PORT d[2] (1411:1411:1411) (1436:1436:1436)) + (PORT d[3] (1243:1243:1243) (1258:1258:1258)) + (PORT d[4] (1243:1243:1243) (1258:1258:1258)) + (PORT d[5] (710:710:710) (733:733:733)) + (PORT d[6] (710:710:710) (733:733:733)) + (PORT d[7] (710:710:710) (733:733:733)) + (PORT d[8] (710:710:710) (733:733:733)) + (PORT d[9] (710:710:710) (733:733:733)) + (PORT d[10] (710:710:710) (733:733:733)) + (PORT d[11] (710:710:710) (733:733:733)) + (PORT d[12] (710:710:710) (733:733:733)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1602:1602:1602)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2235,38 +1747,275 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT d[0] (1250:1250:1250) (1261:1261:1261)) + (PORT clk (1612:1612:1612) (1609:1609:1609)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (965:965:965) (1011:1011:1011)) + (PORT d[1] (1384:1384:1384) (1415:1415:1415)) + (PORT d[2] (851:851:851) (879:879:879)) + (PORT d[3] (1359:1359:1359) (1362:1362:1362)) + (PORT d[4] (865:865:865) (893:893:893)) + (PORT d[5] (979:979:979) (1019:1019:1019)) + (PORT d[6] (1158:1158:1158) (1174:1174:1174)) + (PORT d[7] (970:970:970) (994:994:994)) + (PORT d[8] (1375:1375:1375) (1392:1392:1392)) + (PORT d[9] (1161:1161:1161) (1191:1191:1191)) + (PORT d[10] (1150:1150:1150) (1166:1166:1166)) + (PORT d[11] (1157:1157:1157) (1177:1177:1177)) + (PORT d[12] (1155:1155:1155) (1174:1174:1174)) + (PORT clk (1609:1609:1609) (1606:1606:1606)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT d[0] (800:800:800) (809:809:809)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1257:1257:1257) (1262:1262:1262)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (704:704:704) (733:733:733)) + (PORT d[1] (597:597:597) (634:634:634)) + (PORT d[2] (1424:1424:1424) (1449:1449:1449)) + (PORT d[3] (623:623:623) (627:627:627)) + (PORT d[4] (623:623:623) (627:627:627)) + (PORT d[5] (447:447:447) (472:472:472)) + (PORT d[6] (447:447:447) (472:472:472)) + (PORT d[7] (447:447:447) (472:472:472)) + (PORT d[8] (447:447:447) (472:472:472)) + (PORT d[9] (447:447:447) (472:472:472)) + (PORT d[10] (447:447:447) (472:472:472)) + (PORT d[11] (447:447:447) (472:472:472)) + (PORT d[12] (447:447:447) (472:472:472)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1261:1261:1261) (1266:1266:1266)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (679:679:679) (718:718:718)) + (PORT d[1] (1414:1414:1414) (1440:1440:1440)) + (PORT d[2] (1426:1426:1426) (1449:1449:1449)) + (PORT d[3] (613:613:613) (642:642:642)) + (PORT d[4] (616:616:616) (651:651:651)) + (PORT d[5] (671:671:671) (707:707:707)) + (PORT d[6] (713:713:713) (745:745:745)) + (PORT d[7] (696:696:696) (738:738:738)) + (PORT d[8] (1404:1404:1404) (1432:1432:1432)) + (PORT d[9] (709:709:709) (732:732:732)) + (PORT d[10] (910:910:910) (932:932:932)) + (PORT d[11] (684:684:684) (714:714:714)) + (PORT d[12] (872:872:872) (895:895:895)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT d[0] (557:557:557) (569:569:569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2276,20 +2025,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1140:1140:1140) (1174:1174:1174)) - (PORT d[1] (1169:1169:1169) (1198:1198:1198)) - (PORT d[2] (1194:1194:1194) (1234:1234:1234)) - (PORT d[3] (1189:1189:1189) (1216:1216:1216)) - (PORT d[4] (1491:1491:1491) (1548:1548:1548)) - (PORT d[5] (1484:1484:1484) (1574:1574:1574)) - (PORT d[6] (1190:1190:1190) (1239:1239:1239)) - (PORT d[7] (1154:1154:1154) (1198:1198:1198)) - (PORT d[8] (1482:1482:1482) (1568:1568:1568)) - (PORT d[9] (1174:1174:1174) (1206:1206:1206)) - (PORT d[10] (1702:1702:1702) (1770:1770:1770)) - (PORT d[11] (1193:1193:1193) (1235:1235:1235)) - (PORT d[12] (1156:1156:1156) (1189:1189:1189)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1463:1463:1463) (1520:1520:1520)) + (PORT d[1] (1184:1184:1184) (1215:1215:1215)) + (PORT d[2] (1162:1162:1162) (1194:1194:1194)) + (PORT d[3] (1176:1176:1176) (1202:1202:1202)) + (PORT d[4] (1194:1194:1194) (1236:1236:1236)) + (PORT d[5] (1453:1453:1453) (1530:1530:1530)) + (PORT d[6] (1157:1157:1157) (1196:1196:1196)) + (PORT d[7] (1142:1142:1142) (1184:1184:1184)) + (PORT d[8] (1171:1171:1171) (1208:1208:1208)) + (PORT d[9] (1184:1184:1184) (1214:1214:1214)) + (PORT d[10] (1181:1181:1181) (1207:1207:1207)) + (PORT d[11] (1171:1171:1171) (1210:1210:1210)) + (PORT d[12] (1425:1425:1425) (1468:1468:1468)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -2301,8 +2050,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (1064:1064:1064) (1056:1056:1056)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1080:1080:1080) (1047:1047:1047)) ) ) ) @@ -2311,7 +2060,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -2321,7 +2070,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) + (PORT clk (1601:1601:1601) (1629:1629:1629)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2335,7 +2084,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (872:872:872) (876:876:876)) ) ) ) @@ -2344,7 +2093,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (873:873:873) (877:877:877)) ) ) ) @@ -2353,7 +2102,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (873:873:873) (877:877:877)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2363,21 +2112,166 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1225:1225:1225) (1295:1295:1295)) + (PORT d[1] (1172:1172:1172) (1212:1212:1212)) + (PORT d[2] (1177:1177:1177) (1223:1223:1223)) + (PORT d[3] (1234:1234:1234) (1269:1269:1269)) + (PORT d[4] (1224:1224:1224) (1277:1277:1277)) + (PORT d[5] (1448:1448:1448) (1523:1523:1523)) + (PORT d[6] (1144:1144:1144) (1190:1190:1190)) + (PORT d[7] (1151:1151:1151) (1201:1201:1201)) + (PORT d[8] (1184:1184:1184) (1233:1233:1233)) + (PORT d[9] (1167:1167:1167) (1202:1202:1202)) + (PORT d[10] (1166:1166:1166) (1196:1196:1196)) + (PORT d[11] (1181:1181:1181) (1219:1219:1219)) + (PORT d[12] (1176:1176:1176) (1246:1246:1246)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1083:1083:1083) (1109:1109:1109)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datab (597:597:597) (583:583:583)) - (PORT datac (797:797:797) (769:769:769)) - (PORT datad (747:747:747) (756:756:756)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datac (597:597:597) (621:621:621)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (586:586:586) (570:570:570)) + (PORT datac (853:853:853) (841:841:841)) + (PORT datad (901:901:901) (939:939:939)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -2387,19 +2281,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1404:1404:1404) (1451:1451:1451)) - (PORT d[1] (1754:1754:1754) (1846:1846:1846)) - (PORT d[2] (1170:1170:1170) (1226:1226:1226)) - (PORT d[3] (1230:1230:1230) (1270:1270:1270)) - (PORT d[4] (1206:1206:1206) (1267:1267:1267)) - (PORT d[5] (1157:1157:1157) (1221:1221:1221)) - (PORT d[6] (1207:1207:1207) (1273:1273:1273)) - (PORT d[7] (1170:1170:1170) (1232:1232:1232)) - (PORT d[8] (1488:1488:1488) (1556:1556:1556)) - (PORT d[9] (1215:1215:1215) (1269:1269:1269)) - (PORT d[10] (1722:1722:1722) (1787:1787:1787)) - (PORT d[11] (1184:1184:1184) (1241:1241:1241)) - (PORT d[12] (1422:1422:1422) (1464:1464:1464)) + (PORT d[0] (1471:1471:1471) (1536:1536:1536)) + (PORT d[1] (917:917:917) (958:958:958)) + (PORT d[2] (929:929:929) (984:984:984)) + (PORT d[3] (974:974:974) (991:991:991)) + (PORT d[4] (912:912:912) (955:955:955)) + (PORT d[5] (1454:1454:1454) (1531:1531:1531)) + (PORT d[6] (910:910:910) (947:947:947)) + (PORT d[7] (884:884:884) (927:927:927)) + (PORT d[8] (938:938:938) (983:983:983)) + (PORT d[9] (1410:1410:1410) (1416:1416:1416)) + (PORT d[10] (1372:1372:1372) (1359:1359:1359)) + (PORT d[11] (886:886:886) (923:923:923)) + (PORT d[12] (926:926:926) (969:969:969)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -2413,7 +2307,7 @@ (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (1100:1100:1100) (1091:1091:1091)) + (PORT d[0] (829:829:829) (809:809:809)) ) ) ) @@ -2484,20 +2378,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1448:1448:1448) (1498:1498:1498)) - (PORT d[1] (1506:1506:1506) (1592:1592:1592)) - (PORT d[2] (1452:1452:1452) (1509:1509:1509)) - (PORT d[3] (1528:1528:1528) (1576:1576:1576)) - (PORT d[4] (1475:1475:1475) (1541:1541:1541)) - (PORT d[5] (1462:1462:1462) (1522:1522:1522)) - (PORT d[6] (1454:1454:1454) (1503:1503:1503)) - (PORT d[7] (1420:1420:1420) (1469:1469:1469)) - (PORT d[8] (1442:1442:1442) (1487:1487:1487)) - (PORT d[9] (1473:1473:1473) (1520:1520:1520)) - (PORT d[10] (1421:1421:1421) (1470:1470:1470)) - (PORT d[11] (1448:1448:1448) (1508:1508:1508)) - (PORT d[12] (1420:1420:1420) (1464:1464:1464)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1166:1166:1166) (1209:1209:1209)) + (PORT d[1] (1176:1176:1176) (1219:1219:1219)) + (PORT d[2] (1148:1148:1148) (1195:1195:1195)) + (PORT d[3] (1218:1218:1218) (1252:1252:1252)) + (PORT d[4] (1181:1181:1181) (1236:1236:1236)) + (PORT d[5] (1446:1446:1446) (1481:1481:1481)) + (PORT d[6] (1170:1170:1170) (1218:1218:1218)) + (PORT d[7] (1154:1154:1154) (1206:1206:1206)) + (PORT d[8] (1188:1188:1188) (1239:1239:1239)) + (PORT d[9] (1170:1170:1170) (1208:1208:1208)) + (PORT d[10] (1169:1169:1169) (1201:1201:1201)) + (PORT d[11] (1159:1159:1159) (1204:1204:1204)) + (PORT d[12] (1405:1405:1405) (1441:1441:1441)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -2509,8 +2403,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (1331:1331:1331) (1332:1332:1332)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1034:1034:1034) (1056:1056:1056)) ) ) ) @@ -2519,7 +2413,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -2529,7 +2423,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) + (PORT clk (1599:1599:1599) (1626:1626:1626)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2543,7 +2437,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) + (PORT clk (870:870:870) (873:873:873)) ) ) ) @@ -2552,7 +2446,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (871:871:871) (874:874:874)) ) ) ) @@ -2561,7 +2455,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (871:871:871) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2571,22 +2465,119 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (871:871:871) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT datab (584:584:584) (569:569:569)) - (PORT datac (839:839:839) (835:835:835)) - (PORT datad (1050:1050:1050) (1093:1093:1093)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (581:581:581) (581:581:581)) + (PORT datab (675:675:675) (722:722:722)) + (PORT datac (835:835:835) (825:825:825)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1730:1730:1730) (1788:1788:1788)) + (PORT d[1] (1138:1138:1138) (1162:1162:1162)) + (PORT d[2] (1178:1178:1178) (1212:1212:1212)) + (PORT d[3] (1221:1221:1221) (1226:1226:1226)) + (PORT d[4] (1174:1174:1174) (1190:1190:1190)) + (PORT d[5] (1739:1739:1739) (1812:1812:1812)) + (PORT d[6] (1161:1161:1161) (1174:1174:1174)) + (PORT d[7] (1257:1257:1257) (1318:1318:1318)) + (PORT d[8] (1125:1125:1125) (1155:1155:1155)) + (PORT d[9] (1167:1167:1167) (1188:1188:1188)) + (PORT d[10] (1178:1178:1178) (1194:1194:1194)) + (PORT d[11] (1131:1131:1131) (1145:1145:1145)) + (PORT d[12] (1172:1172:1172) (1230:1230:1230)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1039:1039:1039) (1059:1059:1059)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) @@ -2595,19 +2586,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (891:891:891) (939:939:939)) - (PORT d[1] (1151:1151:1151) (1192:1192:1192)) - (PORT d[2] (982:982:982) (1034:1034:1034)) - (PORT d[3] (1008:1008:1008) (1057:1057:1057)) - (PORT d[4] (914:914:914) (974:974:974)) - (PORT d[5] (988:988:988) (1039:1039:1039)) - (PORT d[6] (1336:1336:1336) (1464:1464:1464)) - (PORT d[7] (1184:1184:1184) (1228:1228:1228)) - (PORT d[8] (977:977:977) (1032:1032:1032)) - (PORT d[9] (982:982:982) (1046:1046:1046)) - (PORT d[10] (949:949:949) (1003:1003:1003)) - (PORT d[11] (1165:1165:1165) (1197:1197:1197)) - (PORT d[12] (1210:1210:1210) (1246:1246:1246)) + (PORT d[0] (709:709:709) (744:744:744)) + (PORT d[1] (597:597:597) (635:635:635)) + (PORT d[2] (1405:1405:1405) (1428:1428:1428)) + (PORT d[3] (1136:1136:1136) (1139:1139:1139)) + (PORT d[4] (876:876:876) (905:905:905)) + (PORT d[5] (977:977:977) (1007:1007:1007)) + (PORT d[6] (1112:1112:1112) (1125:1125:1125)) + (PORT d[7] (1159:1159:1159) (1172:1172:1172)) + (PORT d[8] (1381:1381:1381) (1409:1409:1409)) + (PORT d[9] (1161:1161:1161) (1186:1186:1186)) + (PORT d[10] (1148:1148:1148) (1158:1158:1158)) + (PORT d[11] (1125:1125:1125) (1135:1135:1135)) + (PORT d[12] (1149:1149:1149) (1159:1159:1159)) (PORT clk (1643:1643:1643) (1672:1672:1672)) ) ) @@ -2621,7 +2612,7 @@ (DELAY (ABSOLUTE (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (842:842:842) (851:851:851)) + (PORT d[0] (817:817:817) (799:799:799)) ) ) ) @@ -2687,233 +2678,39 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (853:853:853) (884:884:884)) - (PORT d[1] (606:606:606) (638:638:638)) - (PORT d[2] (1214:1214:1214) (1272:1272:1272)) - (PORT d[3] (1231:1231:1231) (1305:1305:1305)) - (PORT d[4] (860:860:860) (887:887:887)) - (PORT d[5] (973:973:973) (1005:1005:1005)) - (PORT d[6] (1300:1300:1300) (1396:1396:1396)) - (PORT d[7] (1150:1150:1150) (1164:1164:1164)) - (PORT d[8] (1515:1515:1515) (1564:1564:1564)) - (PORT d[9] (972:972:972) (1000:1000:1000)) - (PORT d[10] (968:968:968) (992:992:992)) - (PORT d[11] (1116:1116:1116) (1120:1120:1120)) - (PORT d[12] (1163:1163:1163) (1171:1171:1171)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (798:798:798) (816:816:816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (659:659:659)) - (PORT datac (837:837:837) (850:850:850)) - (PORT datad (328:328:328) (320:320:320)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (876:876:876) (918:918:918)) + (PORT datac (557:557:557) (538:538:538)) + (PORT datad (966:966:966) (927:927:927)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1373:1373:1373) (1418:1418:1418)) - (PORT d[1] (1747:1747:1747) (1825:1825:1825)) - (PORT d[2] (1746:1746:1746) (1807:1807:1807)) - (PORT d[3] (1277:1277:1277) (1330:1330:1330)) - (PORT d[4] (1743:1743:1743) (1797:1797:1797)) - (PORT d[5] (1224:1224:1224) (1295:1295:1295)) - (PORT d[6] (1233:1233:1233) (1302:1302:1302)) - (PORT d[7] (1171:1171:1171) (1233:1233:1233)) - (PORT d[8] (1217:1217:1217) (1283:1283:1283)) - (PORT d[9] (1191:1191:1191) (1242:1242:1242)) - (PORT d[10] (1667:1667:1667) (1716:1716:1716)) - (PORT d[11] (1184:1184:1184) (1242:1242:1242)) - (PORT d[12] (1175:1175:1175) (1226:1226:1226)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (1135:1135:1135) (1114:1114:1114)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1688:1688:1688) (1727:1727:1727)) - (PORT d[1] (1489:1489:1489) (1529:1529:1529)) - (PORT d[2] (1466:1466:1466) (1541:1541:1541)) - (PORT d[3] (1503:1503:1503) (1555:1555:1555)) - (PORT d[4] (1477:1477:1477) (1556:1556:1556)) - (PORT d[5] (1450:1450:1450) (1516:1516:1516)) - (PORT d[6] (1438:1438:1438) (1502:1502:1502)) - (PORT d[7] (1428:1428:1428) (1489:1489:1489)) - (PORT d[8] (1421:1421:1421) (1476:1476:1476)) - (PORT d[9] (1475:1475:1475) (1533:1533:1533)) - (PORT d[10] (1392:1392:1392) (1448:1448:1448)) - (PORT d[11] (1450:1450:1450) (1514:1514:1514)) - (PORT d[12] (1424:1424:1424) (1479:1479:1479)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1429:1429:1429) (1476:1476:1476)) + (PORT d[1] (1197:1197:1197) (1241:1241:1241)) + (PORT d[2] (1171:1171:1171) (1217:1217:1217)) + (PORT d[3] (1268:1268:1268) (1305:1305:1305)) + (PORT d[4] (1457:1457:1457) (1497:1497:1497)) + (PORT d[5] (1204:1204:1204) (1268:1268:1268)) + (PORT d[6] (1196:1196:1196) (1238:1238:1238)) + (PORT d[7] (1155:1155:1155) (1207:1207:1207)) + (PORT d[8] (1164:1164:1164) (1212:1212:1212)) + (PORT d[9] (1196:1196:1196) (1237:1237:1237)) + (PORT d[10] (1195:1195:1195) (1230:1230:1230)) + (PORT d[11] (1159:1159:1159) (1205:1205:1205)) + (PORT d[12] (1156:1156:1156) (1197:1197:1197)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) ) ) (TIMINGCHECK @@ -2925,8 +2722,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1660:1660:1660)) - (PORT d[0] (1376:1376:1376) (1394:1394:1394)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + (PORT d[0] (1051:1051:1051) (1017:1017:1017)) ) ) ) @@ -2935,7 +2732,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1661:1661:1661)) + (PORT clk (1630:1630:1630) (1659:1659:1659)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -2945,7 +2742,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) + (PORT clk (1596:1596:1596) (1624:1624:1624)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -2959,7 +2756,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) + (PORT clk (867:867:867) (871:871:871)) ) ) ) @@ -2968,7 +2765,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (868:868:868) (872:872:872)) ) ) ) @@ -2977,7 +2774,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (868:868:868) (872:872:872)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -2987,21 +2784,118 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (942:942:942) (994:994:994)) + (PORT d[1] (857:857:857) (902:902:902)) + (PORT d[2] (859:859:859) (895:895:895)) + (PORT d[3] (1152:1152:1152) (1160:1160:1160)) + (PORT d[4] (1403:1403:1403) (1451:1451:1451)) + (PORT d[5] (1209:1209:1209) (1238:1238:1238)) + (PORT d[6] (1157:1157:1157) (1180:1180:1180)) + (PORT d[7] (1218:1218:1218) (1253:1253:1253)) + (PORT d[8] (1362:1362:1362) (1381:1381:1381)) + (PORT d[9] (1172:1172:1172) (1214:1214:1214)) + (PORT d[10] (1167:1167:1167) (1196:1196:1196)) + (PORT d[11] (1179:1179:1179) (1206:1206:1206)) + (PORT d[12] (1176:1176:1176) (1203:1203:1203)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (824:824:824) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) (DELAY (ABSOLUTE - (PORT datab (593:593:593) (577:577:577)) - (PORT datac (833:833:833) (822:822:822)) - (PORT datad (1052:1052:1052) (1094:1094:1094)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (927:927:927) (979:979:979)) + (PORT datac (562:562:562) (545:545:545)) + (PORT datad (978:978:978) (932:932:932)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index 1499b6d..e44946c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:12:28" +// DATE "03/30/2022 13:47:24" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -93,7 +93,6 @@ wire \counter[9]~38 ; wire \counter[10]~39_combout ; wire \counter[10]~40 ; wire \counter[11]~41_combout ; -wire \counter[11]~feeder_combout ; wire \counter[11]~42 ; wire \counter[12]~43_combout ; wire \counter[12]~44 ; @@ -110,83 +109,71 @@ wire \counter[17]~54 ; wire \counter[18]~55_combout ; wire \counter[18]~56 ; wire \counter[19]~57_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \counter[19]~58 ; -wire \counter[20]~59_combout ; -wire \counter[20]~60 ; -wire \counter[21]~61_combout ; -wire \Equal0~7_combout ; -wire \address[0]~39_combout ; -wire \address[1]~13_combout ; wire \Equal0~6_combout ; -wire \address[1]~14 ; -wire \address[2]~15_combout ; -wire \address[2]~16 ; -wire \address[3]~17_combout ; -wire \address[3]~18 ; -wire \address[4]~19_combout ; -wire \address[4]~20 ; -wire \address[5]~21_combout ; -wire \address[5]~22 ; -wire \address[6]~23_combout ; -wire \address[6]~24 ; -wire \address[7]~25_combout ; -wire \address[7]~26 ; -wire \address[8]~27_combout ; -wire \address[8]~28 ; -wire \address[9]~29_combout ; -wire \address[9]~30 ; -wire \address[10]~31_combout ; -wire \address[10]~32 ; -wire \address[11]~33_combout ; -wire \address[11]~34 ; -wire \address[12]~35_combout ; -wire \address[12]~36 ; -wire \address[13]~37_combout ; +wire \A[0]~39_combout ; +wire \A[1]~13_combout ; +wire \A[1]~14 ; +wire \A[2]~15_combout ; +wire \A[2]~16 ; +wire \A[3]~17_combout ; +wire \A[3]~18 ; +wire \A[4]~19_combout ; +wire \A[4]~20 ; +wire \A[5]~21_combout ; +wire \A[5]~22 ; +wire \A[6]~23_combout ; +wire \A[6]~24 ; +wire \A[7]~25_combout ; +wire \A[7]~26 ; +wire \A[8]~27_combout ; +wire \A[8]~28 ; +wire \A[9]~29_combout ; +wire \A[9]~30 ; +wire \A[10]~31_combout ; +wire \A[10]~32 ; +wire \A[11]~33_combout ; +wire \A[11]~34 ; +wire \A[12]~35_combout ; +wire \A[12]~36 ; +wire \A[13]~37_combout ; +wire \~GND~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; wire [21:0] counter; -wire [13:0] address; +wire [15:0] A; wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -196,21 +183,13 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bu wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -230,7 +209,7 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -243,7 +222,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -256,7 +235,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,7 +248,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -282,7 +261,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -295,7 +274,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -308,7 +287,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -321,7 +300,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -355,7 +334,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N2 +// Location: LCCOMB_X30_Y14_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -372,7 +351,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N3 +// Location: FF_X30_Y14_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -391,7 +370,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N12 +// Location: LCCOMB_X30_Y14_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -409,7 +388,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N13 +// Location: FF_X30_Y14_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -428,7 +407,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 +// Location: LCCOMB_X30_Y14_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -446,7 +425,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N15 +// Location: FF_X30_Y14_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -465,7 +444,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N16 +// Location: LCCOMB_X30_Y14_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -483,7 +462,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N17 +// Location: FF_X30_Y14_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -502,7 +481,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N18 +// Location: LCCOMB_X30_Y14_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -520,7 +499,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N19 +// Location: FF_X30_Y14_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -539,7 +518,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N20 +// Location: LCCOMB_X30_Y14_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -557,7 +536,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N21 +// Location: FF_X30_Y14_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -576,7 +555,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X30_Y14_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -594,7 +573,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N23 +// Location: FF_X30_Y14_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -613,7 +592,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N24 +// Location: LCCOMB_X30_Y14_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -631,7 +610,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N25 +// Location: FF_X30_Y14_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -650,7 +629,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N26 +// Location: LCCOMB_X30_Y14_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -668,7 +647,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N27 +// Location: FF_X30_Y14_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -687,7 +666,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N28 +// Location: LCCOMB_X30_Y14_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -705,7 +684,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N29 +// Location: FF_X30_Y14_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -724,7 +703,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N30 +// Location: LCCOMB_X30_Y14_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -742,7 +721,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N31 +// Location: FF_X30_Y14_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -761,45 +740,28 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N0 +// Location: LCCOMB_X30_Y13_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) // \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(counter[11]), - .datab(gnd), + .dataa(gnd), + .datab(counter[11]), .datac(gnd), .datad(vcc), .cin(\counter[10]~40 ), .combout(\counter[11]~41_combout ), .cout(\counter[11]~42 )); // synopsys translate_off -defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \counter[11]~feeder ( -// Equation(s): -// \counter[11]~feeder_combout = \counter[11]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\counter[11]~41_combout ), - .cin(gnd), - .combout(\counter[11]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \counter[11]~feeder .lut_mask = 16'hFF00; -defparam \counter[11]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N5 +// Location: FF_X30_Y13_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~feeder_combout ), + .d(\counter[11]~41_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -815,7 +777,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N2 +// Location: LCCOMB_X30_Y13_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -833,7 +795,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N3 +// Location: FF_X30_Y13_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -852,25 +814,25 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N4 +// Location: LCCOMB_X30_Y13_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) // \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) - .dataa(gnd), - .datab(counter[13]), + .dataa(counter[13]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[12]~44 ), .combout(\counter[13]~45_combout ), .cout(\counter[13]~46 )); // synopsys translate_off -defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N5 +// Location: FF_X30_Y13_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -889,7 +851,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N6 +// Location: LCCOMB_X30_Y13_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -907,7 +869,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N7 +// Location: FF_X30_Y13_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -926,25 +888,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N8 +// Location: LCCOMB_X30_Y13_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(gnd), - .datab(counter[15]), + .dataa(counter[15]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .lut_mask = 16'hA50A; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N9 +// Location: FF_X30_Y13_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -963,7 +925,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N10 +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -981,7 +943,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N11 +// Location: FF_X30_Y13_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -1000,7 +962,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N12 +// Location: LCCOMB_X30_Y13_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -1018,7 +980,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N13 +// Location: FF_X30_Y13_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -1037,7 +999,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N14 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1055,7 +1017,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N15 +// Location: FF_X30_Y13_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1074,7 +1036,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N16 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1092,7 +1054,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N17 +// Location: FF_X30_Y13_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1111,109 +1073,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N28 -cycloneive_lcell_comb \Equal0~5 ( -// Equation(s): -// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - - .dataa(counter[17]), - .datab(counter[19]), - .datac(counter[18]), - .datad(counter[16]), - .cin(gnd), - .combout(\Equal0~5_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~5 .lut_mask = 16'h0001; -defparam \Equal0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \Equal0~0 ( -// Equation(s): -// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(counter[2]), - .datad(counter[3]), - .cin(gnd), - .combout(\Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~0 .lut_mask = 16'h0001; -defparam \Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) - - .dataa(counter[6]), - .datab(counter[7]), - .datac(counter[5]), - .datad(counter[4]), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \Equal0~2 ( -// Equation(s): -// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - - .dataa(counter[8]), - .datab(counter[11]), - .datac(counter[10]), - .datad(counter[9]), - .cin(gnd), - .combout(\Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~2 .lut_mask = 16'h0001; -defparam \Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \Equal0~3 ( -// Equation(s): -// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - - .dataa(counter[14]), - .datab(counter[13]), - .datac(counter[15]), - .datad(counter[12]), - .cin(gnd), - .combout(\Equal0~3_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~3 .lut_mask = 16'h0001; -defparam \Equal0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \Equal0~4 ( -// Equation(s): -// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - - .dataa(\Equal0~0_combout ), - .datab(\Equal0~1_combout ), - .datac(\Equal0~2_combout ), - .datad(\Equal0~3_combout ), - .cin(gnd), - .combout(\Equal0~4_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~4 .lut_mask = 16'h8000; -defparam \Equal0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 +// Location: LCCOMB_X30_Y13_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1231,7 +1091,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N19 +// Location: FF_X30_Y13_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1250,7 +1110,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N20 +// Location: LCCOMB_X30_Y13_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1267,7 +1127,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N21 +// Location: FF_X30_Y13_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1286,78 +1146,109 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \Equal0~7 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~7_combout = (!counter[21] & !counter[20]) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(counter[20]), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), - .combout(\Equal0~7_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h000F; -defparam \Equal0~7 .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \address[0]~39 ( +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Equal0~5_combout ), - .datab(\Equal0~4_combout ), - .datac(address[0]), - .datad(\Equal0~7_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), - .combout(\address[0]~39_combout ), + .combout(\Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \address[0]~39 .lut_mask = 16'h78F0; -defparam \address[0]~39 .sum_lutc_input = "datac"; +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N31 -dffeas \address[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(address[0]), - .prn(vcc)); -// synopsys translate_off -defparam \address[0] .is_wysiwyg = "true"; -defparam \address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \address[1]~13 ( +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) -// \address[1]~14 = CARRY((address[0] & address[1])) +// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) - .dataa(address[0]), - .datab(address[1]), - .datac(gnd), - .datad(vcc), + .dataa(counter[6]), + .datab(counter[4]), + .datac(counter[7]), + .datad(counter[5]), .cin(gnd), - .combout(\address[1]~13_combout ), - .cout(\address[1]~14 )); + .combout(\Equal0~1_combout ), + .cout()); // synopsys translate_off -defparam \address[1]~13 .lut_mask = 16'h6688; -defparam \address[1]~13 .sum_lutc_input = "datac"; +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N26 +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) + + .dataa(counter[10]), + .datab(counter[9]), + .datac(counter[8]), + .datad(counter[11]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) + + .dataa(counter[14]), + .datab(counter[15]), + .datac(counter[13]), + .datad(counter[12]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): // \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) @@ -1374,489 +1265,27 @@ defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \address[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~13_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[1]), - .prn(vcc)); -// synopsys translate_off -defparam \address[1] .is_wysiwyg = "true"; -defparam \address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \address[2]~15 ( +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \A[0]~39 ( // Equation(s): -// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) -// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) - - .dataa(gnd), - .datab(address[2]), - .datac(gnd), - .datad(vcc), - .cin(\address[1]~14 ), - .combout(\address[2]~15_combout ), - .cout(\address[2]~16 )); -// synopsys translate_off -defparam \address[2]~15 .lut_mask = 16'h3C3F; -defparam \address[2]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N3 -dffeas \address[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[2]), - .prn(vcc)); -// synopsys translate_off -defparam \address[2] .is_wysiwyg = "true"; -defparam \address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \address[3]~17 ( -// Equation(s): -// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) -// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) - - .dataa(gnd), - .datab(address[3]), - .datac(gnd), - .datad(vcc), - .cin(\address[2]~16 ), - .combout(\address[3]~17_combout ), - .cout(\address[3]~18 )); -// synopsys translate_off -defparam \address[3]~17 .lut_mask = 16'hC30C; -defparam \address[3]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N5 -dffeas \address[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[3]~17_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[3]), - .prn(vcc)); -// synopsys translate_off -defparam \address[3] .is_wysiwyg = "true"; -defparam \address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \address[4]~19 ( -// Equation(s): -// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) -// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) - - .dataa(address[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[3]~18 ), - .combout(\address[4]~19_combout ), - .cout(\address[4]~20 )); -// synopsys translate_off -defparam \address[4]~19 .lut_mask = 16'h5A5F; -defparam \address[4]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N7 -dffeas \address[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[4]~19_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[4]), - .prn(vcc)); -// synopsys translate_off -defparam \address[4] .is_wysiwyg = "true"; -defparam \address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \address[5]~21 ( -// Equation(s): -// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) -// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) - - .dataa(gnd), - .datab(address[5]), - .datac(gnd), - .datad(vcc), - .cin(\address[4]~20 ), - .combout(\address[5]~21_combout ), - .cout(\address[5]~22 )); -// synopsys translate_off -defparam \address[5]~21 .lut_mask = 16'hC30C; -defparam \address[5]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \address[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[5]), - .prn(vcc)); -// synopsys translate_off -defparam \address[5] .is_wysiwyg = "true"; -defparam \address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \address[6]~23 ( -// Equation(s): -// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) -// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) - - .dataa(address[6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[5]~22 ), - .combout(\address[6]~23_combout ), - .cout(\address[6]~24 )); -// synopsys translate_off -defparam \address[6]~23 .lut_mask = 16'h5A5F; -defparam \address[6]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \address[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[6]~23_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[6]), - .prn(vcc)); -// synopsys translate_off -defparam \address[6] .is_wysiwyg = "true"; -defparam \address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \address[7]~25 ( -// Equation(s): -// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) -// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) - - .dataa(address[7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[6]~24 ), - .combout(\address[7]~25_combout ), - .cout(\address[7]~26 )); -// synopsys translate_off -defparam \address[7]~25 .lut_mask = 16'hA50A; -defparam \address[7]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N13 -dffeas \address[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[7]~25_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[7]), - .prn(vcc)); -// synopsys translate_off -defparam \address[7] .is_wysiwyg = "true"; -defparam \address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \address[8]~27 ( -// Equation(s): -// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) -// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) - - .dataa(gnd), - .datab(address[8]), - .datac(gnd), - .datad(vcc), - .cin(\address[7]~26 ), - .combout(\address[8]~27_combout ), - .cout(\address[8]~28 )); -// synopsys translate_off -defparam \address[8]~27 .lut_mask = 16'h3C3F; -defparam \address[8]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \address[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[8]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[8]), - .prn(vcc)); -// synopsys translate_off -defparam \address[8] .is_wysiwyg = "true"; -defparam \address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \address[9]~29 ( -// Equation(s): -// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) -// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) - - .dataa(gnd), - .datab(address[9]), - .datac(gnd), - .datad(vcc), - .cin(\address[8]~28 ), - .combout(\address[9]~29_combout ), - .cout(\address[9]~30 )); -// synopsys translate_off -defparam \address[9]~29 .lut_mask = 16'hC30C; -defparam \address[9]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \address[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[9]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[9]), - .prn(vcc)); -// synopsys translate_off -defparam \address[9] .is_wysiwyg = "true"; -defparam \address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \address[10]~31 ( -// Equation(s): -// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) -// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) - - .dataa(gnd), - .datab(address[10]), - .datac(gnd), - .datad(vcc), - .cin(\address[9]~30 ), - .combout(\address[10]~31_combout ), - .cout(\address[10]~32 )); -// synopsys translate_off -defparam \address[10]~31 .lut_mask = 16'h3C3F; -defparam \address[10]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N19 -dffeas \address[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[10]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[10]), - .prn(vcc)); -// synopsys translate_off -defparam \address[10] .is_wysiwyg = "true"; -defparam \address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \address[11]~33 ( -// Equation(s): -// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) -// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) - - .dataa(gnd), - .datab(address[11]), - .datac(gnd), - .datad(vcc), - .cin(\address[10]~32 ), - .combout(\address[11]~33_combout ), - .cout(\address[11]~34 )); -// synopsys translate_off -defparam \address[11]~33 .lut_mask = 16'hC30C; -defparam \address[11]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N21 -dffeas \address[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[11]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[11]), - .prn(vcc)); -// synopsys translate_off -defparam \address[11] .is_wysiwyg = "true"; -defparam \address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \address[12]~35 ( -// Equation(s): -// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) -// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) - - .dataa(address[12]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[11]~34 ), - .combout(\address[12]~35_combout ), - .cout(\address[12]~36 )); -// synopsys translate_off -defparam \address[12]~35 .lut_mask = 16'h5A5F; -defparam \address[12]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \address[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[12]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[12]), - .prn(vcc)); -// synopsys translate_off -defparam \address[12] .is_wysiwyg = "true"; -defparam \address[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \address[13]~37 ( -// Equation(s): -// \address[13]~37_combout = \address[12]~36 $ (!address[13]) +// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(address[13]), - .cin(\address[12]~36 ), - .combout(\address[13]~37_combout ), - .cout()); -// synopsys translate_off -defparam \address[13]~37 .lut_mask = 16'hF00F; -defparam \address[13]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N25 -dffeas \address[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[13]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[13]), - .prn(vcc)); -// synopsys translate_off -defparam \address[13] .is_wysiwyg = "true"; -defparam \address[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(address[13]), + .datac(A[0]), + .datad(\Equal0~6_combout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .combout(\A[0]~39_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[0]~39 .lut_mask = 16'h0FF0; +defparam \A[0]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( +// Location: FF_X30_Y14_N1 +dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .d(\A[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1865,626 +1294,787 @@ dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .q(A[0]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \A[0] .is_wysiwyg = "true"; +defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y18_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \A[1]~13 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~14 = CARRY((A[1] & A[0])) - .dataa(gnd), - .datab(gnd), + .dataa(A[1]), + .datab(A[0]), .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(vcc), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); + .combout(\A[1]~13_combout ), + .cout(\A[1]~14 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[1]~13 .lut_mask = 16'h6688; +defparam \A[1]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N25 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X29_Y14_N1 +dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\A[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(A[1]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \A[1] .is_wysiwyg = "true"; +defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \A[2]~15 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) +// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) +// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), - .cout()); + .datab(A[2]), + .datac(gnd), + .datad(vcc), + .cin(\A[1]~14 ), + .combout(\A[2]~15_combout ), + .cout(\A[2]~16 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +defparam \A[2]~15 .lut_mask = 16'h3C3F; +defparam \A[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X29_Y14_N3 +dffeas \A[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[2]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(A[2]), + .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +defparam \A[2] .is_wysiwyg = "true"; +defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \A[3]~17 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) +// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) +// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .dataa(gnd), + .datab(A[3]), + .datac(gnd), + .datad(vcc), + .cin(\A[2]~16 ), + .combout(\A[3]~17_combout ), + .cout(\A[3]~18 )); +// synopsys translate_off +defparam \A[3]~17 .lut_mask = 16'hC30C; +defparam \A[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \A[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[3]), + .prn(vcc)); +// synopsys translate_off +defparam \A[3] .is_wysiwyg = "true"; +defparam \A[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \A[4]~19 ( +// Equation(s): +// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) +// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) + + .dataa(A[4]), .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(\A[3]~18 ), + .combout(\A[4]~19_combout ), + .cout(\A[4]~20 )); +// synopsys translate_off +defparam \A[4]~19 .lut_mask = 16'h5A5F; +defparam \A[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \A[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[4]), + .prn(vcc)); +// synopsys translate_off +defparam \A[4] .is_wysiwyg = "true"; +defparam \A[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \A[5]~21 ( +// Equation(s): +// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) +// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) + + .dataa(gnd), + .datab(A[5]), + .datac(gnd), + .datad(vcc), + .cin(\A[4]~20 ), + .combout(\A[5]~21_combout ), + .cout(\A[5]~22 )); +// synopsys translate_off +defparam \A[5]~21 .lut_mask = 16'hC30C; +defparam \A[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \A[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[5]), + .prn(vcc)); +// synopsys translate_off +defparam \A[5] .is_wysiwyg = "true"; +defparam \A[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \A[6]~23 ( +// Equation(s): +// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) +// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) + + .dataa(A[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[5]~22 ), + .combout(\A[6]~23_combout ), + .cout(\A[6]~24 )); +// synopsys translate_off +defparam \A[6]~23 .lut_mask = 16'h5A5F; +defparam \A[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \A[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[6]), + .prn(vcc)); +// synopsys translate_off +defparam \A[6] .is_wysiwyg = "true"; +defparam \A[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \A[7]~25 ( +// Equation(s): +// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) +// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) + + .dataa(A[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[6]~24 ), + .combout(\A[7]~25_combout ), + .cout(\A[7]~26 )); +// synopsys translate_off +defparam \A[7]~25 .lut_mask = 16'hA50A; +defparam \A[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \A[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[7]), + .prn(vcc)); +// synopsys translate_off +defparam \A[7] .is_wysiwyg = "true"; +defparam \A[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \A[8]~27 ( +// Equation(s): +// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) +// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) + + .dataa(A[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[7]~26 ), + .combout(\A[8]~27_combout ), + .cout(\A[8]~28 )); +// synopsys translate_off +defparam \A[8]~27 .lut_mask = 16'h5A5F; +defparam \A[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N15 +dffeas \A[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[8]), + .prn(vcc)); +// synopsys translate_off +defparam \A[8] .is_wysiwyg = "true"; +defparam \A[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \A[9]~29 ( +// Equation(s): +// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) +// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) + + .dataa(gnd), + .datab(A[9]), + .datac(gnd), + .datad(vcc), + .cin(\A[8]~28 ), + .combout(\A[9]~29_combout ), + .cout(\A[9]~30 )); +// synopsys translate_off +defparam \A[9]~29 .lut_mask = 16'hC30C; +defparam \A[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \A[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[9]), + .prn(vcc)); +// synopsys translate_off +defparam \A[9] .is_wysiwyg = "true"; +defparam \A[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \A[10]~31 ( +// Equation(s): +// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) +// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) + + .dataa(gnd), + .datab(A[10]), + .datac(gnd), + .datad(vcc), + .cin(\A[9]~30 ), + .combout(\A[10]~31_combout ), + .cout(\A[10]~32 )); +// synopsys translate_off +defparam \A[10]~31 .lut_mask = 16'h3C3F; +defparam \A[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \A[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[10]), + .prn(vcc)); +// synopsys translate_off +defparam \A[10] .is_wysiwyg = "true"; +defparam \A[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \A[11]~33 ( +// Equation(s): +// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) +// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) + + .dataa(gnd), + .datab(A[11]), + .datac(gnd), + .datad(vcc), + .cin(\A[10]~32 ), + .combout(\A[11]~33_combout ), + .cout(\A[11]~34 )); +// synopsys translate_off +defparam \A[11]~33 .lut_mask = 16'hC30C; +defparam \A[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \A[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[11]), + .prn(vcc)); +// synopsys translate_off +defparam \A[11] .is_wysiwyg = "true"; +defparam \A[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \A[12]~35 ( +// Equation(s): +// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) +// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) + + .dataa(A[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[11]~34 ), + .combout(\A[12]~35_combout ), + .cout(\A[12]~36 )); +// synopsys translate_off +defparam \A[12]~35 .lut_mask = 16'h5A5F; +defparam \A[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \A[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[12]), + .prn(vcc)); +// synopsys translate_off +defparam \A[12] .is_wysiwyg = "true"; +defparam \A[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \A[13]~37 ( +// Equation(s): +// \A[13]~37_combout = \A[12]~36 $ (!A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[13]), + .cin(\A[12]~36 ), + .combout(\A[13]~37_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +defparam \A[13]~37 .lut_mask = 16'hF00F; +defparam \A[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \A[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[13]), + .prn(vcc)); +// synopsys translate_off +defparam \A[13] .is_wysiwyg = "true"; +defparam \A[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 +// Location: M9K_X22_Y13_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -2494,14 +2084,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2540,25 +2130,153 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X23_Y18_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), - .cout()); +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2568,14 +2286,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2614,7 +2332,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X22_Y11_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2624,14 +2342,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2670,81 +2388,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(gnd), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2754,14 +2416,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2800,26 +2462,8 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: LCCOMB_X32_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2828,53 +2472,71 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(vcc), .portare(vcc), @@ -2884,14 +2546,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2930,22 +2592,78 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N12 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 9b80f0c..074a56c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:12:28") + (DATE "03/30/2022 13:47:24") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1643:1643:1643) (1694:1694:1694)) + (PORT i (2240:2240:2240) (2288:2288:2288)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1565:1565:1565) (1603:1603:1603)) + (PORT i (2683:2683:2683) (2776:2776:2776)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1737:1737:1737) (1749:1749:1749)) + (PORT i (2672:2672:2672) (2728:2728:2728)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1124:1124:1124) (1166:1166:1166)) + (PORT i (1887:1887:1887) (1922:1922:1922)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1456:1456:1456) (1512:1512:1512)) + (PORT i (2419:2419:2419) (2498:2498:2498)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (2115:2115:2115) (2173:2173:2173)) + (PORT i (1958:1958:1958) (2059:2059:2059)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2428:2428:2428) (2433:2433:2433)) + (PORT i (2348:2348:2348) (2361:2361:2361)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (957:957:957) (1031:1031:1031)) + (PORT i (1275:1275:1275) (1275:1275:1275)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -148,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -177,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -205,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -233,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -247,7 +247,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -261,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -275,7 +275,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (346:346:346)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -289,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -317,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -331,7 +331,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -345,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -359,7 +359,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (341:341:341)) + (PORT dataa (264:264:264) (350:350:350)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -373,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -387,7 +387,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -401,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -415,7 +415,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (340:340:340)) + (PORT dataa (264:264:264) (350:350:350)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -429,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -443,31 +443,21 @@ (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT dataa (704:704:704) (765:765:765)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (318:318:318) (335:335:335)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -495,7 +485,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -509,9 +499,9 @@ (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (335:335:335)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (403:403:403) (479:479:479)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -523,7 +513,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -551,7 +541,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -565,9 +555,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (403:403:403) (479:479:479)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -579,7 +569,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -607,7 +597,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -635,7 +625,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -663,7 +653,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -691,7 +681,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -700,102 +690,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (252:252:252) (336:336:336)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (226:226:226) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (224:224:224) (302:302:302)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (251:251:251) (337:337:337)) - (PORT datac (381:381:381) (440:440:440)) - (PORT datad (225:225:225) (297:297:297)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (347:347:347)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (226:226:226) (308:308:308)) - (PORT datad (228:228:228) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (370:370:370)) - (PORT datab (345:345:345) (370:370:370)) - (PORT datac (335:335:335) (354:354:354)) - (PORT datad (589:589:589) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE counter\[20\]\~59) @@ -815,7 +709,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -840,7 +734,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -851,11 +745,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datac (669:669:669) (728:728:728)) - (PORT datad (646:646:646) (700:700:700)) + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -863,44 +761,80 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~39) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (663:663:663)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (330:330:330) (347:347:347)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1877:1877:1877)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (381:381:381) (442:442:442)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~13) + (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (268:268:268) (356:356:356)) - (PORT datab (261:261:261) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (447:447:447) (515:515:515)) + (PORT datab (406:406:406) (480:480:480)) + (PORT datac (566:566:566) (611:611:611)) + (PORT datad (576:576:576) (620:620:620)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (265:265:265) (348:348:348)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (416:416:416)) + (PORT datab (345:345:345) (380:380:380)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (640:640:640) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -910,10 +844,10 @@ (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (763:763:763)) - (PORT datab (674:674:674) (730:730:730)) - (PORT datac (613:613:613) (625:625:625)) - (PORT datad (181:181:181) (210:210:210)) + (PORT dataa (888:888:888) (955:955:955)) + (PORT datab (926:926:926) (973:973:973)) + (PORT datac (615:615:615) (635:635:635)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -922,13 +856,53 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[0\]\~39) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT datad (330:330:330) (344:344:344)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (522:522:522)) + (PORT datab (618:618:618) (683:683:683)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -939,7 +913,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~15) + (INSTANCE A\[2\]\~15) (DELAY (ABSOLUTE (PORT datab (261:261:261) (343:343:343)) @@ -953,12 +927,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -969,10 +943,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[3\]\~17) + (INSTANCE A\[3\]\~17) (DELAY (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -983,12 +957,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[3\]) + (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -999,7 +973,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[4\]\~19) + (INSTANCE A\[4\]\~19) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (351:351:351)) @@ -1013,12 +987,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[4\]) + (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1029,7 +1003,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[5\]\~21) + (INSTANCE A\[5\]\~21) (DELAY (ABSOLUTE (PORT datab (263:263:263) (345:345:345)) @@ -1043,12 +1017,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[5\]) + (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1059,7 +1033,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[6\]\~23) + (INSTANCE A\[6\]\~23) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (353:353:353)) @@ -1073,12 +1047,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[6\]) + (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1089,7 +1063,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[7\]\~25) + (INSTANCE A\[7\]\~25) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (353:353:353)) @@ -1103,12 +1077,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[7\]) + (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1119,7 +1093,67 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[8\]\~27) + (INSTANCE A\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (480:480:480)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[10\]\~31) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1133,12 +1167,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[8\]) + (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1149,7 +1183,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[9\]\~29) + (INSTANCE A\[11\]\~33) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1163,12 +1197,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[9\]) + (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1179,67 +1213,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[10\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[11\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[12\]\~35) + (INSTANCE A\[12\]\~35) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (352:352:352)) @@ -1253,12 +1227,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[12\]) + (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1269,7 +1243,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[13\]\~37) + (INSTANCE A\[13\]\~37) (DELAY (ABSOLUTE (PORT datad (258:258:258) (327:327:327)) @@ -1280,12 +1254,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[13\]) + (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1294,13 +1268,959 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1043:1043:1043) (1097:1097:1097)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1047:1047:1047) (1146:1146:1146)) + (PORT d[1] (1492:1492:1492) (1562:1562:1562)) + (PORT d[2] (954:954:954) (1036:1036:1036)) + (PORT d[3] (1018:1018:1018) (1075:1075:1075)) + (PORT d[4] (1018:1018:1018) (1075:1075:1075)) + (PORT d[5] (783:783:783) (838:838:838)) + (PORT d[6] (783:783:783) (838:838:838)) + (PORT d[7] (783:783:783) (838:838:838)) + (PORT d[8] (783:783:783) (838:838:838)) + (PORT d[9] (783:783:783) (838:838:838)) + (PORT d[10] (783:783:783) (838:838:838)) + (PORT d[11] (783:783:783) (838:838:838)) + (PORT d[12] (783:783:783) (838:838:838)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1809:1809:1809)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1102:1102:1102)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1127:1127:1127)) + (PORT d[1] (1493:1493:1493) (1562:1562:1562)) + (PORT d[2] (979:979:979) (1058:1058:1058)) + (PORT d[3] (1250:1250:1250) (1312:1312:1312)) + (PORT d[4] (967:967:967) (1025:1025:1025)) + (PORT d[5] (1558:1558:1558) (1643:1643:1643)) + (PORT d[6] (1237:1237:1237) (1323:1323:1323)) + (PORT d[7] (1284:1284:1284) (1363:1363:1363)) + (PORT d[8] (1214:1214:1214) (1273:1273:1273)) + (PORT d[9] (1235:1235:1235) (1302:1302:1302)) + (PORT d[10] (1250:1250:1250) (1318:1318:1318)) + (PORT d[11] (1232:1232:1232) (1314:1314:1314)) + (PORT d[12] (1287:1287:1287) (1358:1358:1358)) + (PORT clk (1819:1819:1819) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1815:1815:1815)) + (PORT d[0] (903:903:903) (890:890:890)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1006:1006:1006) (1061:1061:1061)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1030:1030:1030) (1132:1132:1132)) + (PORT d[1] (1194:1194:1194) (1270:1270:1270)) + (PORT d[2] (957:957:957) (1039:1039:1039)) + (PORT d[3] (1025:1025:1025) (1086:1086:1086)) + (PORT d[4] (1025:1025:1025) (1086:1086:1086)) + (PORT d[5] (813:813:813) (881:881:881)) + (PORT d[6] (813:813:813) (881:881:881)) + (PORT d[7] (813:813:813) (881:881:881)) + (PORT d[8] (813:813:813) (881:881:881)) + (PORT d[9] (813:813:813) (881:881:881)) + (PORT d[10] (813:813:813) (881:881:881)) + (PORT d[11] (813:813:813) (881:881:881)) + (PORT d[12] (813:813:813) (881:881:881)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1066:1066:1066)) + (PORT clk (1821:1821:1821) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1054:1054:1054) (1156:1156:1156)) + (PORT d[1] (960:960:960) (1039:1039:1039)) + (PORT d[2] (1276:1276:1276) (1350:1350:1350)) + (PORT d[3] (1249:1249:1249) (1279:1279:1279)) + (PORT d[4] (941:941:941) (1014:1014:1014)) + (PORT d[5] (1553:1553:1553) (1633:1633:1633)) + (PORT d[6] (1275:1275:1275) (1334:1334:1334)) + (PORT d[7] (1286:1286:1286) (1364:1364:1364)) + (PORT d[8] (1442:1442:1442) (1487:1487:1487)) + (PORT d[9] (1239:1239:1239) (1309:1309:1309)) + (PORT d[10] (1259:1259:1259) (1333:1333:1333)) + (PORT d[11] (1243:1243:1243) (1305:1305:1305)) + (PORT d[12] (1271:1271:1271) (1318:1318:1318)) + (PORT clk (1817:1817:1817) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1814:1814:1814)) + (PORT d[0] (908:908:908) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1352:1352:1352) (1400:1400:1400)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1071:1071:1071) (1146:1146:1146)) + (PORT d[1] (935:935:935) (1004:1004:1004)) + (PORT d[2] (1531:1531:1531) (1621:1621:1621)) + (PORT d[3] (1349:1349:1349) (1401:1401:1401)) + (PORT d[4] (1349:1349:1349) (1401:1401:1401)) + (PORT d[5] (773:773:773) (814:814:814)) + (PORT d[6] (773:773:773) (814:814:814)) + (PORT d[7] (773:773:773) (814:814:814)) + (PORT d[8] (773:773:773) (814:814:814)) + (PORT d[9] (773:773:773) (814:814:814)) + (PORT d[10] (773:773:773) (814:814:814)) + (PORT d[11] (773:773:773) (814:814:814)) + (PORT d[12] (773:773:773) (814:814:814)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1357:1357:1357) (1405:1405:1405)) + (PORT clk (1824:1824:1824) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1049:1049:1049) (1122:1122:1122)) + (PORT d[1] (1503:1503:1503) (1591:1591:1591)) + (PORT d[2] (917:917:917) (979:979:979)) + (PORT d[3] (1464:1464:1464) (1521:1521:1521)) + (PORT d[4] (935:935:935) (996:996:996)) + (PORT d[5] (1058:1058:1058) (1128:1128:1128)) + (PORT d[6] (1250:1250:1250) (1319:1319:1319)) + (PORT d[7] (1047:1047:1047) (1105:1105:1105)) + (PORT d[8] (1486:1486:1486) (1542:1542:1542)) + (PORT d[9] (1254:1254:1254) (1312:1312:1312)) + (PORT d[10] (1242:1242:1242) (1297:1297:1297)) + (PORT d[11] (1250:1250:1250) (1319:1319:1319)) + (PORT d[12] (1251:1251:1251) (1299:1299:1299)) + (PORT clk (1820:1820:1820) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1817:1817:1817)) + (PORT d[0] (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1362:1362:1362) (1429:1429:1429)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (762:762:762) (824:824:824)) + (PORT d[1] (644:644:644) (706:706:706)) + (PORT d[2] (1543:1543:1543) (1614:1614:1614)) + (PORT d[3] (664:664:664) (693:693:693)) + (PORT d[4] (664:664:664) (693:693:693)) + (PORT d[5] (484:484:484) (522:522:522)) + (PORT d[6] (484:484:484) (522:522:522)) + (PORT d[7] (484:484:484) (522:522:522)) + (PORT d[8] (484:484:484) (522:522:522)) + (PORT d[9] (484:484:484) (522:522:522)) + (PORT d[10] (484:484:484) (522:522:522)) + (PORT d[11] (484:484:484) (522:522:522)) + (PORT d[12] (484:484:484) (522:522:522)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1367:1367:1367) (1434:1434:1434)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (735:735:735) (812:812:812)) + (PORT d[1] (1534:1534:1534) (1599:1599:1599)) + (PORT d[2] (1545:1545:1545) (1615:1615:1615)) + (PORT d[3] (659:659:659) (709:709:709)) + (PORT d[4] (664:664:664) (725:725:725)) + (PORT d[5] (722:722:722) (794:794:794)) + (PORT d[6] (766:766:766) (839:839:839)) + (PORT d[7] (749:749:749) (827:827:827)) + (PORT d[8] (1517:1517:1517) (1590:1590:1590)) + (PORT d[9] (761:761:761) (822:822:822)) + (PORT d[10] (979:979:979) (1037:1037:1037)) + (PORT d[11] (734:734:734) (803:803:803)) + (PORT d[12] (940:940:940) (991:991:991)) + (PORT clk (1821:1821:1821) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT d[0] (628:628:628) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1580:1580:1580) (1693:1693:1693)) + (PORT d[1] (1272:1272:1272) (1354:1354:1354)) + (PORT d[2] (1245:1245:1245) (1308:1308:1308)) + (PORT d[3] (1263:1263:1263) (1339:1339:1339)) + (PORT d[4] (1283:1283:1283) (1370:1370:1370)) + (PORT d[5] (1569:1569:1569) (1701:1701:1701)) + (PORT d[6] (1243:1243:1243) (1329:1329:1329)) + (PORT d[7] (1231:1231:1231) (1310:1310:1310)) + (PORT d[8] (1267:1267:1267) (1363:1363:1363)) + (PORT d[9] (1273:1273:1273) (1361:1361:1361)) + (PORT d[10] (1275:1275:1275) (1366:1366:1366)) + (PORT d[11] (1259:1259:1259) (1344:1344:1344)) + (PORT d[12] (1532:1532:1532) (1614:1614:1614)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1172:1172:1172) (1188:1188:1188)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1320:1320:1320) (1440:1440:1440)) + (PORT d[1] (1259:1259:1259) (1353:1353:1353)) + (PORT d[2] (1264:1264:1264) (1323:1323:1323)) + (PORT d[3] (1324:1324:1324) (1419:1419:1419)) + (PORT d[4] (1316:1316:1316) (1418:1418:1418)) + (PORT d[5] (1564:1564:1564) (1691:1691:1691)) + (PORT d[6] (1229:1229:1229) (1326:1326:1326)) + (PORT d[7] (1239:1239:1239) (1332:1332:1332)) + (PORT d[8] (1280:1280:1280) (1393:1393:1393)) + (PORT d[9] (1254:1254:1254) (1351:1351:1351)) + (PORT d[10] (1258:1258:1258) (1357:1357:1357)) + (PORT d[11] (1267:1267:1267) (1367:1367:1367)) + (PORT d[12] (1266:1266:1266) (1351:1351:1351)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1215:1215:1215) (1202:1202:1202)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (428:428:428) (485:485:485)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (643:643:643) (706:706:706)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -1323,7 +2243,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) + (PORT datad (219:219:219) (289:289:289)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1342,1064 +2262,38 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1232:1232:1232) (1314:1314:1314)) - (PORT d[1] (1273:1273:1273) (1381:1381:1381)) - (PORT d[2] (1342:1342:1342) (1456:1456:1456)) - (PORT d[3] (1317:1317:1317) (1435:1435:1435)) - (PORT d[4] (1249:1249:1249) (1341:1341:1341)) - (PORT d[5] (1362:1362:1362) (1458:1458:1458)) - (PORT d[6] (1704:1704:1704) (1869:1869:1869)) - (PORT d[7] (1310:1310:1310) (1434:1434:1434)) - (PORT d[8] (1316:1316:1316) (1419:1419:1419)) - (PORT d[9] (1359:1359:1359) (1447:1447:1447)) - (PORT d[10] (1320:1320:1320) (1425:1425:1425)) - (PORT d[11] (1570:1570:1570) (1654:1654:1654)) - (PORT d[12] (1289:1289:1289) (1390:1390:1390)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (1167:1167:1167) (1189:1189:1189)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1246:1246:1246)) - (PORT d[1] (973:973:973) (1069:1069:1069)) - (PORT d[2] (1034:1034:1034) (1138:1138:1138)) - (PORT d[3] (1341:1341:1341) (1439:1439:1439)) - (PORT d[4] (1248:1248:1248) (1333:1333:1333)) - (PORT d[5] (1325:1325:1325) (1408:1408:1408)) - (PORT d[6] (1491:1491:1491) (1664:1664:1664)) - (PORT d[7] (1263:1263:1263) (1339:1339:1339)) - (PORT d[8] (1326:1326:1326) (1417:1417:1417)) - (PORT d[9] (1388:1388:1388) (1482:1482:1482)) - (PORT d[10] (1305:1305:1305) (1406:1406:1406)) - (PORT d[11] (1274:1274:1274) (1349:1349:1349)) - (PORT d[12] (1340:1340:1340) (1438:1438:1438)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (954:954:954) (925:925:925)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) (DELAY (ABSOLUTE - (PORT datab (956:956:956) (1072:1072:1072)) - (PORT datac (880:880:880) (883:883:883)) - (PORT datad (605:605:605) (612:612:612)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1457:1457:1457) (1535:1535:1535)) - (PORT d[1] (1538:1538:1538) (1599:1599:1599)) - (PORT d[2] (1565:1565:1565) (1669:1669:1669)) - (PORT d[3] (1248:1248:1248) (1294:1294:1294)) - (PORT d[4] (1607:1607:1607) (1738:1738:1738)) - (PORT d[5] (1904:1904:1904) (2043:2043:2043)) - (PORT d[6] (1250:1250:1250) (1306:1306:1306)) - (PORT d[7] (1340:1340:1340) (1441:1441:1441)) - (PORT d[8] (1887:1887:1887) (2029:2029:2029)) - (PORT d[9] (1230:1230:1230) (1303:1303:1303)) - (PORT d[10] (1415:1415:1415) (1517:1517:1517)) - (PORT d[11] (1208:1208:1208) (1273:1273:1273)) - (PORT d[12] (1256:1256:1256) (1338:1338:1338)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1141:1141:1141) (1128:1128:1128)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1500:1500:1500) (1594:1594:1594)) - (PORT d[1] (1355:1355:1355) (1470:1470:1470)) - (PORT d[2] (1591:1591:1591) (1703:1703:1703)) - (PORT d[3] (1336:1336:1336) (1417:1417:1417)) - (PORT d[4] (1313:1313:1313) (1422:1422:1422)) - (PORT d[5] (1595:1595:1595) (1733:1733:1733)) - (PORT d[6] (1268:1268:1268) (1373:1373:1373)) - (PORT d[7] (1255:1255:1255) (1355:1355:1355)) - (PORT d[8] (1615:1615:1615) (1750:1750:1750)) - (PORT d[9] (1326:1326:1326) (1421:1421:1421)) - (PORT d[10] (1812:1812:1812) (1937:1937:1937)) - (PORT d[11] (1293:1293:1293) (1402:1402:1402)) - (PORT d[12] (1561:1561:1561) (1676:1676:1676)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1207:1207:1207) (1256:1256:1256)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (652:652:652)) - (PORT datac (877:877:877) (907:907:907)) - (PORT datad (1342:1342:1342) (1396:1396:1396)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1238:1238:1238) (1323:1323:1323)) - (PORT d[1] (1282:1282:1282) (1374:1374:1374)) - (PORT d[2] (1603:1603:1603) (1716:1716:1716)) - (PORT d[3] (1381:1381:1381) (1467:1467:1467)) - (PORT d[4] (1282:1282:1282) (1376:1376:1376)) - (PORT d[5] (1277:1277:1277) (1395:1395:1395)) - (PORT d[6] (1716:1716:1716) (1879:1879:1879)) - (PORT d[7] (1344:1344:1344) (1433:1433:1433)) - (PORT d[8] (1329:1329:1329) (1433:1433:1433)) - (PORT d[9] (1412:1412:1412) (1507:1507:1507)) - (PORT d[10] (1764:1764:1764) (1843:1843:1843)) - (PORT d[11] (1578:1578:1578) (1656:1656:1656)) - (PORT d[12] (1322:1322:1322) (1422:1422:1422)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1242:1242:1242) (1194:1194:1194)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (1054:1054:1054)) - (PORT d[1] (1258:1258:1258) (1343:1343:1343)) - (PORT d[2] (1047:1047:1047) (1135:1135:1135)) - (PORT d[3] (1074:1074:1074) (1167:1167:1167)) - (PORT d[4] (966:966:966) (1059:1059:1059)) - (PORT d[5] (1239:1239:1239) (1332:1332:1332)) - (PORT d[6] (1463:1463:1463) (1631:1631:1631)) - (PORT d[7] (1262:1262:1262) (1338:1338:1338)) - (PORT d[8] (1053:1053:1053) (1156:1156:1156)) - (PORT d[9] (1100:1100:1100) (1206:1206:1206)) - (PORT d[10] (1512:1512:1512) (1581:1581:1581)) - (PORT d[11] (1273:1273:1273) (1348:1348:1348)) - (PORT d[12] (1313:1313:1313) (1405:1405:1405)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (924:924:924) (953:953:953)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (980:980:980) (1094:1094:1094)) - (PORT datac (902:902:902) (940:940:940)) - (PORT datad (596:596:596) (601:601:601)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (988:988:988)) - (PORT d[1] (979:979:979) (1053:1053:1053)) - (PORT d[2] (1080:1080:1080) (1156:1156:1156)) - (PORT d[3] (1058:1058:1058) (1130:1130:1130)) - (PORT d[4] (956:956:956) (1028:1028:1028)) - (PORT d[5] (1006:1006:1006) (1083:1083:1083)) - (PORT d[6] (1424:1424:1424) (1563:1563:1563)) - (PORT d[7] (1240:1240:1240) (1316:1316:1316)) - (PORT d[8] (1625:1625:1625) (1738:1738:1738)) - (PORT d[9] (1086:1086:1086) (1162:1162:1162)) - (PORT d[10] (1042:1042:1042) (1125:1125:1125)) - (PORT d[11] (1300:1300:1300) (1361:1361:1361)) - (PORT d[12] (1299:1299:1299) (1370:1370:1370)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (908:908:908) (912:912:912)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1205:1205:1205) (1260:1260:1260)) - (PORT d[1] (651:651:651) (711:711:711)) - (PORT d[2] (713:713:713) (781:781:781)) - (PORT d[3] (760:760:760) (830:830:830)) - (PORT d[4] (659:659:659) (721:721:721)) - (PORT d[5] (734:734:734) (814:814:814)) - (PORT d[6] (761:761:761) (832:832:832)) - (PORT d[7] (740:740:740) (819:819:819)) - (PORT d[8] (756:756:756) (828:828:828)) - (PORT d[9] (769:769:769) (847:847:847)) - (PORT d[10] (1226:1226:1226) (1292:1292:1292)) - (PORT d[11] (741:741:741) (813:813:813)) - (PORT d[12] (751:751:751) (826:826:826)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (642:642:642) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (939:939:939)) - (PORT datac (648:648:648) (723:723:723)) - (PORT datad (603:603:603) (610:610:610)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (628:628:628) (637:637:637)) + (PORT datac (922:922:922) (922:922:922)) + (PORT datad (973:973:973) (1040:1040:1040)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1471:1471:1471) (1551:1551:1551)) - (PORT d[1] (1529:1529:1529) (1590:1590:1590)) - (PORT d[2] (1557:1557:1557) (1660:1660:1660)) - (PORT d[3] (988:988:988) (1045:1045:1045)) - (PORT d[4] (976:976:976) (1062:1062:1062)) - (PORT d[5] (1604:1604:1604) (1749:1749:1749)) - (PORT d[6] (996:996:996) (1079:1079:1079)) - (PORT d[7] (948:948:948) (1026:1026:1026)) - (PORT d[8] (1601:1601:1601) (1742:1742:1742)) - (PORT d[9] (998:998:998) (1064:1064:1064)) - (PORT d[10] (979:979:979) (1057:1057:1057)) - (PORT d[11] (958:958:958) (1040:1040:1040)) - (PORT d[12] (969:969:969) (1047:1047:1047)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (904:904:904) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1219:1219:1219) (1307:1307:1307)) - (PORT d[1] (1255:1255:1255) (1323:1323:1323)) - (PORT d[2] (1279:1279:1279) (1381:1381:1381)) - (PORT d[3] (1279:1279:1279) (1328:1328:1328)) - (PORT d[4] (1603:1603:1603) (1733:1733:1733)) - (PORT d[5] (1603:1603:1603) (1748:1748:1748)) - (PORT d[6] (1281:1281:1281) (1369:1369:1369)) - (PORT d[7] (1245:1245:1245) (1325:1325:1325)) - (PORT d[8] (1600:1600:1600) (1741:1741:1741)) - (PORT d[9] (1266:1266:1266) (1335:1335:1335)) - (PORT d[10] (1838:1838:1838) (1967:1967:1967)) - (PORT d[11] (1283:1283:1283) (1373:1373:1373)) - (PORT d[12] (1245:1245:1245) (1330:1330:1330)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1151:1151:1151) (1179:1179:1179)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (640:640:640) (651:651:651)) - (PORT datac (859:859:859) (855:855:855)) - (PORT datad (794:794:794) (853:853:853)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1508:1508:1508) (1612:1612:1612)) - (PORT d[1] (1896:1896:1896) (2041:2041:2041)) - (PORT d[2] (1251:1251:1251) (1359:1359:1359)) - (PORT d[3] (1319:1319:1319) (1368:1368:1368)) - (PORT d[4] (1294:1294:1294) (1407:1407:1407)) - (PORT d[5] (1248:1248:1248) (1360:1360:1360)) - (PORT d[6] (1297:1297:1297) (1411:1411:1411)) - (PORT d[7] (1260:1260:1260) (1366:1366:1366)) - (PORT d[8] (1608:1608:1608) (1726:1726:1726)) - (PORT d[9] (1309:1309:1309) (1408:1408:1408)) - (PORT d[10] (1860:1860:1860) (1990:1990:1990)) - (PORT d[11] (1271:1271:1271) (1381:1381:1381)) - (PORT d[12] (1527:1527:1527) (1637:1637:1637)) + (PORT d[0] (1588:1588:1588) (1696:1696:1696)) + (PORT d[1] (980:980:980) (1067:1067:1067)) + (PORT d[2] (995:995:995) (1068:1068:1068)) + (PORT d[3] (1044:1044:1044) (1123:1123:1123)) + (PORT d[4] (975:975:975) (1061:1061:1061)) + (PORT d[5] (1570:1570:1570) (1702:1702:1702)) + (PORT d[6] (974:974:974) (1057:1057:1057)) + (PORT d[7] (950:950:950) (1029:1029:1029)) + (PORT d[8] (1007:1007:1007) (1107:1107:1107)) + (PORT d[9] (1511:1511:1511) (1583:1583:1583)) + (PORT d[10] (1476:1476:1476) (1552:1552:1552)) + (PORT d[11] (949:949:949) (1029:1029:1029)) + (PORT d[12] (993:993:993) (1056:1056:1056)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2413,7 +2307,7 @@ (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1193:1193:1193) (1239:1239:1239)) + (PORT d[0] (897:897:897) (921:921:921)) ) ) ) @@ -2484,20 +2378,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1667:1667:1667)) - (PORT d[1] (1626:1626:1626) (1776:1776:1776)) - (PORT d[2] (1557:1557:1557) (1668:1668:1668)) - (PORT d[3] (1644:1644:1644) (1709:1709:1709)) - (PORT d[4] (1593:1593:1593) (1715:1715:1715)) - (PORT d[5] (1575:1575:1575) (1680:1680:1680)) - (PORT d[6] (1565:1565:1565) (1670:1670:1670)) - (PORT d[7] (1531:1531:1531) (1632:1632:1632)) - (PORT d[8] (1555:1555:1555) (1659:1659:1659)) - (PORT d[9] (1587:1587:1587) (1682:1682:1682)) - (PORT d[10] (1533:1533:1533) (1638:1638:1638)) - (PORT d[11] (1559:1559:1559) (1667:1667:1667)) - (PORT d[12] (1527:1527:1527) (1639:1639:1639)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1251:1251:1251) (1346:1346:1346)) + (PORT d[1] (1263:1263:1263) (1359:1359:1359)) + (PORT d[2] (1230:1230:1230) (1312:1312:1312)) + (PORT d[3] (1305:1305:1305) (1378:1378:1378)) + (PORT d[4] (1268:1268:1268) (1374:1374:1374)) + (PORT d[5] (1558:1558:1558) (1661:1661:1661)) + (PORT d[6] (1255:1255:1255) (1359:1359:1359)) + (PORT d[7] (1243:1243:1243) (1338:1338:1338)) + (PORT d[8] (1284:1284:1284) (1400:1400:1400)) + (PORT d[9] (1257:1257:1257) (1358:1358:1358)) + (PORT d[10] (1261:1261:1261) (1362:1362:1362)) + (PORT d[11] (1244:1244:1244) (1341:1341:1341)) + (PORT d[12] (1513:1513:1513) (1597:1597:1597)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -2509,8 +2403,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1489:1489:1489) (1442:1442:1442)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (1181:1181:1181) (1146:1146:1146)) ) ) ) @@ -2519,7 +2413,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2529,7 +2423,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) + (PORT clk (1807:1807:1807) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2543,7 +2437,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (992:992:992) (997:997:997)) ) ) ) @@ -2552,7 +2446,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) @@ -2561,7 +2455,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2571,22 +2465,119 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT datab (626:626:626) (635:635:635)) - (PORT datac (909:909:909) (911:911:911)) - (PORT datad (1120:1120:1120) (1222:1222:1222)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (627:627:627) (648:648:648)) + (PORT datab (722:722:722) (791:791:791)) + (PORT datac (902:902:902) (941:941:941)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1869:1869:1869) (2011:2011:2011)) + (PORT d[1] (1219:1219:1219) (1293:1293:1293)) + (PORT d[2] (1262:1262:1262) (1328:1328:1328)) + (PORT d[3] (1315:1315:1315) (1385:1385:1385)) + (PORT d[4] (1268:1268:1268) (1345:1345:1345)) + (PORT d[5] (1878:1878:1878) (2013:2013:2013)) + (PORT d[6] (1241:1241:1241) (1311:1311:1311)) + (PORT d[7] (1353:1353:1353) (1455:1455:1455)) + (PORT d[8] (1215:1215:1215) (1306:1306:1306)) + (PORT d[9] (1254:1254:1254) (1335:1335:1335)) + (PORT d[10] (1270:1270:1270) (1354:1354:1354)) + (PORT d[11] (1212:1212:1212) (1279:1279:1279)) + (PORT d[12] (1262:1262:1262) (1346:1346:1346)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1161:1161:1161) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -2595,19 +2586,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (965:965:965) (1030:1030:1030)) - (PORT d[1] (1241:1241:1241) (1329:1329:1329)) - (PORT d[2] (1056:1056:1056) (1157:1157:1157)) - (PORT d[3] (1088:1088:1088) (1177:1177:1177)) - (PORT d[4] (990:990:990) (1084:1084:1084)) - (PORT d[5] (1067:1067:1067) (1137:1137:1137)) - (PORT d[6] (1434:1434:1434) (1593:1593:1593)) - (PORT d[7] (1278:1278:1278) (1382:1382:1382)) - (PORT d[8] (1052:1052:1052) (1156:1156:1156)) - (PORT d[9] (1060:1060:1060) (1159:1159:1159)) - (PORT d[10] (1022:1022:1022) (1126:1126:1126)) - (PORT d[11] (1256:1256:1256) (1351:1351:1351)) - (PORT d[12] (1309:1309:1309) (1400:1400:1400)) + (PORT d[0] (767:767:767) (837:837:837)) + (PORT d[1] (644:644:644) (707:707:707)) + (PORT d[2] (1522:1522:1522) (1591:1591:1591)) + (PORT d[3] (1232:1232:1232) (1276:1276:1276)) + (PORT d[4] (948:948:948) (1009:1009:1009)) + (PORT d[5] (1053:1053:1053) (1132:1132:1132)) + (PORT d[6] (1198:1198:1198) (1268:1268:1268)) + (PORT d[7] (1251:1251:1251) (1321:1321:1321)) + (PORT d[8] (1492:1492:1492) (1563:1563:1563)) + (PORT d[9] (1256:1256:1256) (1307:1307:1307)) + (PORT d[10] (1239:1239:1239) (1292:1292:1292)) + (PORT d[11] (1213:1213:1213) (1275:1275:1275)) + (PORT d[12] (1242:1242:1242) (1308:1308:1308)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -2621,7 +2612,7 @@ (DELAY (ABSOLUTE (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (918:918:918) (941:941:941)) + (PORT d[0] (890:890:890) (887:887:887)) ) ) ) @@ -2687,233 +2678,39 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (921:921:921) (982:982:982)) - (PORT d[1] (652:652:652) (711:711:711)) - (PORT d[2] (1323:1323:1323) (1400:1400:1400)) - (PORT d[3] (1338:1338:1338) (1452:1452:1452)) - (PORT d[4] (929:929:929) (988:988:988)) - (PORT d[5] (1048:1048:1048) (1131:1131:1131)) - (PORT d[6] (1394:1394:1394) (1522:1522:1522)) - (PORT d[7] (1240:1240:1240) (1309:1309:1309)) - (PORT d[8] (1638:1638:1638) (1740:1740:1740)) - (PORT d[9] (1048:1048:1048) (1110:1110:1110)) - (PORT d[10] (1044:1044:1044) (1103:1103:1103)) - (PORT d[11] (1204:1204:1204) (1263:1263:1263)) - (PORT d[12] (1258:1258:1258) (1304:1304:1304)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (887:887:887) (888:888:888)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (743:743:743)) - (PORT datac (917:917:917) (955:955:955)) - (PORT datad (347:347:347) (362:362:362)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (938:938:938) (1009:1009:1009)) + (PORT datac (597:597:597) (600:600:600)) + (PORT datad (1037:1037:1037) (1036:1036:1036)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1471:1471:1471) (1578:1578:1578)) - (PORT d[1] (1888:1888:1888) (2030:2030:2030)) - (PORT d[2] (1880:1880:1880) (2006:2006:2006)) - (PORT d[3] (1371:1371:1371) (1434:1434:1434)) - (PORT d[4] (1886:1886:1886) (2001:2001:2001)) - (PORT d[5] (1321:1321:1321) (1439:1439:1439)) - (PORT d[6] (1325:1325:1325) (1443:1443:1443)) - (PORT d[7] (1261:1261:1261) (1367:1367:1367)) - (PORT d[8] (1312:1312:1312) (1427:1427:1427)) - (PORT d[9] (1283:1283:1283) (1377:1377:1377)) - (PORT d[10] (1803:1803:1803) (1907:1907:1907)) - (PORT d[11] (1272:1272:1272) (1382:1382:1382)) - (PORT d[12] (1256:1256:1256) (1366:1366:1366)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1266:1266:1266) (1210:1210:1210)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1817:1817:1817) (1923:1923:1923)) - (PORT d[1] (1607:1607:1607) (1705:1705:1705)) - (PORT d[2] (1576:1576:1576) (1716:1716:1716)) - (PORT d[3] (1616:1616:1616) (1679:1679:1679)) - (PORT d[4] (1594:1594:1594) (1718:1718:1718)) - (PORT d[5] (1563:1563:1563) (1701:1701:1701)) - (PORT d[6] (1548:1548:1548) (1655:1655:1655)) - (PORT d[7] (1539:1539:1539) (1642:1642:1642)) - (PORT d[8] (1532:1532:1532) (1634:1634:1634)) - (PORT d[9] (1589:1589:1589) (1705:1705:1705)) - (PORT d[10] (1503:1503:1503) (1601:1601:1601)) - (PORT d[11] (1561:1561:1561) (1686:1686:1686)) - (PORT d[12] (1531:1531:1531) (1649:1649:1649)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1536:1536:1536) (1641:1641:1641)) + (PORT d[1] (1285:1285:1285) (1385:1385:1385)) + (PORT d[2] (1257:1257:1257) (1341:1341:1341)) + (PORT d[3] (1362:1362:1362) (1438:1438:1438)) + (PORT d[4] (1567:1567:1567) (1669:1669:1669)) + (PORT d[5] (1299:1299:1299) (1410:1410:1410)) + (PORT d[6] (1283:1283:1283) (1391:1391:1391)) + (PORT d[7] (1243:1243:1243) (1339:1339:1339)) + (PORT d[8] (1257:1257:1257) (1369:1369:1369)) + (PORT d[9] (1285:1285:1285) (1390:1390:1390)) + (PORT d[10] (1289:1289:1289) (1395:1395:1395)) + (PORT d[11] (1244:1244:1244) (1342:1342:1342)) + (PORT d[12] (1238:1238:1238) (1316:1316:1316)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -2925,8 +2722,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1872:1872:1872)) - (PORT d[0] (1495:1495:1495) (1543:1543:1543)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (1140:1140:1140) (1166:1166:1166)) ) ) ) @@ -2935,7 +2732,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT clk (1843:1843:1843) (1870:1870:1870)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2945,7 +2742,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1805:1805:1805) (1832:1832:1832)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2959,7 +2756,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (990:990:990) (995:995:995)) ) ) ) @@ -2968,7 +2765,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) ) ) ) @@ -2977,7 +2774,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2987,21 +2784,118 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1019:1019:1019) (1118:1118:1118)) + (PORT d[1] (928:928:928) (1013:1013:1013)) + (PORT d[2] (926:926:926) (1007:1007:1007)) + (PORT d[3] (1249:1249:1249) (1279:1279:1279)) + (PORT d[4] (1509:1509:1509) (1612:1612:1612)) + (PORT d[5] (1306:1306:1306) (1397:1397:1397)) + (PORT d[6] (1247:1247:1247) (1313:1313:1313)) + (PORT d[7] (1321:1321:1321) (1414:1414:1414)) + (PORT d[8] (1471:1471:1471) (1521:1521:1521)) + (PORT d[9] (1265:1265:1265) (1341:1341:1341)) + (PORT d[10] (1259:1259:1259) (1333:1333:1333)) + (PORT d[11] (1270:1270:1270) (1337:1337:1337)) + (PORT d[12] (1271:1271:1271) (1319:1319:1319)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (909:909:909) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) (DELAY (ABSOLUTE - (PORT datab (636:636:636) (645:645:645)) - (PORT datac (906:906:906) (905:905:905)) - (PORT datad (1123:1123:1123) (1224:1224:1224)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (992:992:992) (1066:1066:1066)) + (PORT datac (604:604:604) (608:608:608)) + (PORT datad (1039:1039:1039) (1055:1055:1055)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 03b41ff..3ea9d90 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 13:12:28" +// DATE "03/30/2022 13:47:24" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -93,7 +93,6 @@ wire \counter[9]~38 ; wire \counter[10]~39_combout ; wire \counter[10]~40 ; wire \counter[11]~41_combout ; -wire \counter[11]~feeder_combout ; wire \counter[11]~42 ; wire \counter[12]~43_combout ; wire \counter[12]~44 ; @@ -110,83 +109,71 @@ wire \counter[17]~54 ; wire \counter[18]~55_combout ; wire \counter[18]~56 ; wire \counter[19]~57_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~5_combout ; wire \Equal0~0_combout ; wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \counter[19]~58 ; -wire \counter[20]~59_combout ; -wire \counter[20]~60 ; -wire \counter[21]~61_combout ; -wire \Equal0~7_combout ; -wire \address[0]~39_combout ; -wire \address[1]~13_combout ; wire \Equal0~6_combout ; -wire \address[1]~14 ; -wire \address[2]~15_combout ; -wire \address[2]~16 ; -wire \address[3]~17_combout ; -wire \address[3]~18 ; -wire \address[4]~19_combout ; -wire \address[4]~20 ; -wire \address[5]~21_combout ; -wire \address[5]~22 ; -wire \address[6]~23_combout ; -wire \address[6]~24 ; -wire \address[7]~25_combout ; -wire \address[7]~26 ; -wire \address[8]~27_combout ; -wire \address[8]~28 ; -wire \address[9]~29_combout ; -wire \address[9]~30 ; -wire \address[10]~31_combout ; -wire \address[10]~32 ; -wire \address[11]~33_combout ; -wire \address[11]~34 ; -wire \address[12]~35_combout ; -wire \address[12]~36 ; -wire \address[13]~37_combout ; +wire \A[0]~39_combout ; +wire \A[1]~13_combout ; +wire \A[1]~14 ; +wire \A[2]~15_combout ; +wire \A[2]~16 ; +wire \A[3]~17_combout ; +wire \A[3]~18 ; +wire \A[4]~19_combout ; +wire \A[4]~20 ; +wire \A[5]~21_combout ; +wire \A[5]~22 ; +wire \A[6]~23_combout ; +wire \A[6]~24 ; +wire \A[7]~25_combout ; +wire \A[7]~26 ; +wire \A[8]~27_combout ; +wire \A[8]~28 ; +wire \A[9]~29_combout ; +wire \A[9]~30 ; +wire \A[10]~31_combout ; +wire \A[10]~32 ; +wire \A[11]~33_combout ; +wire \A[11]~34 ; +wire \A[12]~35_combout ; +wire \A[12]~36 ; +wire \A[13]~37_combout ; +wire \~GND~combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; wire [21:0] counter; -wire [13:0] address; +wire [15:0] A; wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; @@ -196,21 +183,13 @@ wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bu wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; @@ -230,7 +209,7 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -243,7 +222,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -256,7 +235,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,7 +248,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .i(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -282,7 +261,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -295,7 +274,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -308,7 +287,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -321,7 +300,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -355,7 +334,7 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N2 +// Location: LCCOMB_X30_Y14_N2 cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): // \counter[0]~63_combout = !counter[0] @@ -372,7 +351,7 @@ defparam \counter[0]~63 .lut_mask = 16'h0F0F; defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N3 +// Location: FF_X30_Y14_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[0]~63_combout ), @@ -391,7 +370,7 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N12 +// Location: LCCOMB_X30_Y14_N12 cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): // \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) @@ -409,7 +388,7 @@ defparam \counter[1]~21 .lut_mask = 16'h6688; defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N13 +// Location: FF_X30_Y14_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[1]~21_combout ), @@ -428,7 +407,7 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 +// Location: LCCOMB_X30_Y14_N14 cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): // \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) @@ -446,7 +425,7 @@ defparam \counter[2]~23 .lut_mask = 16'h3C3F; defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N15 +// Location: FF_X30_Y14_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[2]~23_combout ), @@ -465,7 +444,7 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N16 +// Location: LCCOMB_X30_Y14_N16 cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): // \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) @@ -483,7 +462,7 @@ defparam \counter[3]~25 .lut_mask = 16'hC30C; defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N17 +// Location: FF_X30_Y14_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[3]~25_combout ), @@ -502,7 +481,7 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N18 +// Location: LCCOMB_X30_Y14_N18 cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): // \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) @@ -520,7 +499,7 @@ defparam \counter[4]~27 .lut_mask = 16'h3C3F; defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N19 +// Location: FF_X30_Y14_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[4]~27_combout ), @@ -539,7 +518,7 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N20 +// Location: LCCOMB_X30_Y14_N20 cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): // \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) @@ -557,7 +536,7 @@ defparam \counter[5]~29 .lut_mask = 16'hC30C; defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N21 +// Location: FF_X30_Y14_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[5]~29_combout ), @@ -576,7 +555,7 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X30_Y14_N22 cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): // \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) @@ -594,7 +573,7 @@ defparam \counter[6]~31 .lut_mask = 16'h5A5F; defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N23 +// Location: FF_X30_Y14_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[6]~31_combout ), @@ -613,7 +592,7 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N24 +// Location: LCCOMB_X30_Y14_N24 cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): // \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) @@ -631,7 +610,7 @@ defparam \counter[7]~33 .lut_mask = 16'hC30C; defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N25 +// Location: FF_X30_Y14_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[7]~33_combout ), @@ -650,7 +629,7 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N26 +// Location: LCCOMB_X30_Y14_N26 cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): // \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) @@ -668,7 +647,7 @@ defparam \counter[8]~35 .lut_mask = 16'h5A5F; defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N27 +// Location: FF_X30_Y14_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[8]~35_combout ), @@ -687,7 +666,7 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N28 +// Location: LCCOMB_X30_Y14_N28 cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): // \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) @@ -705,7 +684,7 @@ defparam \counter[9]~37 .lut_mask = 16'hC30C; defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N29 +// Location: FF_X30_Y14_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[9]~37_combout ), @@ -724,7 +703,7 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N30 +// Location: LCCOMB_X30_Y14_N30 cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): // \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) @@ -742,7 +721,7 @@ defparam \counter[10]~39 .lut_mask = 16'h5A5F; defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y18_N31 +// Location: FF_X30_Y14_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[10]~39_combout ), @@ -761,45 +740,28 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N0 +// Location: LCCOMB_X30_Y13_N0 cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): // \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) // \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(counter[11]), - .datab(gnd), + .dataa(gnd), + .datab(counter[11]), .datac(gnd), .datad(vcc), .cin(\counter[10]~40 ), .combout(\counter[11]~41_combout ), .cout(\counter[11]~42 )); // synopsys translate_off -defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .lut_mask = 16'hC30C; defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \counter[11]~feeder ( -// Equation(s): -// \counter[11]~feeder_combout = \counter[11]~41_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\counter[11]~41_combout ), - .cin(gnd), - .combout(\counter[11]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \counter[11]~feeder .lut_mask = 16'hFF00; -defparam \counter[11]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N5 +// Location: FF_X30_Y13_N1 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~feeder_combout ), + .d(\counter[11]~41_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -815,7 +777,7 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N2 +// Location: LCCOMB_X30_Y13_N2 cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): // \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) @@ -833,7 +795,7 @@ defparam \counter[12]~43 .lut_mask = 16'h3C3F; defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N3 +// Location: FF_X30_Y13_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[12]~43_combout ), @@ -852,25 +814,25 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N4 +// Location: LCCOMB_X30_Y13_N4 cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): // \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) // \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) - .dataa(gnd), - .datab(counter[13]), + .dataa(counter[13]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[12]~44 ), .combout(\counter[13]~45_combout ), .cout(\counter[13]~46 )); // synopsys translate_off -defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .lut_mask = 16'hA50A; defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N5 +// Location: FF_X30_Y13_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[13]~45_combout ), @@ -889,7 +851,7 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N6 +// Location: LCCOMB_X30_Y13_N6 cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): // \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) @@ -907,7 +869,7 @@ defparam \counter[14]~47 .lut_mask = 16'h5A5F; defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N7 +// Location: FF_X30_Y13_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[14]~47_combout ), @@ -926,25 +888,25 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N8 +// Location: LCCOMB_X30_Y13_N8 cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): // \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) // \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) - .dataa(gnd), - .datab(counter[15]), + .dataa(counter[15]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\counter[14]~48 ), .combout(\counter[15]~49_combout ), .cout(\counter[15]~50 )); // synopsys translate_off -defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .lut_mask = 16'hA50A; defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N9 +// Location: FF_X30_Y13_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[15]~49_combout ), @@ -963,7 +925,7 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N10 +// Location: LCCOMB_X30_Y13_N10 cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): // \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) @@ -981,7 +943,7 @@ defparam \counter[16]~51 .lut_mask = 16'h5A5F; defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N11 +// Location: FF_X30_Y13_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[16]~51_combout ), @@ -1000,7 +962,7 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N12 +// Location: LCCOMB_X30_Y13_N12 cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): // \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) @@ -1018,7 +980,7 @@ defparam \counter[17]~53 .lut_mask = 16'hA50A; defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N13 +// Location: FF_X30_Y13_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[17]~53_combout ), @@ -1037,7 +999,7 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N14 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): // \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) @@ -1055,7 +1017,7 @@ defparam \counter[18]~55 .lut_mask = 16'h3C3F; defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N15 +// Location: FF_X30_Y13_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[18]~55_combout ), @@ -1074,7 +1036,7 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N16 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): // \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) @@ -1092,7 +1054,7 @@ defparam \counter[19]~57 .lut_mask = 16'hC30C; defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N17 +// Location: FF_X30_Y13_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[19]~57_combout ), @@ -1111,109 +1073,7 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N28 -cycloneive_lcell_comb \Equal0~5 ( -// Equation(s): -// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - - .dataa(counter[17]), - .datab(counter[19]), - .datac(counter[18]), - .datad(counter[16]), - .cin(gnd), - .combout(\Equal0~5_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~5 .lut_mask = 16'h0001; -defparam \Equal0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \Equal0~0 ( -// Equation(s): -// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(counter[2]), - .datad(counter[3]), - .cin(gnd), - .combout(\Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~0 .lut_mask = 16'h0001; -defparam \Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) - - .dataa(counter[6]), - .datab(counter[7]), - .datac(counter[5]), - .datad(counter[4]), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \Equal0~2 ( -// Equation(s): -// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - - .dataa(counter[8]), - .datab(counter[11]), - .datac(counter[10]), - .datad(counter[9]), - .cin(gnd), - .combout(\Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~2 .lut_mask = 16'h0001; -defparam \Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N26 -cycloneive_lcell_comb \Equal0~3 ( -// Equation(s): -// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - - .dataa(counter[14]), - .datab(counter[13]), - .datac(counter[15]), - .datad(counter[12]), - .cin(gnd), - .combout(\Equal0~3_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~3 .lut_mask = 16'h0001; -defparam \Equal0~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \Equal0~4 ( -// Equation(s): -// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - - .dataa(\Equal0~0_combout ), - .datab(\Equal0~1_combout ), - .datac(\Equal0~2_combout ), - .datad(\Equal0~3_combout ), - .cin(gnd), - .combout(\Equal0~4_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~4 .lut_mask = 16'h8000; -defparam \Equal0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y17_N18 +// Location: LCCOMB_X30_Y13_N18 cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): // \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) @@ -1231,7 +1091,7 @@ defparam \counter[20]~59 .lut_mask = 16'h3C3F; defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N19 +// Location: FF_X30_Y13_N19 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[20]~59_combout ), @@ -1250,7 +1110,7 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y17_N20 +// Location: LCCOMB_X30_Y13_N20 cycloneive_lcell_comb \counter[21]~61 ( // Equation(s): // \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) @@ -1267,7 +1127,7 @@ defparam \counter[21]~61 .lut_mask = 16'hF00F; defparam \counter[21]~61 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X28_Y17_N21 +// Location: FF_X30_Y13_N21 dffeas \counter[21] ( .clk(\CLOCK_50~inputclkctrl_outclk ), .d(\counter[21]~61_combout ), @@ -1286,78 +1146,109 @@ defparam \counter[21] .is_wysiwyg = "true"; defparam \counter[21] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \Equal0~7 ( +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~7_combout = (!counter[21] & !counter[20]) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(counter[20]), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), - .combout(\Equal0~7_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h000F; -defparam \Equal0~7 .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \address[0]~39 ( +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Equal0~5_combout ), - .datab(\Equal0~4_combout ), - .datac(address[0]), - .datad(\Equal0~7_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), - .combout(\address[0]~39_combout ), + .combout(\Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \address[0]~39 .lut_mask = 16'h78F0; -defparam \address[0]~39 .sum_lutc_input = "datac"; +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N31 -dffeas \address[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(address[0]), - .prn(vcc)); -// synopsys translate_off -defparam \address[0] .is_wysiwyg = "true"; -defparam \address[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \address[1]~13 ( +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \Equal0~1 ( // Equation(s): -// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) -// \address[1]~14 = CARRY((address[0] & address[1])) +// \Equal0~1_combout = (!counter[6] & (!counter[4] & (!counter[7] & !counter[5]))) - .dataa(address[0]), - .datab(address[1]), - .datac(gnd), - .datad(vcc), + .dataa(counter[6]), + .datab(counter[4]), + .datac(counter[7]), + .datad(counter[5]), .cin(gnd), - .combout(\address[1]~13_combout ), - .cout(\address[1]~14 )); + .combout(\Equal0~1_combout ), + .cout()); // synopsys translate_off -defparam \address[1]~13 .lut_mask = 16'h6688; -defparam \address[1]~13 .sum_lutc_input = "datac"; +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N26 +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!counter[10] & (!counter[9] & (!counter[8] & !counter[11]))) + + .dataa(counter[10]), + .datab(counter[9]), + .datac(counter[8]), + .datad(counter[11]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!counter[14] & (!counter[15] & (!counter[13] & !counter[12]))) + + .dataa(counter[14]), + .datab(counter[15]), + .datac(counter[13]), + .datad(counter[12]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): // \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) @@ -1374,489 +1265,27 @@ defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \address[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~13_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[1]), - .prn(vcc)); -// synopsys translate_off -defparam \address[1] .is_wysiwyg = "true"; -defparam \address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \address[2]~15 ( +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \A[0]~39 ( // Equation(s): -// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) -// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) - - .dataa(gnd), - .datab(address[2]), - .datac(gnd), - .datad(vcc), - .cin(\address[1]~14 ), - .combout(\address[2]~15_combout ), - .cout(\address[2]~16 )); -// synopsys translate_off -defparam \address[2]~15 .lut_mask = 16'h3C3F; -defparam \address[2]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N3 -dffeas \address[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[2]), - .prn(vcc)); -// synopsys translate_off -defparam \address[2] .is_wysiwyg = "true"; -defparam \address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \address[3]~17 ( -// Equation(s): -// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) -// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) - - .dataa(gnd), - .datab(address[3]), - .datac(gnd), - .datad(vcc), - .cin(\address[2]~16 ), - .combout(\address[3]~17_combout ), - .cout(\address[3]~18 )); -// synopsys translate_off -defparam \address[3]~17 .lut_mask = 16'hC30C; -defparam \address[3]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N5 -dffeas \address[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[3]~17_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[3]), - .prn(vcc)); -// synopsys translate_off -defparam \address[3] .is_wysiwyg = "true"; -defparam \address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \address[4]~19 ( -// Equation(s): -// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) -// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) - - .dataa(address[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[3]~18 ), - .combout(\address[4]~19_combout ), - .cout(\address[4]~20 )); -// synopsys translate_off -defparam \address[4]~19 .lut_mask = 16'h5A5F; -defparam \address[4]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N7 -dffeas \address[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[4]~19_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[4]), - .prn(vcc)); -// synopsys translate_off -defparam \address[4] .is_wysiwyg = "true"; -defparam \address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \address[5]~21 ( -// Equation(s): -// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) -// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) - - .dataa(gnd), - .datab(address[5]), - .datac(gnd), - .datad(vcc), - .cin(\address[4]~20 ), - .combout(\address[5]~21_combout ), - .cout(\address[5]~22 )); -// synopsys translate_off -defparam \address[5]~21 .lut_mask = 16'hC30C; -defparam \address[5]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \address[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[5]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[5]), - .prn(vcc)); -// synopsys translate_off -defparam \address[5] .is_wysiwyg = "true"; -defparam \address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \address[6]~23 ( -// Equation(s): -// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) -// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) - - .dataa(address[6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[5]~22 ), - .combout(\address[6]~23_combout ), - .cout(\address[6]~24 )); -// synopsys translate_off -defparam \address[6]~23 .lut_mask = 16'h5A5F; -defparam \address[6]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \address[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[6]~23_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[6]), - .prn(vcc)); -// synopsys translate_off -defparam \address[6] .is_wysiwyg = "true"; -defparam \address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \address[7]~25 ( -// Equation(s): -// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) -// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) - - .dataa(address[7]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[6]~24 ), - .combout(\address[7]~25_combout ), - .cout(\address[7]~26 )); -// synopsys translate_off -defparam \address[7]~25 .lut_mask = 16'hA50A; -defparam \address[7]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N13 -dffeas \address[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[7]~25_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[7]), - .prn(vcc)); -// synopsys translate_off -defparam \address[7] .is_wysiwyg = "true"; -defparam \address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \address[8]~27 ( -// Equation(s): -// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) -// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) - - .dataa(gnd), - .datab(address[8]), - .datac(gnd), - .datad(vcc), - .cin(\address[7]~26 ), - .combout(\address[8]~27_combout ), - .cout(\address[8]~28 )); -// synopsys translate_off -defparam \address[8]~27 .lut_mask = 16'h3C3F; -defparam \address[8]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \address[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[8]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[8]), - .prn(vcc)); -// synopsys translate_off -defparam \address[8] .is_wysiwyg = "true"; -defparam \address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \address[9]~29 ( -// Equation(s): -// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) -// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) - - .dataa(gnd), - .datab(address[9]), - .datac(gnd), - .datad(vcc), - .cin(\address[8]~28 ), - .combout(\address[9]~29_combout ), - .cout(\address[9]~30 )); -// synopsys translate_off -defparam \address[9]~29 .lut_mask = 16'hC30C; -defparam \address[9]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \address[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[9]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[9]), - .prn(vcc)); -// synopsys translate_off -defparam \address[9] .is_wysiwyg = "true"; -defparam \address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \address[10]~31 ( -// Equation(s): -// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) -// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) - - .dataa(gnd), - .datab(address[10]), - .datac(gnd), - .datad(vcc), - .cin(\address[9]~30 ), - .combout(\address[10]~31_combout ), - .cout(\address[10]~32 )); -// synopsys translate_off -defparam \address[10]~31 .lut_mask = 16'h3C3F; -defparam \address[10]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N19 -dffeas \address[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[10]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[10]), - .prn(vcc)); -// synopsys translate_off -defparam \address[10] .is_wysiwyg = "true"; -defparam \address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \address[11]~33 ( -// Equation(s): -// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) -// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) - - .dataa(gnd), - .datab(address[11]), - .datac(gnd), - .datad(vcc), - .cin(\address[10]~32 ), - .combout(\address[11]~33_combout ), - .cout(\address[11]~34 )); -// synopsys translate_off -defparam \address[11]~33 .lut_mask = 16'hC30C; -defparam \address[11]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N21 -dffeas \address[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[11]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[11]), - .prn(vcc)); -// synopsys translate_off -defparam \address[11] .is_wysiwyg = "true"; -defparam \address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \address[12]~35 ( -// Equation(s): -// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) -// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) - - .dataa(address[12]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\address[11]~34 ), - .combout(\address[12]~35_combout ), - .cout(\address[12]~36 )); -// synopsys translate_off -defparam \address[12]~35 .lut_mask = 16'h5A5F; -defparam \address[12]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \address[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[12]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[12]), - .prn(vcc)); -// synopsys translate_off -defparam \address[12] .is_wysiwyg = "true"; -defparam \address[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \address[13]~37 ( -// Equation(s): -// \address[13]~37_combout = \address[12]~36 $ (!address[13]) +// \A[0]~39_combout = A[0] $ (\Equal0~6_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(address[13]), - .cin(\address[12]~36 ), - .combout(\address[13]~37_combout ), - .cout()); -// synopsys translate_off -defparam \address[13]~37 .lut_mask = 16'hF00F; -defparam \address[13]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X29_Y18_N25 -dffeas \address[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[13]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\Equal0~6_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(address[13]), - .prn(vcc)); -// synopsys translate_off -defparam \address[13] .is_wysiwyg = "true"; -defparam \address[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y18_N2 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(address[13]), + .datac(A[0]), + .datad(\Equal0~6_combout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .combout(\A[0]~39_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[0]~39 .lut_mask = 16'h0FF0; +defparam \A[0]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N3 -dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( +// Location: FF_X30_Y14_N1 +dffeas \A[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .d(\A[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1865,626 +1294,787 @@ dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .q(A[0]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +defparam \A[0] .is_wysiwyg = "true"; +defparam \A[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X30_Y18_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \A[1]~13 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] +// \A[1]~13_combout = (A[1] & (A[0] $ (VCC))) # (!A[1] & (A[0] & VCC)) +// \A[1]~14 = CARRY((A[1] & A[0])) - .dataa(gnd), - .datab(gnd), + .dataa(A[1]), + .datab(A[0]), .datac(gnd), - .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .datad(vcc), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), - .cout()); + .combout(\A[1]~13_combout ), + .cout(\A[1]~14 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +defparam \A[1]~13 .lut_mask = 16'h6688; +defparam \A[1]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y18_N25 -dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( +// Location: FF_X29_Y14_N1 +dffeas \A[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .d(\A[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .q(A[1]), .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +defparam \A[1] .is_wysiwyg = "true"; +defparam \A[1] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \A[2]~15 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) +// \A[2]~15_combout = (A[2] & (!\A[1]~14 )) # (!A[2] & ((\A[1]~14 ) # (GND))) +// \A[2]~16 = CARRY((!\A[1]~14 ) # (!A[2])) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), - .cout()); + .datab(A[2]), + .datac(gnd), + .datad(vcc), + .cin(\A[1]~14 ), + .combout(\A[2]~15_combout ), + .cout(\A[2]~16 )); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +defparam \A[2]~15 .lut_mask = 16'h3C3F; +defparam \A[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: FF_X29_Y14_N3 +dffeas \A[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[2]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(A[2]), + .prn(vcc)); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +defparam \A[2] .is_wysiwyg = "true"; +defparam \A[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: LCCOMB_X23_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \A[3]~17 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) +// \A[3]~17_combout = (A[3] & (\A[2]~16 $ (GND))) # (!A[3] & (!\A[2]~16 & VCC)) +// \A[3]~18 = CARRY((A[3] & !\A[2]~16 )) - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .dataa(gnd), + .datab(A[3]), + .datac(gnd), + .datad(vcc), + .cin(\A[2]~16 ), + .combout(\A[3]~17_combout ), + .cout(\A[3]~18 )); +// synopsys translate_off +defparam \A[3]~17 .lut_mask = 16'hC30C; +defparam \A[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N5 +dffeas \A[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[3]), + .prn(vcc)); +// synopsys translate_off +defparam \A[3] .is_wysiwyg = "true"; +defparam \A[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \A[4]~19 ( +// Equation(s): +// \A[4]~19_combout = (A[4] & (!\A[3]~18 )) # (!A[4] & ((\A[3]~18 ) # (GND))) +// \A[4]~20 = CARRY((!\A[3]~18 ) # (!A[4])) + + .dataa(A[4]), .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(\A[3]~18 ), + .combout(\A[4]~19_combout ), + .cout(\A[4]~20 )); +// synopsys translate_off +defparam \A[4]~19 .lut_mask = 16'h5A5F; +defparam \A[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \A[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[4]), + .prn(vcc)); +// synopsys translate_off +defparam \A[4] .is_wysiwyg = "true"; +defparam \A[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \A[5]~21 ( +// Equation(s): +// \A[5]~21_combout = (A[5] & (\A[4]~20 $ (GND))) # (!A[5] & (!\A[4]~20 & VCC)) +// \A[5]~22 = CARRY((A[5] & !\A[4]~20 )) + + .dataa(gnd), + .datab(A[5]), + .datac(gnd), + .datad(vcc), + .cin(\A[4]~20 ), + .combout(\A[5]~21_combout ), + .cout(\A[5]~22 )); +// synopsys translate_off +defparam \A[5]~21 .lut_mask = 16'hC30C; +defparam \A[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \A[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[5]), + .prn(vcc)); +// synopsys translate_off +defparam \A[5] .is_wysiwyg = "true"; +defparam \A[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \A[6]~23 ( +// Equation(s): +// \A[6]~23_combout = (A[6] & (!\A[5]~22 )) # (!A[6] & ((\A[5]~22 ) # (GND))) +// \A[6]~24 = CARRY((!\A[5]~22 ) # (!A[6])) + + .dataa(A[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[5]~22 ), + .combout(\A[6]~23_combout ), + .cout(\A[6]~24 )); +// synopsys translate_off +defparam \A[6]~23 .lut_mask = 16'h5A5F; +defparam \A[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \A[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[6]), + .prn(vcc)); +// synopsys translate_off +defparam \A[6] .is_wysiwyg = "true"; +defparam \A[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \A[7]~25 ( +// Equation(s): +// \A[7]~25_combout = (A[7] & (\A[6]~24 $ (GND))) # (!A[7] & (!\A[6]~24 & VCC)) +// \A[7]~26 = CARRY((A[7] & !\A[6]~24 )) + + .dataa(A[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[6]~24 ), + .combout(\A[7]~25_combout ), + .cout(\A[7]~26 )); +// synopsys translate_off +defparam \A[7]~25 .lut_mask = 16'hA50A; +defparam \A[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \A[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[7]), + .prn(vcc)); +// synopsys translate_off +defparam \A[7] .is_wysiwyg = "true"; +defparam \A[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \A[8]~27 ( +// Equation(s): +// \A[8]~27_combout = (A[8] & (!\A[7]~26 )) # (!A[8] & ((\A[7]~26 ) # (GND))) +// \A[8]~28 = CARRY((!\A[7]~26 ) # (!A[8])) + + .dataa(A[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[7]~26 ), + .combout(\A[8]~27_combout ), + .cout(\A[8]~28 )); +// synopsys translate_off +defparam \A[8]~27 .lut_mask = 16'h5A5F; +defparam \A[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N15 +dffeas \A[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[8]), + .prn(vcc)); +// synopsys translate_off +defparam \A[8] .is_wysiwyg = "true"; +defparam \A[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \A[9]~29 ( +// Equation(s): +// \A[9]~29_combout = (A[9] & (\A[8]~28 $ (GND))) # (!A[9] & (!\A[8]~28 & VCC)) +// \A[9]~30 = CARRY((A[9] & !\A[8]~28 )) + + .dataa(gnd), + .datab(A[9]), + .datac(gnd), + .datad(vcc), + .cin(\A[8]~28 ), + .combout(\A[9]~29_combout ), + .cout(\A[9]~30 )); +// synopsys translate_off +defparam \A[9]~29 .lut_mask = 16'hC30C; +defparam \A[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \A[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[9]), + .prn(vcc)); +// synopsys translate_off +defparam \A[9] .is_wysiwyg = "true"; +defparam \A[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \A[10]~31 ( +// Equation(s): +// \A[10]~31_combout = (A[10] & (!\A[9]~30 )) # (!A[10] & ((\A[9]~30 ) # (GND))) +// \A[10]~32 = CARRY((!\A[9]~30 ) # (!A[10])) + + .dataa(gnd), + .datab(A[10]), + .datac(gnd), + .datad(vcc), + .cin(\A[9]~30 ), + .combout(\A[10]~31_combout ), + .cout(\A[10]~32 )); +// synopsys translate_off +defparam \A[10]~31 .lut_mask = 16'h3C3F; +defparam \A[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \A[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[10]), + .prn(vcc)); +// synopsys translate_off +defparam \A[10] .is_wysiwyg = "true"; +defparam \A[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \A[11]~33 ( +// Equation(s): +// \A[11]~33_combout = (A[11] & (\A[10]~32 $ (GND))) # (!A[11] & (!\A[10]~32 & VCC)) +// \A[11]~34 = CARRY((A[11] & !\A[10]~32 )) + + .dataa(gnd), + .datab(A[11]), + .datac(gnd), + .datad(vcc), + .cin(\A[10]~32 ), + .combout(\A[11]~33_combout ), + .cout(\A[11]~34 )); +// synopsys translate_off +defparam \A[11]~33 .lut_mask = 16'hC30C; +defparam \A[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \A[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[11]), + .prn(vcc)); +// synopsys translate_off +defparam \A[11] .is_wysiwyg = "true"; +defparam \A[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \A[12]~35 ( +// Equation(s): +// \A[12]~35_combout = (A[12] & (!\A[11]~34 )) # (!A[12] & ((\A[11]~34 ) # (GND))) +// \A[12]~36 = CARRY((!\A[11]~34 ) # (!A[12])) + + .dataa(A[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\A[11]~34 ), + .combout(\A[12]~35_combout ), + .cout(\A[12]~36 )); +// synopsys translate_off +defparam \A[12]~35 .lut_mask = 16'h5A5F; +defparam \A[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \A[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[12]), + .prn(vcc)); +// synopsys translate_off +defparam \A[12] .is_wysiwyg = "true"; +defparam \A[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \A[13]~37 ( +// Equation(s): +// \A[13]~37_combout = \A[12]~36 $ (!A[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(A[13]), + .cin(\A[12]~36 ), + .combout(\A[13]~37_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +defparam \A[13]~37 .lut_mask = 16'hF00F; +defparam \A[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \A[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\A[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(A[13]), + .prn(vcc)); +// synopsys translate_off +defparam \A[13] .is_wysiwyg = "true"; +defparam \A[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; // synopsys translate_on // Location: M9K_X33_Y12_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; // synopsys translate_on -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), +// Location: M9K_X33_Y14_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(gnd), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(vcc), + .ena1(!A[13]), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portadatain({\~GND~combout }), + .portaaddr({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,A[2],A[1],A[0]}), .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), + .portbdatain({\~GND~combout }), + .portbaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 +// Location: M9K_X22_Y13_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portawe(vcc), .portare(vcc), @@ -2494,14 +2084,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2540,25 +2130,153 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; // synopsys translate_on -// Location: LCCOMB_X23_Y18_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) - - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), - .cout()); +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = A[13] + + .dataa(gnd), + .datab(gnd), + .datac(A[13]), + .datad(gnd), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hF0F0; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portawe(vcc), .portare(vcc), @@ -2568,14 +2286,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2614,7 +2332,7 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; // synopsys translate_on -// Location: M9K_X22_Y13_N0 +// Location: M9K_X22_Y11_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portawe(vcc), .portare(vcc), @@ -2624,14 +2342,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2670,81 +2388,25 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # // (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(gnd), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hB8B8; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(address[13]), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portawe(vcc), .portare(vcc), @@ -2754,14 +2416,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(!A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2800,26 +2462,8 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; // synopsys translate_on -// Location: LCCOMB_X32_Y19_N0 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( -// Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(gnd), - .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -2828,53 +2472,71 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portawe(vcc), .portare(vcc), @@ -2884,14 +2546,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(address[13]), + .ena0(A[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), .portabyteenamasks(1'b1), .portbdatain(1'b0), .portbaddr(13'b0000000000000), @@ -2930,22 +2592,78 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; // synopsys translate_on -// Location: LCCOMB_X23_Y14_N12 -cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!A[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({A[12],A[11],A[10],A[9],A[8],A[7],A[6],A[5],A[4],A[3],A[2],A[1],A[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( // Equation(s): -// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # -// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) .dataa(gnd), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), .cin(gnd), - .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; -defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index e0f98d2..dc41597 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:12:28") + (DATE "03/30/2022 13:47:24") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (941:941:941) (1090:1090:1090)) + (PORT i (1282:1282:1282) (1434:1434:1434)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (858:858:858) (973:973:973)) + (PORT i (1564:1564:1564) (1750:1750:1750)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (957:957:957) (1082:1082:1082)) + (PORT i (1536:1536:1536) (1717:1717:1717)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (611:611:611) (701:701:701)) + (PORT i (1057:1057:1057) (1192:1192:1192)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (821:821:821) (940:940:940)) + (PORT i (1350:1350:1350) (1544:1544:1544)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1195:1195:1195) (1350:1350:1350)) + (PORT i (1115:1115:1115) (1270:1270:1270)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1351:1351:1351) (1507:1507:1507)) + (PORT i (1307:1307:1307) (1471:1471:1471)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (550:550:550) (639:639:639)) + (PORT i (694:694:694) (773:773:773)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -163,7 +163,7 @@ (DELAY (ABSOLUTE (PORT dataa (136:136:136) (187:187:187)) - (PORT datab (135:135:135) (186:186:186)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -247,7 +247,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (183:183:183)) + (PORT datab (134:134:134) (184:184:184)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -275,7 +275,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (189:189:189)) + (PORT datab (134:134:134) (182:182:182)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -331,7 +331,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (183:183:183)) + (PORT datab (142:142:142) (189:189:189)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -359,7 +359,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (188:188:188)) + (PORT dataa (142:142:142) (193:193:193)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -387,7 +387,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (182:182:182)) + (PORT datab (141:141:141) (189:189:189)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -415,7 +415,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (133:133:133) (187:187:187)) + (PORT dataa (141:141:141) (192:192:192)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -443,31 +443,21 @@ (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (454:454:454)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (164:164:164) (192:192:192)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -495,7 +485,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -509,9 +499,9 @@ (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (211:211:211) (270:270:270)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -523,7 +513,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -551,7 +541,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -565,9 +555,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (211:211:211) (270:270:270)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -579,7 +569,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -607,7 +597,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -635,7 +625,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -649,7 +639,7 @@ (INSTANCE counter\[18\]\~55) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -663,7 +653,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -691,7 +681,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -700,102 +690,6 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (191:191:191)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (122:122:122) (165:165:165)) - (PORT datad (124:124:124) (164:164:164)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (135:135:135) (185:185:185)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (122:122:122) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (191:191:191)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (200:200:200) (245:245:245)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (194:194:194)) - (PORT datab (141:141:141) (190:190:190)) - (PORT datac (125:125:125) (170:170:170)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (192:192:192)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (123:123:123) (166:166:166)) - (PORT datad (124:124:124) (164:164:164)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (213:213:213)) - (PORT datab (177:177:177) (213:213:213)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (314:314:314) (364:364:364)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE counter\[20\]\~59) @@ -815,7 +709,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1139:1139:1139)) + (PORT clk (1110:1110:1110) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -840,7 +734,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1139:1139:1139)) + (PORT clk (1110:1110:1110) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -851,11 +745,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datac (359:359:359) (433:433:433)) - (PORT datad (350:350:350) (417:417:417)) + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -863,44 +761,80 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~39) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (401:401:401)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datad (170:170:170) (199:199:199)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (200:200:200) (246:246:246)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~13) + (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (146:146:146) (199:199:199)) - (PORT datab (140:140:140) (189:189:189)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (232:232:232) (289:289:289)) + (PORT datab (213:213:213) (270:270:270)) + (PORT datac (296:296:296) (349:349:349)) + (PORT datad (300:300:300) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (238:238:238)) + (PORT datab (177:177:177) (218:218:218)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (336:336:336) (394:394:394)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -910,10 +844,10 @@ (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (454:454:454)) - (PORT datab (364:364:364) (436:436:436)) - (PORT datac (325:325:325) (377:377:377)) - (PORT datad (95:95:95) (115:115:115)) + (PORT dataa (472:472:472) (559:559:559)) + (PORT datab (488:488:488) (576:576:576)) + (PORT datac (327:327:327) (384:384:384)) + (PORT datad (89:89:89) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -922,13 +856,53 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[0\]\~39) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (295:295:295)) + (PORT datab (320:320:320) (389:389:389)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -939,7 +913,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~15) + (INSTANCE A\[2\]\~15) (DELAY (ABSOLUTE (PORT datab (141:141:141) (189:189:189)) @@ -953,12 +927,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -969,10 +943,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[3\]\~17) + (INSTANCE A\[3\]\~17) (DELAY (ABSOLUTE - (PORT datab (154:154:154) (201:201:201)) + (PORT datab (141:141:141) (190:190:190)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -983,12 +957,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[3\]) + (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -999,7 +973,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[4\]\~19) + (INSTANCE A\[4\]\~19) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -1013,12 +987,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[4\]) + (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1029,7 +1003,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[5\]\~21) + (INSTANCE A\[5\]\~21) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -1043,12 +1017,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[5\]) + (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1059,7 +1033,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[6\]\~23) + (INSTANCE A\[6\]\~23) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -1073,12 +1047,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[6\]) + (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1089,7 +1063,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[7\]\~25) + (INSTANCE A\[7\]\~25) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -1103,12 +1077,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[7\]) + (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1119,7 +1093,67 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[8\]\~27) + (INSTANCE A\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (271:271:271)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (442:442:442)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (442:442:442)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[10\]\~31) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -1133,12 +1167,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[8\]) + (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1149,7 +1183,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[9\]\~29) + (INSTANCE A\[11\]\~33) (DELAY (ABSOLUTE (PORT datab (142:142:142) (190:190:190)) @@ -1163,12 +1197,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[9\]) + (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1179,67 +1213,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[10\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[11\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[12\]\~35) + (INSTANCE A\[12\]\~35) (DELAY (ABSOLUTE (PORT dataa (143:143:143) (193:193:193)) @@ -1253,12 +1227,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[12\]) + (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1269,7 +1243,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[13\]\~37) + (INSTANCE A\[13\]\~37) (DELAY (ABSOLUTE (PORT datad (141:141:141) (177:177:177)) @@ -1280,12 +1254,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[13\]) + (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) + (PORT clk (1111:1111:1111) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (409:409:409) (429:429:429)) + (PORT ena (422:422:422) (442:442:442)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -1294,170 +1268,13 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (275:275:275)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (696:696:696) (809:809:809)) - (PORT d[1] (727:727:727) (854:854:854)) - (PORT d[2] (770:770:770) (905:905:905)) - (PORT d[3] (752:752:752) (874:874:874)) - (PORT d[4] (709:709:709) (827:827:827)) - (PORT d[5] (774:774:774) (910:910:910)) - (PORT d[6] (1002:1002:1002) (1193:1193:1193)) - (PORT d[7] (749:749:749) (870:870:870)) - (PORT d[8] (756:756:756) (884:884:884)) - (PORT d[9] (769:769:769) (904:904:904)) - (PORT d[10] (751:751:751) (876:876:876)) - (PORT d[11] (880:880:880) (1014:1014:1014)) - (PORT d[12] (737:737:737) (853:853:853)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (659:659:659) (736:736:736)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE + (PORT d[0] (575:575:575) (672:672:672)) (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (643:643:643) (747:747:747)) - (PORT d[1] (556:556:556) (658:658:658)) - (PORT d[2] (593:593:593) (701:701:701)) - (PORT d[3] (758:758:758) (882:882:882)) - (PORT d[4] (705:705:705) (826:826:826)) - (PORT d[5] (749:749:749) (874:874:874)) - (PORT d[6] (874:874:874) (1055:1055:1055)) - (PORT d[7] (708:708:708) (817:817:817)) - (PORT d[8] (753:753:753) (886:886:886)) - (PORT d[9] (784:784:784) (927:927:927)) - (PORT d[10] (741:741:741) (864:864:864)) - (PORT d[11] (709:709:709) (823:823:823)) - (PORT d[12] (755:755:755) (877:877:877)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -1466,316 +1283,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (582:582:582) (526:526:526)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (545:545:545) (645:645:645)) - (PORT datac (484:484:484) (546:546:546)) - (PORT datad (333:333:333) (377:377:377)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (813:813:813) (941:941:941)) - (PORT d[1] (863:863:863) (1008:1008:1008)) - (PORT d[2] (881:881:881) (1027:1027:1027)) - (PORT d[3] (699:699:699) (808:808:808)) - (PORT d[4] (926:926:926) (1077:1077:1077)) - (PORT d[5] (1093:1093:1093) (1290:1290:1290)) - (PORT d[6] (695:695:695) (813:813:813)) - (PORT d[7] (761:761:761) (903:903:903)) - (PORT d[8] (1083:1083:1083) (1274:1274:1274)) - (PORT d[9] (677:677:677) (796:796:796)) - (PORT d[10] (799:799:799) (948:948:948)) - (PORT d[11] (665:665:665) (771:771:771)) - (PORT d[12] (687:687:687) (813:813:813)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (695:695:695) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (826:826:826) (972:972:972)) - (PORT d[1] (756:756:756) (903:903:903)) - (PORT d[2] (889:889:889) (1041:1041:1041)) - (PORT d[3] (752:752:752) (884:884:884)) - (PORT d[4] (736:736:736) (866:866:866)) - (PORT d[5] (908:908:908) (1078:1078:1078)) - (PORT d[6] (715:715:715) (845:845:845)) - (PORT d[7] (708:708:708) (834:834:834)) - (PORT d[8] (917:917:917) (1088:1088:1088)) - (PORT d[9] (746:746:746) (884:884:884)) - (PORT d[10] (1042:1042:1042) (1212:1212:1212)) - (PORT d[11] (728:728:728) (859:859:859)) - (PORT d[12] (886:886:886) (1034:1034:1034)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (672:672:672) (765:765:765)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (399:399:399)) - (PORT datac (502:502:502) (567:567:567)) - (PORT datad (721:721:721) (843:843:843)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (705:705:705) (819:819:819)) - (PORT d[1] (732:732:732) (860:860:860)) - (PORT d[2] (910:910:910) (1062:1062:1062)) - (PORT d[3] (784:784:784) (916:916:916)) - (PORT d[4] (732:732:732) (858:858:858)) - (PORT d[5] (737:737:737) (856:856:856)) - (PORT d[6] (1011:1011:1011) (1205:1205:1205)) - (PORT d[7] (765:765:765) (893:893:893)) - (PORT d[8] (760:760:760) (891:891:891)) - (PORT d[9] (803:803:803) (947:947:947)) - (PORT d[10] (982:982:982) (1126:1126:1126)) - (PORT d[11] (885:885:885) (1020:1020:1020)) - (PORT d[12] (758:758:758) (879:879:879)) + (PORT d[0] (590:590:590) (696:696:696)) + (PORT d[1] (817:817:817) (948:948:948)) + (PORT d[2] (530:530:530) (622:622:622)) + (PORT d[3] (567:567:567) (666:666:666)) + (PORT d[4] (567:567:567) (666:666:666)) + (PORT d[5] (440:440:440) (515:515:515)) + (PORT d[6] (440:440:440) (515:515:515)) + (PORT d[7] (440:440:440) (515:515:515)) + (PORT d[8] (440:440:440) (515:515:515)) + (PORT d[9] (440:440:440) (515:515:515)) + (PORT d[10] (440:440:440) (515:515:515)) + (PORT d[11] (440:440:440) (515:515:515)) + (PORT d[12] (440:440:440) (515:515:515)) (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) @@ -1785,114 +1308,26 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (765:765:765) (689:689:689)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (541:541:541) (637:637:637)) - (PORT d[1] (708:708:708) (828:828:828)) - (PORT d[2] (601:601:601) (702:702:702)) - (PORT d[3] (607:607:607) (715:715:715)) - (PORT d[4] (549:549:549) (647:647:647)) - (PORT d[5] (691:691:691) (797:797:797)) - (PORT d[6] (860:860:860) (1033:1033:1033)) - (PORT d[7] (707:707:707) (817:817:817)) - (PORT d[8] (599:599:599) (713:713:713)) - (PORT d[9] (625:625:625) (746:746:746)) - (PORT d[10] (828:828:828) (957:957:957)) - (PORT d[11] (709:709:709) (822:822:822)) - (PORT d[12] (742:742:742) (856:856:856)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (525:525:525) (581:581:581)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) @@ -1901,11 +1336,31 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1070:1070:1070)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -1916,74 +1371,310 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT d[0] (579:579:579) (676:676:676)) + (PORT clk (1056:1056:1056) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (581:581:581) (685:685:685)) + (PORT d[1] (818:818:818) (948:948:948)) + (PORT d[2] (541:541:541) (634:634:634)) + (PORT d[3] (677:677:677) (784:784:784)) + (PORT d[4] (537:537:537) (629:629:629)) + (PORT d[5] (882:882:882) (1013:1013:1013)) + (PORT d[6] (689:689:689) (790:790:790)) + (PORT d[7] (709:709:709) (819:819:819)) + (PORT d[8] (674:674:674) (787:787:787)) + (PORT d[9] (692:692:692) (792:792:792)) + (PORT d[10] (701:701:701) (805:805:805)) + (PORT d[11] (685:685:685) (787:787:787)) + (PORT d[12] (719:719:719) (829:829:829)) + (PORT clk (1053:1053:1053) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1073:1073:1073)) + (PORT d[0] (542:542:542) (498:498:498)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (551:551:551) (659:659:659)) - (PORT datac (509:509:509) (578:578:578)) - (PORT datad (328:328:328) (369:369:369)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (513:513:513) (599:599:599)) - (PORT d[1] (535:535:535) (638:638:638)) - (PORT d[2] (594:594:594) (707:707:707)) - (PORT d[3] (582:582:582) (682:682:682)) - (PORT d[4] (527:527:527) (618:618:618)) - (PORT d[5] (558:558:558) (656:656:656)) - (PORT d[6] (819:819:819) (985:985:985)) - (PORT d[7] (682:682:682) (790:790:790)) - (PORT d[8] (911:911:911) (1067:1067:1067)) - (PORT d[9] (597:597:597) (712:712:712)) - (PORT d[10] (575:575:575) (678:678:678)) - (PORT d[11] (710:710:710) (823:823:823)) - (PORT d[12] (716:716:716) (828:828:828)) + (PORT d[0] (564:564:564) (651:651:651)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (587:587:587) (692:692:692)) + (PORT d[1] (673:673:673) (782:782:782)) + (PORT d[2] (535:535:535) (629:629:629)) + (PORT d[3] (576:576:576) (669:669:669)) + (PORT d[4] (576:576:576) (669:669:669)) + (PORT d[5] (461:461:461) (543:543:543)) + (PORT d[6] (461:461:461) (543:543:543)) + (PORT d[7] (461:461:461) (543:543:543)) + (PORT d[8] (461:461:461) (543:543:543)) + (PORT d[9] (461:461:461) (543:543:543)) + (PORT d[10] (461:461:461) (543:543:543)) + (PORT d[11] (461:461:461) (543:543:543)) + (PORT d[12] (461:461:461) (543:543:543)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1068:1068:1068)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (568:568:568) (655:655:655)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (599:599:599) (705:705:705)) + (PORT d[1] (536:536:536) (629:629:629)) + (PORT d[2] (711:711:711) (827:827:827)) + (PORT d[3] (679:679:679) (777:777:777)) + (PORT d[4] (529:529:529) (615:615:615)) + (PORT d[5] (871:871:871) (1002:1002:1002)) + (PORT d[6] (708:708:708) (816:816:816)) + (PORT d[7] (714:714:714) (824:824:824)) + (PORT d[8] (809:809:809) (929:929:929)) + (PORT d[9] (698:698:698) (799:799:799)) + (PORT d[10] (710:710:710) (818:818:818)) + (PORT d[11] (692:692:692) (794:794:794)) + (PORT d[12] (713:713:713) (817:817:817)) + (PORT clk (1051:1051:1051) (1070:1070:1070)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + (PORT d[0] (549:549:549) (504:504:504)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (749:749:749) (870:870:870)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (590:590:590) (703:703:703)) + (PORT d[1] (511:511:511) (605:605:605)) + (PORT d[2] (843:843:843) (978:978:978)) + (PORT d[3] (749:749:749) (871:871:871)) + (PORT d[4] (749:749:749) (871:871:871)) + (PORT d[5] (426:426:426) (499:499:499)) + (PORT d[6] (426:426:426) (499:499:499)) + (PORT d[7] (426:426:426) (499:499:499)) + (PORT d[8] (426:426:426) (499:499:499)) + (PORT d[9] (426:426:426) (499:499:499)) + (PORT d[10] (426:426:426) (499:499:499)) + (PORT d[11] (426:426:426) (499:499:499)) + (PORT d[12] (426:426:426) (499:499:499)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -1993,30 +1684,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (497:497:497) (548:548:548)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1071:1071:1071)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2027,60 +1747,122 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) + (PORT d[0] (753:753:753) (874:874:874)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (581:581:581) (689:689:689)) + (PORT d[1] (829:829:829) (959:959:959)) + (PORT d[2] (505:505:505) (587:587:587)) + (PORT d[3] (808:808:808) (929:929:929)) + (PORT d[4] (517:517:517) (601:601:601)) + (PORT d[5] (584:584:584) (688:688:688)) + (PORT d[6] (687:687:687) (792:792:792)) + (PORT d[7] (579:579:579) (678:678:678)) + (PORT d[8] (830:830:830) (959:959:959)) + (PORT d[9] (693:693:693) (797:797:797)) + (PORT d[10] (688:688:688) (792:792:792)) + (PORT d[11] (686:686:686) (792:792:792)) + (PORT d[12] (694:694:694) (796:796:796)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT d[0] (528:528:528) (485:485:485)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (648:648:648) (753:753:753)) - (PORT d[1] (354:354:354) (417:417:417)) - (PORT d[2] (392:392:392) (461:461:461)) - (PORT d[3] (418:418:418) (491:491:491)) - (PORT d[4] (359:359:359) (424:424:424)) - (PORT d[5] (407:407:407) (482:482:482)) - (PORT d[6] (419:419:419) (492:492:492)) - (PORT d[7] (411:411:411) (485:485:485)) - (PORT d[8] (414:414:414) (490:490:490)) - (PORT d[9] (422:422:422) (503:503:503)) - (PORT d[10] (658:658:658) (769:769:769)) - (PORT d[11] (411:411:411) (482:482:482)) - (PORT d[12] (416:416:416) (490:490:490)) + (PORT d[0] (760:760:760) (881:881:881)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (420:420:420) (491:491:491)) + (PORT d[1] (350:350:350) (416:416:416)) + (PORT d[2] (851:851:851) (986:986:986)) + (PORT d[3] (362:362:362) (421:421:421)) + (PORT d[4] (362:362:362) (421:421:421)) + (PORT d[5] (263:263:263) (312:312:312)) + (PORT d[6] (263:263:263) (312:312:312)) + (PORT d[7] (263:263:263) (312:312:312)) + (PORT d[8] (263:263:263) (312:312:312)) + (PORT d[9] (263:263:263) (312:312:312)) + (PORT d[10] (263:263:263) (312:312:312)) + (PORT d[11] (263:263:263) (312:312:312)) + (PORT d[12] (263:263:263) (312:312:312)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -2090,30 +1872,59 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (376:376:376) (347:347:347)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1071:1071:1071)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2124,75 +1935,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (583:583:583)) - (PORT datac (358:358:358) (424:424:424)) - (PORT datad (331:331:331) (374:374:374)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (813:813:813) (944:944:944)) - (PORT d[1] (852:852:852) (996:996:996)) - (PORT d[2] (870:870:870) (1016:1016:1016)) - (PORT d[3] (550:550:550) (646:646:646)) - (PORT d[4] (543:543:543) (639:639:639)) - (PORT d[5] (921:921:921) (1093:1093:1093)) - (PORT d[6] (544:544:544) (650:650:650)) - (PORT d[7] (519:519:519) (618:618:618)) - (PORT d[8] (920:920:920) (1089:1089:1089)) - (PORT d[9] (546:546:546) (652:652:652)) - (PORT d[10] (536:536:536) (637:637:637)) - (PORT d[11] (524:524:524) (622:622:622)) - (PORT d[12] (537:537:537) (631:631:631)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (764:764:764) (885:885:885)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) ) ) (TIMINGCHECK @@ -2201,72 +1948,74 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (540:540:540) (486:486:486)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + (PORT d[0] (408:408:408) (481:481:481)) + (PORT d[1] (845:845:845) (980:980:980)) + (PORT d[2] (851:851:851) (985:985:985)) + (PORT d[3] (360:360:360) (420:420:420)) + (PORT d[4] (363:363:363) (426:426:426)) + (PORT d[5] (397:397:397) (470:470:470)) + (PORT d[6] (422:422:422) (497:497:497)) + (PORT d[7] (416:416:416) (491:491:491)) + (PORT d[8] (853:853:853) (987:987:987)) + (PORT d[9] (417:417:417) (487:487:487)) + (PORT d[10] (536:536:536) (626:626:626)) + (PORT d[11] (407:407:407) (476:476:476)) + (PORT d[12] (520:520:520) (600:600:600)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) + (HOLD d (posedge clk) (104:104:104)) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT d[0] (367:367:367) (342:342:342)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2276,19 +2025,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (667:667:667) (784:784:784)) - (PORT d[1] (696:696:696) (823:823:823)) - (PORT d[2] (712:712:712) (840:840:840)) - (PORT d[3] (708:708:708) (823:823:823)) - (PORT d[4] (919:919:919) (1070:1070:1070)) - (PORT d[5] (920:920:920) (1092:1092:1092)) - (PORT d[6] (704:704:704) (834:834:834)) - (PORT d[7] (688:688:688) (810:810:810)) - (PORT d[8] (919:919:919) (1088:1088:1088)) - (PORT d[9] (701:701:701) (826:826:826)) - (PORT d[10] (1057:1057:1057) (1230:1230:1230)) - (PORT d[11] (708:708:708) (835:835:835)) - (PORT d[12] (683:683:683) (805:805:805)) + (PORT d[0] (890:890:890) (1046:1046:1046)) + (PORT d[1] (707:707:707) (833:833:833)) + (PORT d[2] (698:698:698) (814:814:814)) + (PORT d[3] (700:700:700) (816:816:816)) + (PORT d[4] (716:716:716) (835:835:835)) + (PORT d[5] (893:893:893) (1047:1047:1047)) + (PORT d[6] (685:685:685) (805:805:805)) + (PORT d[7] (683:683:683) (802:802:802)) + (PORT d[8] (697:697:697) (821:821:821)) + (PORT d[9] (699:699:699) (813:813:813)) + (PORT d[10] (705:705:705) (827:827:827)) + (PORT d[11] (695:695:695) (816:816:816)) + (PORT d[12] (868:868:868) (1002:1002:1002)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -2302,7 +2051,7 @@ (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (637:637:637) (713:713:713)) + (PORT d[0] (652:652:652) (726:726:726)) ) ) ) @@ -2369,14 +2118,159 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT datab (349:349:349) (398:398:398)) - (PORT datac (475:475:475) (533:533:533)) - (PORT datad (428:428:428) (504:504:504)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT d[0] (741:741:741) (882:882:882)) + (PORT d[1] (710:710:710) (834:834:834)) + (PORT d[2] (710:710:710) (834:834:834)) + (PORT d[3] (737:737:737) (861:861:861)) + (PORT d[4] (737:737:737) (864:864:864)) + (PORT d[5] (885:885:885) (1039:1039:1039)) + (PORT d[6] (687:687:687) (804:804:804)) + (PORT d[7] (695:695:695) (814:814:814)) + (PORT d[8] (713:713:713) (841:841:841)) + (PORT d[9] (698:698:698) (807:807:807)) + (PORT d[10] (704:704:704) (821:821:821)) + (PORT d[11] (708:708:708) (830:830:830)) + (PORT d[12] (709:709:709) (830:830:830)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (754:754:754) (674:674:674)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (343:343:343) (405:405:405)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (390:390:390)) + (PORT datac (503:503:503) (576:576:576)) + (PORT datad (534:534:534) (639:639:639)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2387,20 +2281,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (840:840:840) (987:987:987)) - (PORT d[1] (1090:1090:1090) (1276:1276:1276)) - (PORT d[2] (713:713:713) (840:840:840)) - (PORT d[3] (739:739:739) (859:859:859)) - (PORT d[4] (736:736:736) (862:862:862)) - (PORT d[5] (706:706:706) (838:838:838)) - (PORT d[6] (733:733:733) (868:868:868)) - (PORT d[7] (716:716:716) (843:843:843)) - (PORT d[8] (901:901:901) (1069:1069:1069)) - (PORT d[9] (744:744:744) (880:880:880)) - (PORT d[10] (1059:1059:1059) (1238:1238:1238)) - (PORT d[11] (722:722:722) (847:847:847)) - (PORT d[12] (859:859:859) (1000:1000:1000)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (902:902:902) (1061:1061:1061)) + (PORT d[1] (541:541:541) (647:647:647)) + (PORT d[2] (549:549:549) (652:652:652)) + (PORT d[3] (570:570:570) (678:678:678)) + (PORT d[4] (543:543:543) (639:639:639)) + (PORT d[5] (894:894:894) (1048:1048:1048)) + (PORT d[6] (530:530:530) (631:631:631)) + (PORT d[7] (520:520:520) (620:620:620)) + (PORT d[8] (555:555:555) (661:661:661)) + (PORT d[9] (827:827:827) (956:956:956)) + (PORT d[10] (807:807:807) (932:932:932)) + (PORT d[11] (518:518:518) (615:615:615)) + (PORT d[12] (549:549:549) (649:649:649)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) (TIMINGCHECK @@ -2412,8 +2306,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (672:672:672) (759:759:759)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (497:497:497) (552:552:552)) ) ) ) @@ -2422,7 +2316,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2432,7 +2326,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1072:1072:1072) (1088:1088:1088)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2446,7 +2340,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -2455,7 +2349,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) ) ) ) @@ -2464,7 +2358,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2474,7 +2368,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (613:613:613) (621:621:621)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2484,20 +2378,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (867:867:867) (1022:1022:1022)) - (PORT d[1] (928:928:928) (1097:1097:1097)) - (PORT d[2] (889:889:889) (1039:1039:1039)) - (PORT d[3] (932:932:932) (1088:1088:1088)) - (PORT d[4] (904:904:904) (1065:1065:1065)) - (PORT d[5] (892:892:892) (1048:1048:1048)) - (PORT d[6] (883:883:883) (1038:1038:1038)) - (PORT d[7] (871:871:871) (1018:1018:1018)) - (PORT d[8] (871:871:871) (1029:1029:1029)) - (PORT d[9] (908:908:908) (1064:1064:1064)) - (PORT d[10] (863:863:863) (1012:1012:1012)) - (PORT d[11] (892:892:892) (1039:1039:1039)) - (PORT d[12] (860:860:860) (1009:1009:1009)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (709:709:709) (831:831:831)) + (PORT d[1] (717:717:717) (841:841:841)) + (PORT d[2] (701:701:701) (817:817:817)) + (PORT d[3] (729:729:729) (850:850:850)) + (PORT d[4] (722:722:722) (844:844:844)) + (PORT d[5] (871:871:871) (1018:1018:1018)) + (PORT d[6] (705:705:705) (825:825:825)) + (PORT d[7] (701:701:701) (821:821:821)) + (PORT d[8] (720:720:720) (849:849:849)) + (PORT d[9] (704:704:704) (814:814:814)) + (PORT d[10] (710:710:710) (828:828:828)) + (PORT d[11] (701:701:701) (817:817:817)) + (PORT d[12] (850:850:850) (983:983:983)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) (TIMINGCHECK @@ -2509,8 +2403,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (920:920:920) (819:819:819)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (715:715:715) (641:641:641)) ) ) ) @@ -2519,7 +2413,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2529,7 +2423,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) + (PORT clk (1069:1069:1069) (1085:1085:1085)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2543,7 +2437,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (609:609:609) (617:617:617)) ) ) ) @@ -2552,7 +2446,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (610:610:610) (618:618:618)) ) ) ) @@ -2561,7 +2455,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (610:610:610) (618:618:618)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2571,22 +2465,119 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) + (PORT clk (610:610:610) (618:618:618)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT datab (341:341:341) (389:389:389)) - (PORT datac (510:510:510) (575:575:575)) - (PORT datad (626:626:626) (741:741:741)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (343:343:343) (396:396:396)) + (PORT datab (391:391:391) (482:482:482)) + (PORT datac (509:509:509) (578:578:578)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1062:1062:1062) (1240:1240:1240)) + (PORT d[1] (678:678:678) (795:795:795)) + (PORT d[2] (707:707:707) (825:825:825)) + (PORT d[3] (722:722:722) (850:850:850)) + (PORT d[4] (698:698:698) (818:818:818)) + (PORT d[5] (1071:1071:1071) (1252:1252:1252)) + (PORT d[6] (680:680:680) (794:794:794)) + (PORT d[7] (766:766:766) (911:911:911)) + (PORT d[8] (671:671:671) (789:789:789)) + (PORT d[9] (687:687:687) (798:798:798)) + (PORT d[10] (701:701:701) (824:824:824)) + (PORT d[11] (668:668:668) (774:774:774)) + (PORT d[12] (699:699:699) (819:819:819)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (706:706:706) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) @@ -2595,19 +2586,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (539:539:539) (637:637:637)) - (PORT d[1] (697:697:697) (818:818:818)) - (PORT d[2] (599:599:599) (708:708:708)) - (PORT d[3] (608:608:608) (718:718:718)) - (PORT d[4] (555:555:555) (660:660:660)) - (PORT d[5] (599:599:599) (709:709:709)) - (PORT d[6] (841:841:841) (1010:1010:1010)) - (PORT d[7] (714:714:714) (829:829:829)) - (PORT d[8] (596:596:596) (706:706:706)) - (PORT d[9] (600:600:600) (716:716:716)) - (PORT d[10] (579:579:579) (682:682:682)) - (PORT d[11] (699:699:699) (809:809:809)) - (PORT d[12] (735:735:735) (849:849:849)) + (PORT d[0] (418:418:418) (498:498:498)) + (PORT d[1] (350:350:350) (416:416:416)) + (PORT d[2] (841:841:841) (972:972:972)) + (PORT d[3] (659:659:659) (763:763:763)) + (PORT d[4] (523:523:523) (608:608:608)) + (PORT d[5] (581:581:581) (682:682:682)) + (PORT d[6] (662:662:662) (762:762:762)) + (PORT d[7] (686:686:686) (794:794:794)) + (PORT d[8] (846:846:846) (974:974:974)) + (PORT d[9] (689:689:689) (796:796:796)) + (PORT d[10] (686:686:686) (791:791:791)) + (PORT d[11] (665:665:665) (765:765:765)) + (PORT d[12] (681:681:681) (783:783:783)) (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) @@ -2621,7 +2612,7 @@ (DELAY (ABSOLUTE (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (517:517:517) (572:572:572)) + (PORT d[0] (487:487:487) (531:531:531)) ) ) ) @@ -2687,233 +2678,39 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (509:509:509) (594:594:594)) - (PORT d[1] (355:355:355) (418:418:418)) - (PORT d[2] (733:733:733) (863:863:863)) - (PORT d[3] (766:766:766) (895:895:895)) - (PORT d[4] (514:514:514) (597:597:597)) - (PORT d[5] (582:582:582) (683:683:683)) - (PORT d[6] (805:805:805) (963:963:963)) - (PORT d[7] (681:681:681) (788:788:788)) - (PORT d[8] (925:925:925) (1079:1079:1079)) - (PORT d[9] (580:580:580) (683:683:683)) - (PORT d[10] (577:577:577) (677:677:677)) - (PORT d[11] (660:660:660) (761:761:761)) - (PORT d[12] (686:686:686) (789:789:789)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (534:534:534) (487:487:487)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) (DELAY (ABSOLUTE - (PORT dataa (391:391:391) (455:455:455)) - (PORT datac (481:481:481) (561:561:561)) - (PORT datad (186:186:186) (218:218:218)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (527:527:527) (627:627:627)) + (PORT datac (326:326:326) (367:367:367)) + (PORT datad (559:559:559) (635:635:635)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (830:830:830) (970:970:970)) - (PORT d[1] (1078:1078:1078) (1262:1262:1262)) - (PORT d[2] (1085:1085:1085) (1259:1259:1259)) - (PORT d[3] (772:772:772) (909:909:909)) - (PORT d[4] (1067:1067:1067) (1250:1250:1250)) - (PORT d[5] (739:739:739) (887:887:887)) - (PORT d[6] (747:747:747) (889:889:889)) - (PORT d[7] (717:717:717) (844:844:844)) - (PORT d[8] (733:733:733) (878:878:878)) - (PORT d[9] (731:731:731) (861:861:861)) - (PORT d[10] (1020:1020:1020) (1186:1186:1186)) - (PORT d[11] (723:723:723) (848:848:848)) - (PORT d[12] (713:713:713) (836:836:836)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (776:776:776) (683:683:683)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1017:1017:1017) (1190:1190:1190)) - (PORT d[1] (910:910:910) (1072:1072:1072)) - (PORT d[2] (907:907:907) (1065:1065:1065)) - (PORT d[3] (918:918:918) (1070:1070:1070)) - (PORT d[4] (910:910:910) (1068:1068:1068)) - (PORT d[5] (891:891:891) (1047:1047:1047)) - (PORT d[6] (884:884:884) (1036:1036:1036)) - (PORT d[7] (880:880:880) (1029:1029:1029)) - (PORT d[8] (867:867:867) (1020:1020:1020)) - (PORT d[9] (913:913:913) (1070:1070:1070)) - (PORT d[10] (853:853:853) (997:997:997)) - (PORT d[11] (898:898:898) (1045:1045:1045)) - (PORT d[12] (870:870:870) (1019:1019:1019)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (870:870:870) (1017:1017:1017)) + (PORT d[1] (729:729:729) (858:858:858)) + (PORT d[2] (709:709:709) (832:832:832)) + (PORT d[3] (754:754:754) (885:885:885)) + (PORT d[4] (892:892:892) (1033:1033:1033)) + (PORT d[5] (722:722:722) (857:857:857)) + (PORT d[6] (718:718:718) (845:845:845)) + (PORT d[7] (702:702:702) (822:822:822)) + (PORT d[8] (708:708:708) (830:830:830)) + (PORT d[9] (718:718:718) (834:834:834)) + (PORT d[10] (724:724:724) (848:848:848)) + (PORT d[11] (702:702:702) (818:818:818)) + (PORT d[12] (705:705:705) (820:820:820)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) ) ) (TIMINGCHECK @@ -2925,8 +2722,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (PORT d[0] (846:846:846) (959:959:959)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT d[0] (637:637:637) (711:711:711)) ) ) ) @@ -2935,7 +2732,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT clk (1086:1086:1086) (1103:1103:1103)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -2945,7 +2742,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) + (PORT clk (1067:1067:1067) (1083:1083:1083)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -2959,7 +2756,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) + (PORT clk (607:607:607) (615:615:615)) ) ) ) @@ -2968,7 +2765,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (608:608:608) (616:616:616)) ) ) ) @@ -2977,7 +2774,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (608:608:608) (616:616:616)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -2987,20 +2784,117 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (579:579:579) (682:682:682)) + (PORT d[1] (520:520:520) (610:610:610)) + (PORT d[2] (520:520:520) (605:605:605)) + (PORT d[3] (679:679:679) (778:778:778)) + (PORT d[4] (859:859:859) (988:988:988)) + (PORT d[5] (729:729:729) (849:849:849)) + (PORT d[6] (694:694:694) (798:798:798)) + (PORT d[7] (731:731:731) (845:845:845)) + (PORT d[8] (827:827:827) (954:954:954)) + (PORT d[9] (711:711:711) (819:819:819)) + (PORT d[10] (710:710:710) (819:819:819)) + (PORT d[11] (704:704:704) (814:814:814)) + (PORT d[12] (713:713:713) (817:817:817)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (549:549:549) (505:505:505)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) (DELAY (ABSOLUTE - (PORT datab (346:346:346) (394:394:394)) - (PORT datac (502:502:502) (567:567:567)) - (PORT datad (628:628:628) (743:743:743)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (554:554:554) (662:662:662)) + (PORT datac (330:330:330) (371:371:371)) + (PORT datad (564:564:564) (639:639:639)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index 2c6fa75..ff9bb97 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -4,6 +4,8 @@ source_file = 1, /home/benny/work/fpga/projects/output_files/led_patterns.mif source_file = 1, /home/benny/work/fpga/projects/led_patterns.mif source_file = 1, /home/benny/work/fpga/projects/rom0.qip source_file = 1, /home/benny/work/fpga/projects/rom0.v +source_file = 1, /home/benny/work/fpga/projects/ram16.qip +source_file = 1, /home/benny/work/fpga/projects/ram16.v source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc @@ -19,6 +21,8 @@ source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf source_file = 1, /home/benny/work/fpga/projects/rom/gw03.hex source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf +source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf +source_file = 1, /home/benny/work/fpga/projects/db/decode_jsa.tdf design_name = spectrum instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 @@ -53,7 +57,6 @@ instance = comp, \counter[9] , counter[9], spectrum, 1 instance = comp, \counter[10]~39 , counter[10]~39, spectrum, 1 instance = comp, \counter[10] , counter[10], spectrum, 1 instance = comp, \counter[11]~41 , counter[11]~41, spectrum, 1 -instance = comp, \counter[11]~feeder , counter[11]~feeder, spectrum, 1 instance = comp, \counter[11] , counter[11], spectrum, 1 instance = comp, \counter[12]~43 , counter[12]~43, spectrum, 1 instance = comp, \counter[12] , counter[12], spectrum, 1 @@ -71,71 +74,63 @@ instance = comp, \counter[18]~55 , counter[18]~55, spectrum, 1 instance = comp, \counter[18] , counter[18], spectrum, 1 instance = comp, \counter[19]~57 , counter[19]~57, spectrum, 1 instance = comp, \counter[19] , counter[19], spectrum, 1 +instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1 +instance = comp, \counter[20] , counter[20], spectrum, 1 +instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1 +instance = comp, \counter[21] , counter[21], spectrum, 1 instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 -instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1 -instance = comp, \counter[20] , counter[20], spectrum, 1 -instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1 -instance = comp, \counter[21] , counter[21], spectrum, 1 -instance = comp, \Equal0~7 , Equal0~7, spectrum, 1 -instance = comp, \address[0]~39 , address[0]~39, spectrum, 1 -instance = comp, \address[0] , address[0], spectrum, 1 -instance = comp, \address[1]~13 , address[1]~13, spectrum, 1 instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 -instance = comp, \address[1] , address[1], spectrum, 1 -instance = comp, \address[2]~15 , address[2]~15, spectrum, 1 -instance = comp, \address[2] , address[2], spectrum, 1 -instance = comp, \address[3]~17 , address[3]~17, spectrum, 1 -instance = comp, \address[3] , address[3], spectrum, 1 -instance = comp, \address[4]~19 , address[4]~19, spectrum, 1 -instance = comp, \address[4] , address[4], spectrum, 1 -instance = comp, \address[5]~21 , address[5]~21, spectrum, 1 -instance = comp, \address[5] , address[5], spectrum, 1 -instance = comp, \address[6]~23 , address[6]~23, spectrum, 1 -instance = comp, \address[6] , address[6], spectrum, 1 -instance = comp, \address[7]~25 , address[7]~25, spectrum, 1 -instance = comp, \address[7] , address[7], spectrum, 1 -instance = comp, \address[8]~27 , address[8]~27, spectrum, 1 -instance = comp, \address[8] , address[8], spectrum, 1 -instance = comp, \address[9]~29 , address[9]~29, spectrum, 1 -instance = comp, \address[9] , address[9], spectrum, 1 -instance = comp, \address[10]~31 , address[10]~31, spectrum, 1 -instance = comp, \address[10] , address[10], spectrum, 1 -instance = comp, \address[11]~33 , address[11]~33, spectrum, 1 -instance = comp, \address[11] , address[11], spectrum, 1 -instance = comp, \address[12]~35 , address[12]~35, spectrum, 1 -instance = comp, \address[12] , address[12], spectrum, 1 -instance = comp, \address[13]~37 , address[13]~37, spectrum, 1 -instance = comp, \address[13] , address[13], spectrum, 1 +instance = comp, \A[0]~39 , A[0]~39, spectrum, 1 +instance = comp, \A[0] , A[0], spectrum, 1 +instance = comp, \A[1]~13 , A[1]~13, spectrum, 1 +instance = comp, \A[1] , A[1], spectrum, 1 +instance = comp, \A[2]~15 , A[2]~15, spectrum, 1 +instance = comp, \A[2] , A[2], spectrum, 1 +instance = comp, \A[3]~17 , A[3]~17, spectrum, 1 +instance = comp, \A[3] , A[3], spectrum, 1 +instance = comp, \A[4]~19 , A[4]~19, spectrum, 1 +instance = comp, \A[4] , A[4], spectrum, 1 +instance = comp, \A[5]~21 , A[5]~21, spectrum, 1 +instance = comp, \A[5] , A[5], spectrum, 1 +instance = comp, \A[6]~23 , A[6]~23, spectrum, 1 +instance = comp, \A[6] , A[6], spectrum, 1 +instance = comp, \A[7]~25 , A[7]~25, spectrum, 1 +instance = comp, \A[7] , A[7], spectrum, 1 +instance = comp, \A[8]~27 , A[8]~27, spectrum, 1 +instance = comp, \A[8] , A[8], spectrum, 1 +instance = comp, \A[9]~29 , A[9]~29, spectrum, 1 +instance = comp, \A[9] , A[9], spectrum, 1 +instance = comp, \A[10]~31 , A[10]~31, spectrum, 1 +instance = comp, \A[10] , A[10], spectrum, 1 +instance = comp, \A[11]~33 , A[11]~33, spectrum, 1 +instance = comp, \A[11] , A[11], spectrum, 1 +instance = comp, \A[12]~35 , A[12]~35, spectrum, 1 +instance = comp, \A[12] , A[12], spectrum, 1 +instance = comp, \A[13]~37 , A[13]~37, spectrum, 1 +instance = comp, \A[13] , A[13], spectrum, 1 +instance = comp, \~GND , ~GND, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[3]~3, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~4, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~0, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~1, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~6, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~2, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~3, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 9b80f0c..074a56c 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 13:12:28") + (DATE "03/30/2022 13:47:24") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1643:1643:1643) (1694:1694:1694)) + (PORT i (2240:2240:2240) (2288:2288:2288)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1565:1565:1565) (1603:1603:1603)) + (PORT i (2683:2683:2683) (2776:2776:2776)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1737:1737:1737) (1749:1749:1749)) + (PORT i (2672:2672:2672) (2728:2728:2728)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1124:1124:1124) (1166:1166:1166)) + (PORT i (1887:1887:1887) (1922:1922:1922)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1456:1456:1456) (1512:1512:1512)) + (PORT i (2419:2419:2419) (2498:2498:2498)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (2115:2115:2115) (2173:2173:2173)) + (PORT i (1958:1958:1958) (2059:2059:2059)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (2428:2428:2428) (2433:2433:2433)) + (PORT i (2348:2348:2348) (2361:2361:2361)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (957:957:957) (1031:1031:1031)) + (PORT i (1275:1275:1275) (1275:1275:1275)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -148,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -177,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -205,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -233,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -247,7 +247,7 @@ (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -261,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -275,7 +275,7 @@ (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (346:346:346)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -289,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -317,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -331,7 +331,7 @@ (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -345,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -359,7 +359,7 @@ (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (341:341:341)) + (PORT dataa (264:264:264) (350:350:350)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -373,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -387,7 +387,7 @@ (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (333:333:333)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -401,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -415,7 +415,7 @@ (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (340:340:340)) + (PORT dataa (264:264:264) (350:350:350)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -429,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -443,31 +443,21 @@ (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT dataa (704:704:704) (765:765:765)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (318:318:318) (335:335:335)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -495,7 +485,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -509,9 +499,9 @@ (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (335:335:335)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (403:403:403) (479:479:479)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -523,7 +513,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -551,7 +541,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -565,9 +555,9 @@ (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (335:335:335)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (403:403:403) (479:479:479)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -579,7 +569,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -607,7 +597,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -635,7 +625,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -663,7 +653,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -691,7 +681,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -700,102 +690,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (252:252:252) (336:336:336)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (226:226:226) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (250:250:250) (336:336:336)) - (PORT datac (224:224:224) (302:302:302)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (PORT datab (251:251:251) (337:337:337)) - (PORT datac (381:381:381) (440:440:440)) - (PORT datad (225:225:225) (297:297:297)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (347:347:347)) - (PORT datab (262:262:262) (344:344:344)) - (PORT datac (226:226:226) (308:308:308)) - (PORT datad (228:228:228) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~3) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (346:346:346)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (370:370:370)) - (PORT datab (345:345:345) (370:370:370)) - (PORT datac (335:335:335) (354:354:354)) - (PORT datad (589:589:589) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE counter\[20\]\~59) @@ -815,7 +709,7 @@ (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -840,7 +734,7 @@ (INSTANCE counter\[21\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1896:1896:1896) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -851,11 +745,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datac (669:669:669) (728:728:728)) - (PORT datad (646:646:646) (700:700:700)) + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -863,44 +761,80 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~39) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (663:663:663)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (330:330:330) (347:347:347)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (252:252:252) (341:341:341)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1877:1877:1877)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (381:381:381) (442:442:442)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~13) + (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (268:268:268) (356:356:356)) - (PORT datab (261:261:261) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (447:447:447) (515:515:515)) + (PORT datab (406:406:406) (480:480:480)) + (PORT datac (566:566:566) (611:611:611)) + (PORT datad (576:576:576) (620:620:620)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (265:265:265) (348:348:348)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (416:416:416)) + (PORT datab (345:345:345) (380:380:380)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (640:640:640) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -910,10 +844,10 @@ (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (763:763:763)) - (PORT datab (674:674:674) (730:730:730)) - (PORT datac (613:613:613) (625:625:625)) - (PORT datad (181:181:181) (210:210:210)) + (PORT dataa (888:888:888) (955:955:955)) + (PORT datab (926:926:926) (973:973:973)) + (PORT datac (615:615:615) (635:635:635)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -922,13 +856,53 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[0\]\~39) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT datad (330:330:330) (344:344:344)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (522:522:522)) + (PORT datab (618:618:618) (683:683:683)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -939,7 +913,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~15) + (INSTANCE A\[2\]\~15) (DELAY (ABSOLUTE (PORT datab (261:261:261) (343:343:343)) @@ -953,12 +927,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE A\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -969,10 +943,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[3\]\~17) + (INSTANCE A\[3\]\~17) (DELAY (ABSOLUTE - (PORT datab (282:282:282) (364:364:364)) + (PORT datab (262:262:262) (344:344:344)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -983,12 +957,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[3\]) + (INSTANCE A\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -999,7 +973,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[4\]\~19) + (INSTANCE A\[4\]\~19) (DELAY (ABSOLUTE (PORT dataa (265:265:265) (351:351:351)) @@ -1013,12 +987,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[4\]) + (INSTANCE A\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1029,7 +1003,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[5\]\~21) + (INSTANCE A\[5\]\~21) (DELAY (ABSOLUTE (PORT datab (263:263:263) (345:345:345)) @@ -1043,12 +1017,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[5\]) + (INSTANCE A\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1059,7 +1033,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[6\]\~23) + (INSTANCE A\[6\]\~23) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (353:353:353)) @@ -1073,12 +1047,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[6\]) + (INSTANCE A\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1089,7 +1063,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[7\]\~25) + (INSTANCE A\[7\]\~25) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (353:353:353)) @@ -1103,12 +1077,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[7\]) + (INSTANCE A\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1119,7 +1093,67 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[8\]\~27) + (INSTANCE A\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (480:480:480)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE A\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (816:816:816) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE A\[10\]\~31) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1133,12 +1167,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[8\]) + (INSTANCE A\[10\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1149,7 +1183,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[9\]\~29) + (INSTANCE A\[11\]\~33) (DELAY (ABSOLUTE (PORT datab (264:264:264) (347:347:347)) @@ -1163,12 +1197,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[9\]) + (INSTANCE A\[11\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1179,67 +1213,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[10\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[11\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[12\]\~35) + (INSTANCE A\[12\]\~35) (DELAY (ABSOLUTE (PORT dataa (266:266:266) (352:352:352)) @@ -1253,12 +1227,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[12\]) + (INSTANCE A\[12\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1269,7 +1243,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[13\]\~37) + (INSTANCE A\[13\]\~37) (DELAY (ABSOLUTE (PORT datad (258:258:258) (327:327:327)) @@ -1280,12 +1254,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[13\]) + (INSTANCE A\[13\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (795:795:795) (792:792:792)) + (PORT ena (816:816:816) (814:814:814)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -1294,13 +1268,959 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1043:1043:1043) (1097:1097:1097)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1047:1047:1047) (1146:1146:1146)) + (PORT d[1] (1492:1492:1492) (1562:1562:1562)) + (PORT d[2] (954:954:954) (1036:1036:1036)) + (PORT d[3] (1018:1018:1018) (1075:1075:1075)) + (PORT d[4] (1018:1018:1018) (1075:1075:1075)) + (PORT d[5] (783:783:783) (838:838:838)) + (PORT d[6] (783:783:783) (838:838:838)) + (PORT d[7] (783:783:783) (838:838:838)) + (PORT d[8] (783:783:783) (838:838:838)) + (PORT d[9] (783:783:783) (838:838:838)) + (PORT d[10] (783:783:783) (838:838:838)) + (PORT d[11] (783:783:783) (838:838:838)) + (PORT d[12] (783:783:783) (838:838:838)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1809:1809:1809)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1048:1048:1048) (1102:1102:1102)) + (PORT clk (1823:1823:1823) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1127:1127:1127)) + (PORT d[1] (1493:1493:1493) (1562:1562:1562)) + (PORT d[2] (979:979:979) (1058:1058:1058)) + (PORT d[3] (1250:1250:1250) (1312:1312:1312)) + (PORT d[4] (967:967:967) (1025:1025:1025)) + (PORT d[5] (1558:1558:1558) (1643:1643:1643)) + (PORT d[6] (1237:1237:1237) (1323:1323:1323)) + (PORT d[7] (1284:1284:1284) (1363:1363:1363)) + (PORT d[8] (1214:1214:1214) (1273:1273:1273)) + (PORT d[9] (1235:1235:1235) (1302:1302:1302)) + (PORT d[10] (1250:1250:1250) (1318:1318:1318)) + (PORT d[11] (1232:1232:1232) (1314:1314:1314)) + (PORT d[12] (1287:1287:1287) (1358:1358:1358)) + (PORT clk (1819:1819:1819) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1815:1815:1815)) + (PORT d[0] (903:903:903) (890:890:890)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1816:1816:1816)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1006:1006:1006) (1061:1061:1061)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1030:1030:1030) (1132:1132:1132)) + (PORT d[1] (1194:1194:1194) (1270:1270:1270)) + (PORT d[2] (957:957:957) (1039:1039:1039)) + (PORT d[3] (1025:1025:1025) (1086:1086:1086)) + (PORT d[4] (1025:1025:1025) (1086:1086:1086)) + (PORT d[5] (813:813:813) (881:881:881)) + (PORT d[6] (813:813:813) (881:881:881)) + (PORT d[7] (813:813:813) (881:881:881)) + (PORT d[8] (813:813:813) (881:881:881)) + (PORT d[9] (813:813:813) (881:881:881)) + (PORT d[10] (813:813:813) (881:881:881)) + (PORT d[11] (813:813:813) (881:881:881)) + (PORT d[12] (813:813:813) (881:881:881)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1011:1011:1011) (1066:1066:1066)) + (PORT clk (1821:1821:1821) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1054:1054:1054) (1156:1156:1156)) + (PORT d[1] (960:960:960) (1039:1039:1039)) + (PORT d[2] (1276:1276:1276) (1350:1350:1350)) + (PORT d[3] (1249:1249:1249) (1279:1279:1279)) + (PORT d[4] (941:941:941) (1014:1014:1014)) + (PORT d[5] (1553:1553:1553) (1633:1633:1633)) + (PORT d[6] (1275:1275:1275) (1334:1334:1334)) + (PORT d[7] (1286:1286:1286) (1364:1364:1364)) + (PORT d[8] (1442:1442:1442) (1487:1487:1487)) + (PORT d[9] (1239:1239:1239) (1309:1309:1309)) + (PORT d[10] (1259:1259:1259) (1333:1333:1333)) + (PORT d[11] (1243:1243:1243) (1305:1305:1305)) + (PORT d[12] (1271:1271:1271) (1318:1318:1318)) + (PORT clk (1817:1817:1817) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1814:1814:1814)) + (PORT d[0] (908:908:908) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1352:1352:1352) (1400:1400:1400)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1071:1071:1071) (1146:1146:1146)) + (PORT d[1] (935:935:935) (1004:1004:1004)) + (PORT d[2] (1531:1531:1531) (1621:1621:1621)) + (PORT d[3] (1349:1349:1349) (1401:1401:1401)) + (PORT d[4] (1349:1349:1349) (1401:1401:1401)) + (PORT d[5] (773:773:773) (814:814:814)) + (PORT d[6] (773:773:773) (814:814:814)) + (PORT d[7] (773:773:773) (814:814:814)) + (PORT d[8] (773:773:773) (814:814:814)) + (PORT d[9] (773:773:773) (814:814:814)) + (PORT d[10] (773:773:773) (814:814:814)) + (PORT d[11] (773:773:773) (814:814:814)) + (PORT d[12] (773:773:773) (814:814:814)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1357:1357:1357) (1405:1405:1405)) + (PORT clk (1824:1824:1824) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1049:1049:1049) (1122:1122:1122)) + (PORT d[1] (1503:1503:1503) (1591:1591:1591)) + (PORT d[2] (917:917:917) (979:979:979)) + (PORT d[3] (1464:1464:1464) (1521:1521:1521)) + (PORT d[4] (935:935:935) (996:996:996)) + (PORT d[5] (1058:1058:1058) (1128:1128:1128)) + (PORT d[6] (1250:1250:1250) (1319:1319:1319)) + (PORT d[7] (1047:1047:1047) (1105:1105:1105)) + (PORT d[8] (1486:1486:1486) (1542:1542:1542)) + (PORT d[9] (1254:1254:1254) (1312:1312:1312)) + (PORT d[10] (1242:1242:1242) (1297:1297:1297)) + (PORT d[11] (1250:1250:1250) (1319:1319:1319)) + (PORT d[12] (1251:1251:1251) (1299:1299:1299)) + (PORT clk (1820:1820:1820) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1817:1817:1817)) + (PORT d[0] (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1362:1362:1362) (1429:1429:1429)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (762:762:762) (824:824:824)) + (PORT d[1] (644:644:644) (706:706:706)) + (PORT d[2] (1543:1543:1543) (1614:1614:1614)) + (PORT d[3] (664:664:664) (693:693:693)) + (PORT d[4] (664:664:664) (693:693:693)) + (PORT d[5] (484:484:484) (522:522:522)) + (PORT d[6] (484:484:484) (522:522:522)) + (PORT d[7] (484:484:484) (522:522:522)) + (PORT d[8] (484:484:484) (522:522:522)) + (PORT d[9] (484:484:484) (522:522:522)) + (PORT d[10] (484:484:484) (522:522:522)) + (PORT d[11] (484:484:484) (522:522:522)) + (PORT d[12] (484:484:484) (522:522:522)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1367:1367:1367) (1434:1434:1434)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (735:735:735) (812:812:812)) + (PORT d[1] (1534:1534:1534) (1599:1599:1599)) + (PORT d[2] (1545:1545:1545) (1615:1615:1615)) + (PORT d[3] (659:659:659) (709:709:709)) + (PORT d[4] (664:664:664) (725:725:725)) + (PORT d[5] (722:722:722) (794:794:794)) + (PORT d[6] (766:766:766) (839:839:839)) + (PORT d[7] (749:749:749) (827:827:827)) + (PORT d[8] (1517:1517:1517) (1590:1590:1590)) + (PORT d[9] (761:761:761) (822:822:822)) + (PORT d[10] (979:979:979) (1037:1037:1037)) + (PORT d[11] (734:734:734) (803:803:803)) + (PORT d[12] (940:940:940) (991:991:991)) + (PORT clk (1821:1821:1821) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT d[0] (628:628:628) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1819:1819:1819)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1580:1580:1580) (1693:1693:1693)) + (PORT d[1] (1272:1272:1272) (1354:1354:1354)) + (PORT d[2] (1245:1245:1245) (1308:1308:1308)) + (PORT d[3] (1263:1263:1263) (1339:1339:1339)) + (PORT d[4] (1283:1283:1283) (1370:1370:1370)) + (PORT d[5] (1569:1569:1569) (1701:1701:1701)) + (PORT d[6] (1243:1243:1243) (1329:1329:1329)) + (PORT d[7] (1231:1231:1231) (1310:1310:1310)) + (PORT d[8] (1267:1267:1267) (1363:1363:1363)) + (PORT d[9] (1273:1273:1273) (1361:1361:1361)) + (PORT d[10] (1275:1275:1275) (1366:1366:1366)) + (PORT d[11] (1259:1259:1259) (1344:1344:1344)) + (PORT d[12] (1532:1532:1532) (1614:1614:1614)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1172:1172:1172) (1188:1188:1188)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1320:1320:1320) (1440:1440:1440)) + (PORT d[1] (1259:1259:1259) (1353:1353:1353)) + (PORT d[2] (1264:1264:1264) (1323:1323:1323)) + (PORT d[3] (1324:1324:1324) (1419:1419:1419)) + (PORT d[4] (1316:1316:1316) (1418:1418:1418)) + (PORT d[5] (1564:1564:1564) (1691:1691:1691)) + (PORT d[6] (1229:1229:1229) (1326:1326:1326)) + (PORT d[7] (1239:1239:1239) (1332:1332:1332)) + (PORT d[8] (1280:1280:1280) (1393:1393:1393)) + (PORT d[9] (1254:1254:1254) (1351:1351:1351)) + (PORT d[10] (1258:1258:1258) (1357:1357:1357)) + (PORT d[11] (1267:1267:1267) (1367:1367:1367)) + (PORT d[12] (1266:1266:1266) (1351:1351:1351)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1215:1215:1215) (1202:1202:1202)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (428:428:428) (485:485:485)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (643:643:643) (706:706:706)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -1323,7 +2243,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) + (PORT datad (219:219:219) (289:289:289)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1342,1064 +2262,38 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1232:1232:1232) (1314:1314:1314)) - (PORT d[1] (1273:1273:1273) (1381:1381:1381)) - (PORT d[2] (1342:1342:1342) (1456:1456:1456)) - (PORT d[3] (1317:1317:1317) (1435:1435:1435)) - (PORT d[4] (1249:1249:1249) (1341:1341:1341)) - (PORT d[5] (1362:1362:1362) (1458:1458:1458)) - (PORT d[6] (1704:1704:1704) (1869:1869:1869)) - (PORT d[7] (1310:1310:1310) (1434:1434:1434)) - (PORT d[8] (1316:1316:1316) (1419:1419:1419)) - (PORT d[9] (1359:1359:1359) (1447:1447:1447)) - (PORT d[10] (1320:1320:1320) (1425:1425:1425)) - (PORT d[11] (1570:1570:1570) (1654:1654:1654)) - (PORT d[12] (1289:1289:1289) (1390:1390:1390)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (1167:1167:1167) (1189:1189:1189)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1246:1246:1246)) - (PORT d[1] (973:973:973) (1069:1069:1069)) - (PORT d[2] (1034:1034:1034) (1138:1138:1138)) - (PORT d[3] (1341:1341:1341) (1439:1439:1439)) - (PORT d[4] (1248:1248:1248) (1333:1333:1333)) - (PORT d[5] (1325:1325:1325) (1408:1408:1408)) - (PORT d[6] (1491:1491:1491) (1664:1664:1664)) - (PORT d[7] (1263:1263:1263) (1339:1339:1339)) - (PORT d[8] (1326:1326:1326) (1417:1417:1417)) - (PORT d[9] (1388:1388:1388) (1482:1482:1482)) - (PORT d[10] (1305:1305:1305) (1406:1406:1406)) - (PORT d[11] (1274:1274:1274) (1349:1349:1349)) - (PORT d[12] (1340:1340:1340) (1438:1438:1438)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (954:954:954) (925:925:925)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~0) (DELAY (ABSOLUTE - (PORT datab (956:956:956) (1072:1072:1072)) - (PORT datac (880:880:880) (883:883:883)) - (PORT datad (605:605:605) (612:612:612)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1457:1457:1457) (1535:1535:1535)) - (PORT d[1] (1538:1538:1538) (1599:1599:1599)) - (PORT d[2] (1565:1565:1565) (1669:1669:1669)) - (PORT d[3] (1248:1248:1248) (1294:1294:1294)) - (PORT d[4] (1607:1607:1607) (1738:1738:1738)) - (PORT d[5] (1904:1904:1904) (2043:2043:2043)) - (PORT d[6] (1250:1250:1250) (1306:1306:1306)) - (PORT d[7] (1340:1340:1340) (1441:1441:1441)) - (PORT d[8] (1887:1887:1887) (2029:2029:2029)) - (PORT d[9] (1230:1230:1230) (1303:1303:1303)) - (PORT d[10] (1415:1415:1415) (1517:1517:1517)) - (PORT d[11] (1208:1208:1208) (1273:1273:1273)) - (PORT d[12] (1256:1256:1256) (1338:1338:1338)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1141:1141:1141) (1128:1128:1128)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1500:1500:1500) (1594:1594:1594)) - (PORT d[1] (1355:1355:1355) (1470:1470:1470)) - (PORT d[2] (1591:1591:1591) (1703:1703:1703)) - (PORT d[3] (1336:1336:1336) (1417:1417:1417)) - (PORT d[4] (1313:1313:1313) (1422:1422:1422)) - (PORT d[5] (1595:1595:1595) (1733:1733:1733)) - (PORT d[6] (1268:1268:1268) (1373:1373:1373)) - (PORT d[7] (1255:1255:1255) (1355:1355:1355)) - (PORT d[8] (1615:1615:1615) (1750:1750:1750)) - (PORT d[9] (1326:1326:1326) (1421:1421:1421)) - (PORT d[10] (1812:1812:1812) (1937:1937:1937)) - (PORT d[11] (1293:1293:1293) (1402:1402:1402)) - (PORT d[12] (1561:1561:1561) (1676:1676:1676)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1207:1207:1207) (1256:1256:1256)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (652:652:652)) - (PORT datac (877:877:877) (907:907:907)) - (PORT datad (1342:1342:1342) (1396:1396:1396)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1238:1238:1238) (1323:1323:1323)) - (PORT d[1] (1282:1282:1282) (1374:1374:1374)) - (PORT d[2] (1603:1603:1603) (1716:1716:1716)) - (PORT d[3] (1381:1381:1381) (1467:1467:1467)) - (PORT d[4] (1282:1282:1282) (1376:1376:1376)) - (PORT d[5] (1277:1277:1277) (1395:1395:1395)) - (PORT d[6] (1716:1716:1716) (1879:1879:1879)) - (PORT d[7] (1344:1344:1344) (1433:1433:1433)) - (PORT d[8] (1329:1329:1329) (1433:1433:1433)) - (PORT d[9] (1412:1412:1412) (1507:1507:1507)) - (PORT d[10] (1764:1764:1764) (1843:1843:1843)) - (PORT d[11] (1578:1578:1578) (1656:1656:1656)) - (PORT d[12] (1322:1322:1322) (1422:1422:1422)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1880:1880:1880)) - (PORT d[0] (1242:1242:1242) (1194:1194:1194)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (1054:1054:1054)) - (PORT d[1] (1258:1258:1258) (1343:1343:1343)) - (PORT d[2] (1047:1047:1047) (1135:1135:1135)) - (PORT d[3] (1074:1074:1074) (1167:1167:1167)) - (PORT d[4] (966:966:966) (1059:1059:1059)) - (PORT d[5] (1239:1239:1239) (1332:1332:1332)) - (PORT d[6] (1463:1463:1463) (1631:1631:1631)) - (PORT d[7] (1262:1262:1262) (1338:1338:1338)) - (PORT d[8] (1053:1053:1053) (1156:1156:1156)) - (PORT d[9] (1100:1100:1100) (1206:1206:1206)) - (PORT d[10] (1512:1512:1512) (1581:1581:1581)) - (PORT d[11] (1273:1273:1273) (1348:1348:1348)) - (PORT d[12] (1313:1313:1313) (1405:1405:1405)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (924:924:924) (953:953:953)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT datab (980:980:980) (1094:1094:1094)) - (PORT datac (902:902:902) (940:940:940)) - (PORT datad (596:596:596) (601:601:601)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (988:988:988)) - (PORT d[1] (979:979:979) (1053:1053:1053)) - (PORT d[2] (1080:1080:1080) (1156:1156:1156)) - (PORT d[3] (1058:1058:1058) (1130:1130:1130)) - (PORT d[4] (956:956:956) (1028:1028:1028)) - (PORT d[5] (1006:1006:1006) (1083:1083:1083)) - (PORT d[6] (1424:1424:1424) (1563:1563:1563)) - (PORT d[7] (1240:1240:1240) (1316:1316:1316)) - (PORT d[8] (1625:1625:1625) (1738:1738:1738)) - (PORT d[9] (1086:1086:1086) (1162:1162:1162)) - (PORT d[10] (1042:1042:1042) (1125:1125:1125)) - (PORT d[11] (1300:1300:1300) (1361:1361:1361)) - (PORT d[12] (1299:1299:1299) (1370:1370:1370)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (908:908:908) (912:912:912)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1205:1205:1205) (1260:1260:1260)) - (PORT d[1] (651:651:651) (711:711:711)) - (PORT d[2] (713:713:713) (781:781:781)) - (PORT d[3] (760:760:760) (830:830:830)) - (PORT d[4] (659:659:659) (721:721:721)) - (PORT d[5] (734:734:734) (814:814:814)) - (PORT d[6] (761:761:761) (832:832:832)) - (PORT d[7] (740:740:740) (819:819:819)) - (PORT d[8] (756:756:756) (828:828:828)) - (PORT d[9] (769:769:769) (847:847:847)) - (PORT d[10] (1226:1226:1226) (1292:1292:1292)) - (PORT d[11] (741:741:741) (813:813:813)) - (PORT d[12] (751:751:751) (826:826:826)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (642:642:642) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (939:939:939)) - (PORT datac (648:648:648) (723:723:723)) - (PORT datad (603:603:603) (610:610:610)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT datab (628:628:628) (637:637:637)) + (PORT datac (922:922:922) (922:922:922)) + (PORT datad (973:973:973) (1040:1040:1040)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1471:1471:1471) (1551:1551:1551)) - (PORT d[1] (1529:1529:1529) (1590:1590:1590)) - (PORT d[2] (1557:1557:1557) (1660:1660:1660)) - (PORT d[3] (988:988:988) (1045:1045:1045)) - (PORT d[4] (976:976:976) (1062:1062:1062)) - (PORT d[5] (1604:1604:1604) (1749:1749:1749)) - (PORT d[6] (996:996:996) (1079:1079:1079)) - (PORT d[7] (948:948:948) (1026:1026:1026)) - (PORT d[8] (1601:1601:1601) (1742:1742:1742)) - (PORT d[9] (998:998:998) (1064:1064:1064)) - (PORT d[10] (979:979:979) (1057:1057:1057)) - (PORT d[11] (958:958:958) (1040:1040:1040)) - (PORT d[12] (969:969:969) (1047:1047:1047)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (904:904:904) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1219:1219:1219) (1307:1307:1307)) - (PORT d[1] (1255:1255:1255) (1323:1323:1323)) - (PORT d[2] (1279:1279:1279) (1381:1381:1381)) - (PORT d[3] (1279:1279:1279) (1328:1328:1328)) - (PORT d[4] (1603:1603:1603) (1733:1733:1733)) - (PORT d[5] (1603:1603:1603) (1748:1748:1748)) - (PORT d[6] (1281:1281:1281) (1369:1369:1369)) - (PORT d[7] (1245:1245:1245) (1325:1325:1325)) - (PORT d[8] (1600:1600:1600) (1741:1741:1741)) - (PORT d[9] (1266:1266:1266) (1335:1335:1335)) - (PORT d[10] (1838:1838:1838) (1967:1967:1967)) - (PORT d[11] (1283:1283:1283) (1373:1373:1373)) - (PORT d[12] (1245:1245:1245) (1330:1330:1330)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1151:1151:1151) (1179:1179:1179)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT datab (640:640:640) (651:651:651)) - (PORT datac (859:859:859) (855:855:855)) - (PORT datad (794:794:794) (853:853:853)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1508:1508:1508) (1612:1612:1612)) - (PORT d[1] (1896:1896:1896) (2041:2041:2041)) - (PORT d[2] (1251:1251:1251) (1359:1359:1359)) - (PORT d[3] (1319:1319:1319) (1368:1368:1368)) - (PORT d[4] (1294:1294:1294) (1407:1407:1407)) - (PORT d[5] (1248:1248:1248) (1360:1360:1360)) - (PORT d[6] (1297:1297:1297) (1411:1411:1411)) - (PORT d[7] (1260:1260:1260) (1366:1366:1366)) - (PORT d[8] (1608:1608:1608) (1726:1726:1726)) - (PORT d[9] (1309:1309:1309) (1408:1408:1408)) - (PORT d[10] (1860:1860:1860) (1990:1990:1990)) - (PORT d[11] (1271:1271:1271) (1381:1381:1381)) - (PORT d[12] (1527:1527:1527) (1637:1637:1637)) + (PORT d[0] (1588:1588:1588) (1696:1696:1696)) + (PORT d[1] (980:980:980) (1067:1067:1067)) + (PORT d[2] (995:995:995) (1068:1068:1068)) + (PORT d[3] (1044:1044:1044) (1123:1123:1123)) + (PORT d[4] (975:975:975) (1061:1061:1061)) + (PORT d[5] (1570:1570:1570) (1702:1702:1702)) + (PORT d[6] (974:974:974) (1057:1057:1057)) + (PORT d[7] (950:950:950) (1029:1029:1029)) + (PORT d[8] (1007:1007:1007) (1107:1107:1107)) + (PORT d[9] (1511:1511:1511) (1583:1583:1583)) + (PORT d[10] (1476:1476:1476) (1552:1552:1552)) + (PORT d[11] (949:949:949) (1029:1029:1029)) + (PORT d[12] (993:993:993) (1056:1056:1056)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -2413,7 +2307,7 @@ (DELAY (ABSOLUTE (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1193:1193:1193) (1239:1239:1239)) + (PORT d[0] (897:897:897) (921:921:921)) ) ) ) @@ -2484,20 +2378,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1667:1667:1667)) - (PORT d[1] (1626:1626:1626) (1776:1776:1776)) - (PORT d[2] (1557:1557:1557) (1668:1668:1668)) - (PORT d[3] (1644:1644:1644) (1709:1709:1709)) - (PORT d[4] (1593:1593:1593) (1715:1715:1715)) - (PORT d[5] (1575:1575:1575) (1680:1680:1680)) - (PORT d[6] (1565:1565:1565) (1670:1670:1670)) - (PORT d[7] (1531:1531:1531) (1632:1632:1632)) - (PORT d[8] (1555:1555:1555) (1659:1659:1659)) - (PORT d[9] (1587:1587:1587) (1682:1682:1682)) - (PORT d[10] (1533:1533:1533) (1638:1638:1638)) - (PORT d[11] (1559:1559:1559) (1667:1667:1667)) - (PORT d[12] (1527:1527:1527) (1639:1639:1639)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1251:1251:1251) (1346:1346:1346)) + (PORT d[1] (1263:1263:1263) (1359:1359:1359)) + (PORT d[2] (1230:1230:1230) (1312:1312:1312)) + (PORT d[3] (1305:1305:1305) (1378:1378:1378)) + (PORT d[4] (1268:1268:1268) (1374:1374:1374)) + (PORT d[5] (1558:1558:1558) (1661:1661:1661)) + (PORT d[6] (1255:1255:1255) (1359:1359:1359)) + (PORT d[7] (1243:1243:1243) (1338:1338:1338)) + (PORT d[8] (1284:1284:1284) (1400:1400:1400)) + (PORT d[9] (1257:1257:1257) (1358:1358:1358)) + (PORT d[10] (1261:1261:1261) (1362:1362:1362)) + (PORT d[11] (1244:1244:1244) (1341:1341:1341)) + (PORT d[12] (1513:1513:1513) (1597:1597:1597)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -2509,8 +2403,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (1489:1489:1489) (1442:1442:1442)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (1181:1181:1181) (1146:1146:1146)) ) ) ) @@ -2519,7 +2413,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2529,7 +2423,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) + (PORT clk (1807:1807:1807) (1834:1834:1834)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2543,7 +2437,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (992:992:992) (997:997:997)) ) ) ) @@ -2552,7 +2446,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) ) ) ) @@ -2561,7 +2455,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2571,22 +2465,119 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (993:993:993) (998:998:998)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT datab (626:626:626) (635:635:635)) - (PORT datac (909:909:909) (911:911:911)) - (PORT datad (1120:1120:1120) (1222:1222:1222)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (627:627:627) (648:648:648)) + (PORT datab (722:722:722) (791:791:791)) + (PORT datac (902:902:902) (941:941:941)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1869:1869:1869) (2011:2011:2011)) + (PORT d[1] (1219:1219:1219) (1293:1293:1293)) + (PORT d[2] (1262:1262:1262) (1328:1328:1328)) + (PORT d[3] (1315:1315:1315) (1385:1385:1385)) + (PORT d[4] (1268:1268:1268) (1345:1345:1345)) + (PORT d[5] (1878:1878:1878) (2013:2013:2013)) + (PORT d[6] (1241:1241:1241) (1311:1311:1311)) + (PORT d[7] (1353:1353:1353) (1455:1455:1455)) + (PORT d[8] (1215:1215:1215) (1306:1306:1306)) + (PORT d[9] (1254:1254:1254) (1335:1335:1335)) + (PORT d[10] (1270:1270:1270) (1354:1354:1354)) + (PORT d[11] (1212:1212:1212) (1279:1279:1279)) + (PORT d[12] (1262:1262:1262) (1346:1346:1346)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1161:1161:1161) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -2595,19 +2586,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (965:965:965) (1030:1030:1030)) - (PORT d[1] (1241:1241:1241) (1329:1329:1329)) - (PORT d[2] (1056:1056:1056) (1157:1157:1157)) - (PORT d[3] (1088:1088:1088) (1177:1177:1177)) - (PORT d[4] (990:990:990) (1084:1084:1084)) - (PORT d[5] (1067:1067:1067) (1137:1137:1137)) - (PORT d[6] (1434:1434:1434) (1593:1593:1593)) - (PORT d[7] (1278:1278:1278) (1382:1382:1382)) - (PORT d[8] (1052:1052:1052) (1156:1156:1156)) - (PORT d[9] (1060:1060:1060) (1159:1159:1159)) - (PORT d[10] (1022:1022:1022) (1126:1126:1126)) - (PORT d[11] (1256:1256:1256) (1351:1351:1351)) - (PORT d[12] (1309:1309:1309) (1400:1400:1400)) + (PORT d[0] (767:767:767) (837:837:837)) + (PORT d[1] (644:644:644) (707:707:707)) + (PORT d[2] (1522:1522:1522) (1591:1591:1591)) + (PORT d[3] (1232:1232:1232) (1276:1276:1276)) + (PORT d[4] (948:948:948) (1009:1009:1009)) + (PORT d[5] (1053:1053:1053) (1132:1132:1132)) + (PORT d[6] (1198:1198:1198) (1268:1268:1268)) + (PORT d[7] (1251:1251:1251) (1321:1321:1321)) + (PORT d[8] (1492:1492:1492) (1563:1563:1563)) + (PORT d[9] (1256:1256:1256) (1307:1307:1307)) + (PORT d[10] (1239:1239:1239) (1292:1292:1292)) + (PORT d[11] (1213:1213:1213) (1275:1275:1275)) + (PORT d[12] (1242:1242:1242) (1308:1308:1308)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -2621,7 +2612,7 @@ (DELAY (ABSOLUTE (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (918:918:918) (941:941:941)) + (PORT d[0] (890:890:890) (887:887:887)) ) ) ) @@ -2687,233 +2678,39 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (921:921:921) (982:982:982)) - (PORT d[1] (652:652:652) (711:711:711)) - (PORT d[2] (1323:1323:1323) (1400:1400:1400)) - (PORT d[3] (1338:1338:1338) (1452:1452:1452)) - (PORT d[4] (929:929:929) (988:988:988)) - (PORT d[5] (1048:1048:1048) (1131:1131:1131)) - (PORT d[6] (1394:1394:1394) (1522:1522:1522)) - (PORT d[7] (1240:1240:1240) (1309:1309:1309)) - (PORT d[8] (1638:1638:1638) (1740:1740:1740)) - (PORT d[9] (1048:1048:1048) (1110:1110:1110)) - (PORT d[10] (1044:1044:1044) (1103:1103:1103)) - (PORT d[11] (1204:1204:1204) (1263:1263:1263)) - (PORT d[12] (1258:1258:1258) (1304:1304:1304)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (887:887:887) (888:888:888)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~2) (DELAY (ABSOLUTE - (PORT dataa (694:694:694) (743:743:743)) - (PORT datac (917:917:917) (955:955:955)) - (PORT datad (347:347:347) (362:362:362)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (938:938:938) (1009:1009:1009)) + (PORT datac (597:597:597) (600:600:600)) + (PORT datad (1037:1037:1037) (1036:1036:1036)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1471:1471:1471) (1578:1578:1578)) - (PORT d[1] (1888:1888:1888) (2030:2030:2030)) - (PORT d[2] (1880:1880:1880) (2006:2006:2006)) - (PORT d[3] (1371:1371:1371) (1434:1434:1434)) - (PORT d[4] (1886:1886:1886) (2001:2001:2001)) - (PORT d[5] (1321:1321:1321) (1439:1439:1439)) - (PORT d[6] (1325:1325:1325) (1443:1443:1443)) - (PORT d[7] (1261:1261:1261) (1367:1367:1367)) - (PORT d[8] (1312:1312:1312) (1427:1427:1427)) - (PORT d[9] (1283:1283:1283) (1377:1377:1377)) - (PORT d[10] (1803:1803:1803) (1907:1907:1907)) - (PORT d[11] (1272:1272:1272) (1382:1382:1382)) - (PORT d[12] (1256:1256:1256) (1366:1366:1366)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (1266:1266:1266) (1210:1210:1210)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1817:1817:1817) (1923:1923:1923)) - (PORT d[1] (1607:1607:1607) (1705:1705:1705)) - (PORT d[2] (1576:1576:1576) (1716:1716:1716)) - (PORT d[3] (1616:1616:1616) (1679:1679:1679)) - (PORT d[4] (1594:1594:1594) (1718:1718:1718)) - (PORT d[5] (1563:1563:1563) (1701:1701:1701)) - (PORT d[6] (1548:1548:1548) (1655:1655:1655)) - (PORT d[7] (1539:1539:1539) (1642:1642:1642)) - (PORT d[8] (1532:1532:1532) (1634:1634:1634)) - (PORT d[9] (1589:1589:1589) (1705:1705:1705)) - (PORT d[10] (1503:1503:1503) (1601:1601:1601)) - (PORT d[11] (1561:1561:1561) (1686:1686:1686)) - (PORT d[12] (1531:1531:1531) (1649:1649:1649)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1536:1536:1536) (1641:1641:1641)) + (PORT d[1] (1285:1285:1285) (1385:1385:1385)) + (PORT d[2] (1257:1257:1257) (1341:1341:1341)) + (PORT d[3] (1362:1362:1362) (1438:1438:1438)) + (PORT d[4] (1567:1567:1567) (1669:1669:1669)) + (PORT d[5] (1299:1299:1299) (1410:1410:1410)) + (PORT d[6] (1283:1283:1283) (1391:1391:1391)) + (PORT d[7] (1243:1243:1243) (1339:1339:1339)) + (PORT d[8] (1257:1257:1257) (1369:1369:1369)) + (PORT d[9] (1285:1285:1285) (1390:1390:1390)) + (PORT d[10] (1289:1289:1289) (1395:1395:1395)) + (PORT d[11] (1244:1244:1244) (1342:1342:1342)) + (PORT d[12] (1238:1238:1238) (1316:1316:1316)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) (TIMINGCHECK @@ -2925,8 +2722,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1872:1872:1872)) - (PORT d[0] (1495:1495:1495) (1543:1543:1543)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + (PORT d[0] (1140:1140:1140) (1166:1166:1166)) ) ) ) @@ -2935,7 +2732,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1873:1873:1873)) + (PORT clk (1843:1843:1843) (1870:1870:1870)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -2945,7 +2742,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1805:1805:1805) (1832:1832:1832)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -2959,7 +2756,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (990:990:990) (995:995:995)) ) ) ) @@ -2968,7 +2765,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) ) ) ) @@ -2977,7 +2774,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -2987,21 +2784,118 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1019:1019:1019) (1118:1118:1118)) + (PORT d[1] (928:928:928) (1013:1013:1013)) + (PORT d[2] (926:926:926) (1007:1007:1007)) + (PORT d[3] (1249:1249:1249) (1279:1279:1279)) + (PORT d[4] (1509:1509:1509) (1612:1612:1612)) + (PORT d[5] (1306:1306:1306) (1397:1397:1397)) + (PORT d[6] (1247:1247:1247) (1313:1313:1313)) + (PORT d[7] (1321:1321:1321) (1414:1414:1414)) + (PORT d[8] (1471:1471:1471) (1521:1521:1521)) + (PORT d[9] (1265:1265:1265) (1341:1341:1341)) + (PORT d[10] (1259:1259:1259) (1333:1333:1333)) + (PORT d[11] (1270:1270:1270) (1337:1337:1337)) + (PORT d[12] (1271:1271:1271) (1319:1319:1319)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (909:909:909) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) (DELAY (ABSOLUTE - (PORT datab (636:636:636) (645:645:645)) - (PORT datac (906:906:906) (905:905:905)) - (PORT datad (1123:1123:1123) (1224:1224:1224)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (992:992:992) (1066:1066:1066)) + (PORT datac (604:604:604) (608:608:608)) + (PORT datad (1039:1039:1039) (1055:1055:1055)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) diff --git a/spectrum.qsf b/spectrum.qsf index 6f18c4a..527833d 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -410,4 +410,5 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name MIF_FILE output_files/led_patterns.mif set_global_assignment -name MIF_FILE led_patterns.mif set_global_assignment -name QIP_FILE rom0.qip +set_global_assignment -name QIP_FILE ram16.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.v b/spectrum.v index 496dc28..8dab1aa 100644 --- a/spectrum.v +++ b/spectrum.v @@ -12,13 +12,42 @@ rom0 rom( .q(mem_data) ); + +reg [15:0] A; // Global address bus +wire [7:0] D; // CPU data bus +wire [7:0] ram_data; // Internal 16K RAM data +wire RamWE; +// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0; +assign RamWE = 0; +wire[12:0] vram_address; +wire[7:0] vram_data; + +ram16 ram0( + .clock(CLOCK_50), + + .address_a({12'b0, A[2:0]}), + .data_a(D), + .q_a(ram_data), + .wren_a(0), + +// .address_b({1'b0, vram_address}), + .address_b(A[13:0]), + .data_b(8'b0), + .q_b(vram_data), + .wren_b(0) +); + reg[21:0] counter; always @(posedge CLOCK_50) begin counter <= counter + 1; if (counter == 0) + begin address <= address + 1; + A <= A + 1; + end end -assign LED = mem_data; +assign LED[3:0] = ram_data[3:0]; +assign LED[7:4] = mem_data[7:4]; endmodule \ No newline at end of file