Added RAM16

This commit is contained in:
2022-03-30 14:23:28 +03:00
parent 9d6eb7a9fa
commit bd2a66037c
97 changed files with 23178 additions and 19024 deletions
+30 -1
View File
@@ -12,13 +12,42 @@ rom0 rom(
.q(mem_data)
);
reg [15:0] A; // Global address bus
wire [7:0] D; // CPU data bus
wire [7:0] ram_data; // Internal 16K RAM data
wire RamWE;
// assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;
assign RamWE = 0;
wire[12:0] vram_address;
wire[7:0] vram_data;
ram16 ram0(
.clock(CLOCK_50),
.address_a({12'b0, A[2:0]}),
.data_a(D),
.q_a(ram_data),
.wren_a(0),
// .address_b({1'b0, vram_address}),
.address_b(A[13:0]),
.data_b(8'b0),
.q_b(vram_data),
.wren_b(0)
);
reg[21:0] counter;
always @(posedge CLOCK_50)
begin
counter <= counter + 1;
if (counter == 0)
begin
address <= address + 1;
A <= A + 1;
end
end
assign LED = mem_data;
assign LED[3:0] = ram_data[3:0];
assign LED[7:4] = mem_data[7:4];
endmodule