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Added RAM16

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This commit is contained in:
Adrian Scripca
2022-03-30 14:23:28 +03:00
parent 9d6eb7a9fa
commit bd2a66037c
97 changed files with 23178 additions and 19024 deletions
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output_files/spectrum.map.rpt
+541 -57
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum
Wed Mar 30 13:12:13 2022
Wed Mar 30 13:47:09 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -15,12 +15,18 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
13. altsyncram Parameter Settings by Entity Instance
14. Elapsed Time Per Partition
15. Analysis & Synthesis Messages
10. Registers Removed During Synthesis
11. Removed Registers Triggering Further Register Optimizations
12. General Register Statistics
13. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
14. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
15. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
16. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
17. altsyncram Parameter Settings by Entity Instance
18. Port Connectivity Checks: "ram16:ram0"
19. Port Connectivity Checks: "rom0:rom"
20. Elapsed Time Per Partition
21. Analysis & Synthesis Messages
@@ -46,18 +52,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ;
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:47:09 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 54 ;
; Total combinational functions ; 52 ;
; Total logic elements ; 50 ;
; Total combinational functions ; 48 ;
; Dedicated logic registers ; 38 ;
; Total registers ; 38 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 131,072 ;
; Total memory bits ; 98,304 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
@@ -405,12 +411,24 @@ File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v
Library :
File Name with User-Entered Path : ram16.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/ram16.v
Library :
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
@@ -488,6 +506,18 @@ Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf
Library :
File Name with User-Entered Path : db/altsyncram_bui2.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_bui2.tdf
Library :
File Name with User-Entered Path : db/decode_jsa.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_jsa.tdf
Library :
+--------------------------------------------------------------------------------+
@@ -497,16 +527,16 @@ Library :
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 54 ;
; Estimated Total logic elements ; 50 ;
; ; ;
; Total combinational functions ; 52 ;
; Total combinational functions ; 48 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 10 ;
; -- <=2 input functions ; 34 ;
; -- 4 input functions ; 7 ;
; -- 3 input functions ; 6 ;
; -- <=2 input functions ; 35 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 20 ;
; -- normal mode ; 16 ;
; -- arithmetic mode ; 32 ;
; ; ;
; Total registers ; 38 ;
@@ -514,12 +544,12 @@ Library :
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
; Total memory bits ; 131072 ;
; Total memory bits ; 98304 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 473 ;
; Average fan-out ; 3.81 ;
; Maximum fan-out ; 50 ;
; Total fan-out ; 401 ;
; Average fan-out ; 3.46 ;
+---------------------------------------------+----------------+
@@ -527,9 +557,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 52 (44)
LC Combinationals : 48 (44)
LC Registers : 38 (36)
Memory Bits : 131072
Memory Bits : 98304
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -538,10 +568,46 @@ Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
Compilation Hierarchy Node : |ram16:ram0|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_bui2:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 32768
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
Library Name : work
Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 8 (0)
LC Combinationals : 4 (0)
LC Registers : 2 (0)
Memory Bits : 131072
Memory Bits : 65536
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -551,9 +617,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 8 (0)
LC Combinationals : 4 (0)
LC Registers : 2 (0)
Memory Bits : 131072
Memory Bits : 65536
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -563,9 +629,9 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
LC Combinationals : 8 (0)
LC Combinationals : 4 (0)
LC Registers : 2 (2)
Memory Bits : 131072
Memory Bits : 65536
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -575,7 +641,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2|
LC Combinationals : 8 (8)
LC Combinationals : 4 (4)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
@@ -593,6 +659,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : True Dual Port
Port A Depth : 16384
Port A Width : 8
Port B Depth : 16384
Port B Width : 8
Size : 131072
MIF : led_patterns.mif
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
@@ -609,6 +685,14 @@ MIF : ./rom/gw03.hex
+--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+
Vendor : Altera
IP Core Name : RAM: 2-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|ram16:ram0
IP Include File : /home/benny/work/fpga/projects/ram16.v
Vendor : Altera
IP Core Name : ROM: 1-PORT
Version : 13.1
@@ -620,6 +704,42 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0] ; Stuck at GND due to stuck port data_in ;
; address[0] ; Merged with A[0] ;
; address[1] ; Merged with A[1] ;
; address[2] ; Merged with A[2] ;
; address[3] ; Merged with A[3] ;
; address[4] ; Merged with A[4] ;
; address[5] ; Merged with A[5] ;
; address[6] ; Merged with A[6] ;
; address[7] ; Merged with A[7] ;
; address[8] ; Merged with A[8] ;
; address[9] ; Merged with A[9] ;
; address[10] ; Merged with A[10] ;
; address[11] ; Merged with A[11] ;
; address[12] ; Merged with A[12] ;
; address[13] ; Merged with A[13] ;
; A[14,15] ; Lost fanout ;
; Total Number of Removed Registers = 18 ; ;
+------------------------------------------------------------------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------+
Register name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|address_reg_a[0]
Reason for Removal : Stuck at GNDdue to stuck port data_in
Registers Removed due to This Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|out_address_reg_a[0]
+--------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
@@ -646,6 +766,17 @@ To : -
+--------------------------------------------------------------------------------+
; Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
@@ -861,24 +992,312 @@ Type : Untyped
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+------------------------------------------+
; Name ; Value ;
+-------------------------------------------+------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : BIDIR_DUAL_PORT
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_B
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_B
Value : 16384
Type : Signed Integer
Parameter Name : INDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : CLOCK0
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Signed Integer
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_bui2
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+--------------------------------------------+
; Name ; Value ;
+-------------------------------------------+--------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; ram16:ram0|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; BIDIR_DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 16384 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; CLOCK0 ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "ram16:ram0" ;
+--------------------------------------------------------------------------------+
Port : address_a
Type : Input
Severity : Warning
Details : Input port expression (15 bits) is wider than the input port (14 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : address_a[13..3]
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_a[7..4]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_a
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_a[-1]
Type : Input
Severity : Info
Details : Stuck at GND
Port : data_b
Type : Input
Severity : Info
Details : Stuck at GND
Port : q_b
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
Port : wren_b
Type : Input
Severity : Warning
Details : Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts.
Port : wren_b[-1]
Type : Input
Severity : Info
Details : Stuck at GND
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Port Connectivity Checks: "rom0:rom" ;
+--------------------------------------------------------------------------------+
Port : q[3..0]
Type : Output
Severity : Info
Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed.
+--------------------------------------------------------------------------------+
+-------------------------------+
@@ -896,16 +1315,20 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 13:12:11 2022
Info: Processing started: Wed Mar 30 13:47:07 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
Info (12023): Found entity 1: ram16
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)
Warning (10036): Verilog HDL or VHDL warning at spectrum.v(19): object "RamWE" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at spectrum.v(43): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(46): truncated value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at spectrum.v(47): truncated value with size 32 to match size of target (16)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
@@ -933,17 +1356,78 @@ Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
Info (12128): Elaborating entity "ram16" for hierarchy "ram16:ram0"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram16:ram0|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram16:ram0|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram16:ram0|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_reg_b" = "CLOCK0"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
Info (12134): Parameter "indata_reg_b" = "CLOCK0"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "numwords_b" = "16384"
Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_aclr_b" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "widthad_b" = "14"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_b" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12134): Parameter "width_byteena_b" = "1"
Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bui2.tdf
Info (12023): Found entity 1: altsyncram_bui2
Info (12128): Elaborating entity "altsyncram_bui2" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2"
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a4"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a5"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a6"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a7"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a11"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a12"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a13"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a14"
Warning (14320): Synthesized away node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|ram_block1a15"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11"
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (286030): Timing-Driven Synthesis is running
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 54 logic cells
Info (21064): Implemented 16 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 392 megabytes
Info: Processing ended: Wed Mar 30 13:12:13 2022
Info (21061): Implemented 50 logic cells
Info (21064): Implemented 12 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 28 warnings
Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 13:47:09 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02