Added RAM16
This commit is contained in:
+782
-5
@@ -1,9 +1,9 @@
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|spectrum
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CLOCK_50 => CLOCK_50.IN1
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LED[0] <= rom0:rom.q
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LED[1] <= rom0:rom.q
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LED[2] <= rom0:rom.q
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LED[3] <= rom0:rom.q
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CLOCK_50 => CLOCK_50.IN2
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LED[0] <= ram16:ram0.q_a
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LED[1] <= ram16:ram0.q_a
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LED[2] <= ram16:ram0.q_a
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LED[3] <= ram16:ram0.q_a
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LED[4] <= rom0:rom.q
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LED[5] <= rom0:rom.q
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LED[6] <= rom0:rom.q
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@@ -380,3 +380,780 @@ sel[0] => result_node[0].IN0
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sel[0] => _.IN0
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|spectrum|ram16:ram0
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address_a[0] => address_a[0].IN1
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address_a[1] => address_a[1].IN1
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address_a[2] => address_a[2].IN1
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address_a[3] => address_a[3].IN1
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address_a[4] => address_a[4].IN1
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address_a[5] => address_a[5].IN1
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address_a[6] => address_a[6].IN1
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address_a[7] => address_a[7].IN1
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address_a[8] => address_a[8].IN1
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address_a[9] => address_a[9].IN1
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address_a[10] => address_a[10].IN1
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address_a[11] => address_a[11].IN1
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address_a[12] => address_a[12].IN1
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address_a[13] => address_a[13].IN1
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address_b[0] => address_b[0].IN1
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address_b[1] => address_b[1].IN1
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address_b[2] => address_b[2].IN1
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address_b[3] => address_b[3].IN1
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address_b[4] => address_b[4].IN1
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address_b[5] => address_b[5].IN1
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address_b[6] => address_b[6].IN1
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address_b[7] => address_b[7].IN1
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address_b[8] => address_b[8].IN1
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address_b[9] => address_b[9].IN1
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address_b[10] => address_b[10].IN1
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address_b[11] => address_b[11].IN1
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address_b[12] => address_b[12].IN1
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address_b[13] => address_b[13].IN1
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clock => clock.IN1
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data_a[0] => data_a[0].IN1
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data_a[1] => data_a[1].IN1
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data_a[2] => data_a[2].IN1
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data_a[3] => data_a[3].IN1
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data_a[4] => data_a[4].IN1
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data_a[5] => data_a[5].IN1
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data_a[6] => data_a[6].IN1
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data_a[7] => data_a[7].IN1
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data_b[0] => data_b[0].IN1
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data_b[1] => data_b[1].IN1
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data_b[2] => data_b[2].IN1
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data_b[3] => data_b[3].IN1
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data_b[4] => data_b[4].IN1
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data_b[5] => data_b[5].IN1
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data_b[6] => data_b[6].IN1
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data_b[7] => data_b[7].IN1
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wren_a => wren_a.IN1
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wren_b => wren_b.IN1
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q_a[0] <= altsyncram:altsyncram_component.q_a
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q_a[1] <= altsyncram:altsyncram_component.q_a
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q_a[2] <= altsyncram:altsyncram_component.q_a
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q_a[3] <= altsyncram:altsyncram_component.q_a
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q_a[4] <= altsyncram:altsyncram_component.q_a
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q_a[5] <= altsyncram:altsyncram_component.q_a
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q_a[6] <= altsyncram:altsyncram_component.q_a
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q_a[7] <= altsyncram:altsyncram_component.q_a
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q_b[0] <= altsyncram:altsyncram_component.q_b
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q_b[1] <= altsyncram:altsyncram_component.q_b
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q_b[2] <= altsyncram:altsyncram_component.q_b
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q_b[3] <= altsyncram:altsyncram_component.q_b
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q_b[4] <= altsyncram:altsyncram_component.q_b
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q_b[5] <= altsyncram:altsyncram_component.q_b
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q_b[6] <= altsyncram:altsyncram_component.q_b
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q_b[7] <= altsyncram:altsyncram_component.q_b
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|spectrum|ram16:ram0|altsyncram:altsyncram_component
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wren_a => altsyncram_bui2:auto_generated.wren_a
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rden_a => ~NO_FANOUT~
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wren_b => altsyncram_bui2:auto_generated.wren_b
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rden_b => ~NO_FANOUT~
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data_a[0] => altsyncram_bui2:auto_generated.data_a[0]
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data_a[1] => altsyncram_bui2:auto_generated.data_a[1]
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data_a[2] => altsyncram_bui2:auto_generated.data_a[2]
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data_a[3] => altsyncram_bui2:auto_generated.data_a[3]
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data_a[4] => altsyncram_bui2:auto_generated.data_a[4]
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data_a[5] => altsyncram_bui2:auto_generated.data_a[5]
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data_a[6] => altsyncram_bui2:auto_generated.data_a[6]
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data_a[7] => altsyncram_bui2:auto_generated.data_a[7]
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data_b[0] => altsyncram_bui2:auto_generated.data_b[0]
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data_b[1] => altsyncram_bui2:auto_generated.data_b[1]
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data_b[2] => altsyncram_bui2:auto_generated.data_b[2]
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data_b[3] => altsyncram_bui2:auto_generated.data_b[3]
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data_b[4] => altsyncram_bui2:auto_generated.data_b[4]
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data_b[5] => altsyncram_bui2:auto_generated.data_b[5]
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data_b[6] => altsyncram_bui2:auto_generated.data_b[6]
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data_b[7] => altsyncram_bui2:auto_generated.data_b[7]
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address_a[0] => altsyncram_bui2:auto_generated.address_a[0]
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address_a[1] => altsyncram_bui2:auto_generated.address_a[1]
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address_a[2] => altsyncram_bui2:auto_generated.address_a[2]
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address_a[3] => altsyncram_bui2:auto_generated.address_a[3]
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address_a[4] => altsyncram_bui2:auto_generated.address_a[4]
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address_a[5] => altsyncram_bui2:auto_generated.address_a[5]
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address_a[6] => altsyncram_bui2:auto_generated.address_a[6]
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address_a[7] => altsyncram_bui2:auto_generated.address_a[7]
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address_a[8] => altsyncram_bui2:auto_generated.address_a[8]
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address_a[9] => altsyncram_bui2:auto_generated.address_a[9]
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address_a[10] => altsyncram_bui2:auto_generated.address_a[10]
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address_a[11] => altsyncram_bui2:auto_generated.address_a[11]
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address_a[12] => altsyncram_bui2:auto_generated.address_a[12]
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address_a[13] => altsyncram_bui2:auto_generated.address_a[13]
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address_b[0] => altsyncram_bui2:auto_generated.address_b[0]
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address_b[1] => altsyncram_bui2:auto_generated.address_b[1]
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address_b[2] => altsyncram_bui2:auto_generated.address_b[2]
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address_b[3] => altsyncram_bui2:auto_generated.address_b[3]
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address_b[4] => altsyncram_bui2:auto_generated.address_b[4]
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address_b[5] => altsyncram_bui2:auto_generated.address_b[5]
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address_b[6] => altsyncram_bui2:auto_generated.address_b[6]
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address_b[7] => altsyncram_bui2:auto_generated.address_b[7]
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address_b[8] => altsyncram_bui2:auto_generated.address_b[8]
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address_b[9] => altsyncram_bui2:auto_generated.address_b[9]
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address_b[10] => altsyncram_bui2:auto_generated.address_b[10]
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address_b[11] => altsyncram_bui2:auto_generated.address_b[11]
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address_b[12] => altsyncram_bui2:auto_generated.address_b[12]
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address_b[13] => altsyncram_bui2:auto_generated.address_b[13]
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addressstall_a => ~NO_FANOUT~
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addressstall_b => ~NO_FANOUT~
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clock0 => altsyncram_bui2:auto_generated.clock0
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clock1 => ~NO_FANOUT~
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clocken0 => ~NO_FANOUT~
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clocken1 => ~NO_FANOUT~
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clocken2 => ~NO_FANOUT~
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clocken3 => ~NO_FANOUT~
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aclr0 => ~NO_FANOUT~
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aclr1 => ~NO_FANOUT~
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byteena_a[0] => ~NO_FANOUT~
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byteena_b[0] => ~NO_FANOUT~
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q_a[0] <= altsyncram_bui2:auto_generated.q_a[0]
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q_a[1] <= altsyncram_bui2:auto_generated.q_a[1]
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q_a[2] <= altsyncram_bui2:auto_generated.q_a[2]
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q_a[3] <= altsyncram_bui2:auto_generated.q_a[3]
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q_a[4] <= altsyncram_bui2:auto_generated.q_a[4]
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q_a[5] <= altsyncram_bui2:auto_generated.q_a[5]
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q_a[6] <= altsyncram_bui2:auto_generated.q_a[6]
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q_a[7] <= altsyncram_bui2:auto_generated.q_a[7]
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q_b[0] <= altsyncram_bui2:auto_generated.q_b[0]
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q_b[1] <= altsyncram_bui2:auto_generated.q_b[1]
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q_b[2] <= altsyncram_bui2:auto_generated.q_b[2]
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q_b[3] <= altsyncram_bui2:auto_generated.q_b[3]
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q_b[4] <= altsyncram_bui2:auto_generated.q_b[4]
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q_b[5] <= altsyncram_bui2:auto_generated.q_b[5]
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q_b[6] <= altsyncram_bui2:auto_generated.q_b[6]
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q_b[7] <= altsyncram_bui2:auto_generated.q_b[7]
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eccstatus[0] <= <GND>
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eccstatus[1] <= <GND>
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eccstatus[2] <= <GND>
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|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated
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address_a[0] => ram_block1a0.PORTAADDR
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address_a[0] => ram_block1a1.PORTAADDR
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address_a[0] => ram_block1a2.PORTAADDR
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address_a[0] => ram_block1a3.PORTAADDR
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address_a[0] => ram_block1a4.PORTAADDR
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address_a[0] => ram_block1a5.PORTAADDR
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address_a[0] => ram_block1a6.PORTAADDR
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address_a[0] => ram_block1a7.PORTAADDR
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address_a[0] => ram_block1a8.PORTAADDR
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address_a[0] => ram_block1a9.PORTAADDR
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address_a[0] => ram_block1a10.PORTAADDR
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address_a[0] => ram_block1a11.PORTAADDR
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address_a[0] => ram_block1a12.PORTAADDR
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address_a[0] => ram_block1a13.PORTAADDR
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address_a[0] => ram_block1a14.PORTAADDR
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address_a[0] => ram_block1a15.PORTAADDR
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address_a[1] => ram_block1a0.PORTAADDR1
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address_a[1] => ram_block1a1.PORTAADDR1
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address_a[1] => ram_block1a2.PORTAADDR1
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address_a[1] => ram_block1a3.PORTAADDR1
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address_a[1] => ram_block1a4.PORTAADDR1
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address_a[1] => ram_block1a5.PORTAADDR1
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address_a[1] => ram_block1a6.PORTAADDR1
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address_a[1] => ram_block1a7.PORTAADDR1
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address_a[1] => ram_block1a8.PORTAADDR1
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address_a[1] => ram_block1a9.PORTAADDR1
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address_a[1] => ram_block1a10.PORTAADDR1
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address_a[1] => ram_block1a11.PORTAADDR1
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address_a[1] => ram_block1a12.PORTAADDR1
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address_a[1] => ram_block1a13.PORTAADDR1
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address_a[1] => ram_block1a14.PORTAADDR1
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address_a[1] => ram_block1a15.PORTAADDR1
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address_a[2] => ram_block1a0.PORTAADDR2
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address_a[2] => ram_block1a1.PORTAADDR2
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address_a[2] => ram_block1a2.PORTAADDR2
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address_a[2] => ram_block1a3.PORTAADDR2
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address_a[2] => ram_block1a4.PORTAADDR2
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address_a[2] => ram_block1a5.PORTAADDR2
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address_a[2] => ram_block1a6.PORTAADDR2
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address_a[2] => ram_block1a7.PORTAADDR2
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address_a[2] => ram_block1a8.PORTAADDR2
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address_a[2] => ram_block1a9.PORTAADDR2
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address_a[2] => ram_block1a10.PORTAADDR2
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address_a[2] => ram_block1a11.PORTAADDR2
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address_a[2] => ram_block1a12.PORTAADDR2
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address_a[2] => ram_block1a13.PORTAADDR2
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address_a[2] => ram_block1a14.PORTAADDR2
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address_a[2] => ram_block1a15.PORTAADDR2
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address_a[3] => ram_block1a0.PORTAADDR3
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address_a[3] => ram_block1a1.PORTAADDR3
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address_a[3] => ram_block1a2.PORTAADDR3
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address_a[3] => ram_block1a3.PORTAADDR3
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address_a[3] => ram_block1a4.PORTAADDR3
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address_a[3] => ram_block1a5.PORTAADDR3
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address_a[3] => ram_block1a6.PORTAADDR3
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address_a[3] => ram_block1a7.PORTAADDR3
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address_a[3] => ram_block1a8.PORTAADDR3
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address_a[3] => ram_block1a9.PORTAADDR3
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address_a[3] => ram_block1a10.PORTAADDR3
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address_a[3] => ram_block1a11.PORTAADDR3
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address_a[3] => ram_block1a12.PORTAADDR3
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address_a[3] => ram_block1a13.PORTAADDR3
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address_a[3] => ram_block1a14.PORTAADDR3
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address_a[3] => ram_block1a15.PORTAADDR3
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address_a[4] => ram_block1a0.PORTAADDR4
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address_a[4] => ram_block1a1.PORTAADDR4
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address_a[4] => ram_block1a2.PORTAADDR4
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address_a[4] => ram_block1a3.PORTAADDR4
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address_a[4] => ram_block1a4.PORTAADDR4
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address_a[4] => ram_block1a5.PORTAADDR4
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address_a[4] => ram_block1a6.PORTAADDR4
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address_a[4] => ram_block1a7.PORTAADDR4
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address_a[4] => ram_block1a8.PORTAADDR4
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address_a[4] => ram_block1a9.PORTAADDR4
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address_a[4] => ram_block1a10.PORTAADDR4
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address_a[4] => ram_block1a11.PORTAADDR4
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address_a[4] => ram_block1a12.PORTAADDR4
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address_a[4] => ram_block1a13.PORTAADDR4
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address_a[4] => ram_block1a14.PORTAADDR4
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address_a[4] => ram_block1a15.PORTAADDR4
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address_a[5] => ram_block1a0.PORTAADDR5
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address_a[5] => ram_block1a1.PORTAADDR5
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address_a[5] => ram_block1a2.PORTAADDR5
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address_a[5] => ram_block1a3.PORTAADDR5
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address_a[5] => ram_block1a4.PORTAADDR5
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address_a[5] => ram_block1a5.PORTAADDR5
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address_a[5] => ram_block1a6.PORTAADDR5
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address_a[5] => ram_block1a7.PORTAADDR5
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address_a[5] => ram_block1a8.PORTAADDR5
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address_a[5] => ram_block1a9.PORTAADDR5
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address_a[5] => ram_block1a10.PORTAADDR5
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address_a[5] => ram_block1a11.PORTAADDR5
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address_a[5] => ram_block1a12.PORTAADDR5
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address_a[5] => ram_block1a13.PORTAADDR5
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address_a[5] => ram_block1a14.PORTAADDR5
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address_a[5] => ram_block1a15.PORTAADDR5
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address_a[6] => ram_block1a0.PORTAADDR6
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address_a[6] => ram_block1a1.PORTAADDR6
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address_a[6] => ram_block1a2.PORTAADDR6
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address_a[6] => ram_block1a3.PORTAADDR6
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address_a[6] => ram_block1a4.PORTAADDR6
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address_a[6] => ram_block1a5.PORTAADDR6
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address_a[6] => ram_block1a6.PORTAADDR6
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address_a[6] => ram_block1a7.PORTAADDR6
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address_a[6] => ram_block1a8.PORTAADDR6
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address_a[6] => ram_block1a9.PORTAADDR6
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address_a[6] => ram_block1a10.PORTAADDR6
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address_a[6] => ram_block1a11.PORTAADDR6
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address_a[6] => ram_block1a12.PORTAADDR6
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address_a[6] => ram_block1a13.PORTAADDR6
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address_a[6] => ram_block1a14.PORTAADDR6
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address_a[6] => ram_block1a15.PORTAADDR6
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address_a[7] => ram_block1a0.PORTAADDR7
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address_a[7] => ram_block1a1.PORTAADDR7
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address_a[7] => ram_block1a2.PORTAADDR7
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address_a[7] => ram_block1a3.PORTAADDR7
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address_a[7] => ram_block1a4.PORTAADDR7
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address_a[7] => ram_block1a5.PORTAADDR7
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address_a[7] => ram_block1a6.PORTAADDR7
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address_a[7] => ram_block1a7.PORTAADDR7
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address_a[7] => ram_block1a8.PORTAADDR7
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address_a[7] => ram_block1a9.PORTAADDR7
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address_a[7] => ram_block1a10.PORTAADDR7
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address_a[7] => ram_block1a11.PORTAADDR7
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address_a[7] => ram_block1a12.PORTAADDR7
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address_a[7] => ram_block1a13.PORTAADDR7
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address_a[7] => ram_block1a14.PORTAADDR7
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address_a[7] => ram_block1a15.PORTAADDR7
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address_a[8] => ram_block1a0.PORTAADDR8
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address_a[8] => ram_block1a1.PORTAADDR8
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address_a[8] => ram_block1a2.PORTAADDR8
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address_a[8] => ram_block1a3.PORTAADDR8
|
||||
address_a[8] => ram_block1a4.PORTAADDR8
|
||||
address_a[8] => ram_block1a5.PORTAADDR8
|
||||
address_a[8] => ram_block1a6.PORTAADDR8
|
||||
address_a[8] => ram_block1a7.PORTAADDR8
|
||||
address_a[8] => ram_block1a8.PORTAADDR8
|
||||
address_a[8] => ram_block1a9.PORTAADDR8
|
||||
address_a[8] => ram_block1a10.PORTAADDR8
|
||||
address_a[8] => ram_block1a11.PORTAADDR8
|
||||
address_a[8] => ram_block1a12.PORTAADDR8
|
||||
address_a[8] => ram_block1a13.PORTAADDR8
|
||||
address_a[8] => ram_block1a14.PORTAADDR8
|
||||
address_a[8] => ram_block1a15.PORTAADDR8
|
||||
address_a[9] => ram_block1a0.PORTAADDR9
|
||||
address_a[9] => ram_block1a1.PORTAADDR9
|
||||
address_a[9] => ram_block1a2.PORTAADDR9
|
||||
address_a[9] => ram_block1a3.PORTAADDR9
|
||||
address_a[9] => ram_block1a4.PORTAADDR9
|
||||
address_a[9] => ram_block1a5.PORTAADDR9
|
||||
address_a[9] => ram_block1a6.PORTAADDR9
|
||||
address_a[9] => ram_block1a7.PORTAADDR9
|
||||
address_a[9] => ram_block1a8.PORTAADDR9
|
||||
address_a[9] => ram_block1a9.PORTAADDR9
|
||||
address_a[9] => ram_block1a10.PORTAADDR9
|
||||
address_a[9] => ram_block1a11.PORTAADDR9
|
||||
address_a[9] => ram_block1a12.PORTAADDR9
|
||||
address_a[9] => ram_block1a13.PORTAADDR9
|
||||
address_a[9] => ram_block1a14.PORTAADDR9
|
||||
address_a[9] => ram_block1a15.PORTAADDR9
|
||||
address_a[10] => ram_block1a0.PORTAADDR10
|
||||
address_a[10] => ram_block1a1.PORTAADDR10
|
||||
address_a[10] => ram_block1a2.PORTAADDR10
|
||||
address_a[10] => ram_block1a3.PORTAADDR10
|
||||
address_a[10] => ram_block1a4.PORTAADDR10
|
||||
address_a[10] => ram_block1a5.PORTAADDR10
|
||||
address_a[10] => ram_block1a6.PORTAADDR10
|
||||
address_a[10] => ram_block1a7.PORTAADDR10
|
||||
address_a[10] => ram_block1a8.PORTAADDR10
|
||||
address_a[10] => ram_block1a9.PORTAADDR10
|
||||
address_a[10] => ram_block1a10.PORTAADDR10
|
||||
address_a[10] => ram_block1a11.PORTAADDR10
|
||||
address_a[10] => ram_block1a12.PORTAADDR10
|
||||
address_a[10] => ram_block1a13.PORTAADDR10
|
||||
address_a[10] => ram_block1a14.PORTAADDR10
|
||||
address_a[10] => ram_block1a15.PORTAADDR10
|
||||
address_a[11] => ram_block1a0.PORTAADDR11
|
||||
address_a[11] => ram_block1a1.PORTAADDR11
|
||||
address_a[11] => ram_block1a2.PORTAADDR11
|
||||
address_a[11] => ram_block1a3.PORTAADDR11
|
||||
address_a[11] => ram_block1a4.PORTAADDR11
|
||||
address_a[11] => ram_block1a5.PORTAADDR11
|
||||
address_a[11] => ram_block1a6.PORTAADDR11
|
||||
address_a[11] => ram_block1a7.PORTAADDR11
|
||||
address_a[11] => ram_block1a8.PORTAADDR11
|
||||
address_a[11] => ram_block1a9.PORTAADDR11
|
||||
address_a[11] => ram_block1a10.PORTAADDR11
|
||||
address_a[11] => ram_block1a11.PORTAADDR11
|
||||
address_a[11] => ram_block1a12.PORTAADDR11
|
||||
address_a[11] => ram_block1a13.PORTAADDR11
|
||||
address_a[11] => ram_block1a14.PORTAADDR11
|
||||
address_a[11] => ram_block1a15.PORTAADDR11
|
||||
address_a[12] => ram_block1a0.PORTAADDR12
|
||||
address_a[12] => ram_block1a1.PORTAADDR12
|
||||
address_a[12] => ram_block1a2.PORTAADDR12
|
||||
address_a[12] => ram_block1a3.PORTAADDR12
|
||||
address_a[12] => ram_block1a4.PORTAADDR12
|
||||
address_a[12] => ram_block1a5.PORTAADDR12
|
||||
address_a[12] => ram_block1a6.PORTAADDR12
|
||||
address_a[12] => ram_block1a7.PORTAADDR12
|
||||
address_a[12] => ram_block1a8.PORTAADDR12
|
||||
address_a[12] => ram_block1a9.PORTAADDR12
|
||||
address_a[12] => ram_block1a10.PORTAADDR12
|
||||
address_a[12] => ram_block1a11.PORTAADDR12
|
||||
address_a[12] => ram_block1a12.PORTAADDR12
|
||||
address_a[12] => ram_block1a13.PORTAADDR12
|
||||
address_a[12] => ram_block1a14.PORTAADDR12
|
||||
address_a[12] => ram_block1a15.PORTAADDR12
|
||||
address_a[13] => address_reg_a[0].DATAIN
|
||||
address_a[13] => decode_jsa:decode2.data[0]
|
||||
address_a[13] => decode_c8a:rden_decode_a.data[0]
|
||||
address_b[0] => ram_block1a0.PORTBADDR
|
||||
address_b[0] => ram_block1a1.PORTBADDR
|
||||
address_b[0] => ram_block1a2.PORTBADDR
|
||||
address_b[0] => ram_block1a3.PORTBADDR
|
||||
address_b[0] => ram_block1a4.PORTBADDR
|
||||
address_b[0] => ram_block1a5.PORTBADDR
|
||||
address_b[0] => ram_block1a6.PORTBADDR
|
||||
address_b[0] => ram_block1a7.PORTBADDR
|
||||
address_b[0] => ram_block1a8.PORTBADDR
|
||||
address_b[0] => ram_block1a9.PORTBADDR
|
||||
address_b[0] => ram_block1a10.PORTBADDR
|
||||
address_b[0] => ram_block1a11.PORTBADDR
|
||||
address_b[0] => ram_block1a12.PORTBADDR
|
||||
address_b[0] => ram_block1a13.PORTBADDR
|
||||
address_b[0] => ram_block1a14.PORTBADDR
|
||||
address_b[0] => ram_block1a15.PORTBADDR
|
||||
address_b[1] => ram_block1a0.PORTBADDR1
|
||||
address_b[1] => ram_block1a1.PORTBADDR1
|
||||
address_b[1] => ram_block1a2.PORTBADDR1
|
||||
address_b[1] => ram_block1a3.PORTBADDR1
|
||||
address_b[1] => ram_block1a4.PORTBADDR1
|
||||
address_b[1] => ram_block1a5.PORTBADDR1
|
||||
address_b[1] => ram_block1a6.PORTBADDR1
|
||||
address_b[1] => ram_block1a7.PORTBADDR1
|
||||
address_b[1] => ram_block1a8.PORTBADDR1
|
||||
address_b[1] => ram_block1a9.PORTBADDR1
|
||||
address_b[1] => ram_block1a10.PORTBADDR1
|
||||
address_b[1] => ram_block1a11.PORTBADDR1
|
||||
address_b[1] => ram_block1a12.PORTBADDR1
|
||||
address_b[1] => ram_block1a13.PORTBADDR1
|
||||
address_b[1] => ram_block1a14.PORTBADDR1
|
||||
address_b[1] => ram_block1a15.PORTBADDR1
|
||||
address_b[2] => ram_block1a0.PORTBADDR2
|
||||
address_b[2] => ram_block1a1.PORTBADDR2
|
||||
address_b[2] => ram_block1a2.PORTBADDR2
|
||||
address_b[2] => ram_block1a3.PORTBADDR2
|
||||
address_b[2] => ram_block1a4.PORTBADDR2
|
||||
address_b[2] => ram_block1a5.PORTBADDR2
|
||||
address_b[2] => ram_block1a6.PORTBADDR2
|
||||
address_b[2] => ram_block1a7.PORTBADDR2
|
||||
address_b[2] => ram_block1a8.PORTBADDR2
|
||||
address_b[2] => ram_block1a9.PORTBADDR2
|
||||
address_b[2] => ram_block1a10.PORTBADDR2
|
||||
address_b[2] => ram_block1a11.PORTBADDR2
|
||||
address_b[2] => ram_block1a12.PORTBADDR2
|
||||
address_b[2] => ram_block1a13.PORTBADDR2
|
||||
address_b[2] => ram_block1a14.PORTBADDR2
|
||||
address_b[2] => ram_block1a15.PORTBADDR2
|
||||
address_b[3] => ram_block1a0.PORTBADDR3
|
||||
address_b[3] => ram_block1a1.PORTBADDR3
|
||||
address_b[3] => ram_block1a2.PORTBADDR3
|
||||
address_b[3] => ram_block1a3.PORTBADDR3
|
||||
address_b[3] => ram_block1a4.PORTBADDR3
|
||||
address_b[3] => ram_block1a5.PORTBADDR3
|
||||
address_b[3] => ram_block1a6.PORTBADDR3
|
||||
address_b[3] => ram_block1a7.PORTBADDR3
|
||||
address_b[3] => ram_block1a8.PORTBADDR3
|
||||
address_b[3] => ram_block1a9.PORTBADDR3
|
||||
address_b[3] => ram_block1a10.PORTBADDR3
|
||||
address_b[3] => ram_block1a11.PORTBADDR3
|
||||
address_b[3] => ram_block1a12.PORTBADDR3
|
||||
address_b[3] => ram_block1a13.PORTBADDR3
|
||||
address_b[3] => ram_block1a14.PORTBADDR3
|
||||
address_b[3] => ram_block1a15.PORTBADDR3
|
||||
address_b[4] => ram_block1a0.PORTBADDR4
|
||||
address_b[4] => ram_block1a1.PORTBADDR4
|
||||
address_b[4] => ram_block1a2.PORTBADDR4
|
||||
address_b[4] => ram_block1a3.PORTBADDR4
|
||||
address_b[4] => ram_block1a4.PORTBADDR4
|
||||
address_b[4] => ram_block1a5.PORTBADDR4
|
||||
address_b[4] => ram_block1a6.PORTBADDR4
|
||||
address_b[4] => ram_block1a7.PORTBADDR4
|
||||
address_b[4] => ram_block1a8.PORTBADDR4
|
||||
address_b[4] => ram_block1a9.PORTBADDR4
|
||||
address_b[4] => ram_block1a10.PORTBADDR4
|
||||
address_b[4] => ram_block1a11.PORTBADDR4
|
||||
address_b[4] => ram_block1a12.PORTBADDR4
|
||||
address_b[4] => ram_block1a13.PORTBADDR4
|
||||
address_b[4] => ram_block1a14.PORTBADDR4
|
||||
address_b[4] => ram_block1a15.PORTBADDR4
|
||||
address_b[5] => ram_block1a0.PORTBADDR5
|
||||
address_b[5] => ram_block1a1.PORTBADDR5
|
||||
address_b[5] => ram_block1a2.PORTBADDR5
|
||||
address_b[5] => ram_block1a3.PORTBADDR5
|
||||
address_b[5] => ram_block1a4.PORTBADDR5
|
||||
address_b[5] => ram_block1a5.PORTBADDR5
|
||||
address_b[5] => ram_block1a6.PORTBADDR5
|
||||
address_b[5] => ram_block1a7.PORTBADDR5
|
||||
address_b[5] => ram_block1a8.PORTBADDR5
|
||||
address_b[5] => ram_block1a9.PORTBADDR5
|
||||
address_b[5] => ram_block1a10.PORTBADDR5
|
||||
address_b[5] => ram_block1a11.PORTBADDR5
|
||||
address_b[5] => ram_block1a12.PORTBADDR5
|
||||
address_b[5] => ram_block1a13.PORTBADDR5
|
||||
address_b[5] => ram_block1a14.PORTBADDR5
|
||||
address_b[5] => ram_block1a15.PORTBADDR5
|
||||
address_b[6] => ram_block1a0.PORTBADDR6
|
||||
address_b[6] => ram_block1a1.PORTBADDR6
|
||||
address_b[6] => ram_block1a2.PORTBADDR6
|
||||
address_b[6] => ram_block1a3.PORTBADDR6
|
||||
address_b[6] => ram_block1a4.PORTBADDR6
|
||||
address_b[6] => ram_block1a5.PORTBADDR6
|
||||
address_b[6] => ram_block1a6.PORTBADDR6
|
||||
address_b[6] => ram_block1a7.PORTBADDR6
|
||||
address_b[6] => ram_block1a8.PORTBADDR6
|
||||
address_b[6] => ram_block1a9.PORTBADDR6
|
||||
address_b[6] => ram_block1a10.PORTBADDR6
|
||||
address_b[6] => ram_block1a11.PORTBADDR6
|
||||
address_b[6] => ram_block1a12.PORTBADDR6
|
||||
address_b[6] => ram_block1a13.PORTBADDR6
|
||||
address_b[6] => ram_block1a14.PORTBADDR6
|
||||
address_b[6] => ram_block1a15.PORTBADDR6
|
||||
address_b[7] => ram_block1a0.PORTBADDR7
|
||||
address_b[7] => ram_block1a1.PORTBADDR7
|
||||
address_b[7] => ram_block1a2.PORTBADDR7
|
||||
address_b[7] => ram_block1a3.PORTBADDR7
|
||||
address_b[7] => ram_block1a4.PORTBADDR7
|
||||
address_b[7] => ram_block1a5.PORTBADDR7
|
||||
address_b[7] => ram_block1a6.PORTBADDR7
|
||||
address_b[7] => ram_block1a7.PORTBADDR7
|
||||
address_b[7] => ram_block1a8.PORTBADDR7
|
||||
address_b[7] => ram_block1a9.PORTBADDR7
|
||||
address_b[7] => ram_block1a10.PORTBADDR7
|
||||
address_b[7] => ram_block1a11.PORTBADDR7
|
||||
address_b[7] => ram_block1a12.PORTBADDR7
|
||||
address_b[7] => ram_block1a13.PORTBADDR7
|
||||
address_b[7] => ram_block1a14.PORTBADDR7
|
||||
address_b[7] => ram_block1a15.PORTBADDR7
|
||||
address_b[8] => ram_block1a0.PORTBADDR8
|
||||
address_b[8] => ram_block1a1.PORTBADDR8
|
||||
address_b[8] => ram_block1a2.PORTBADDR8
|
||||
address_b[8] => ram_block1a3.PORTBADDR8
|
||||
address_b[8] => ram_block1a4.PORTBADDR8
|
||||
address_b[8] => ram_block1a5.PORTBADDR8
|
||||
address_b[8] => ram_block1a6.PORTBADDR8
|
||||
address_b[8] => ram_block1a7.PORTBADDR8
|
||||
address_b[8] => ram_block1a8.PORTBADDR8
|
||||
address_b[8] => ram_block1a9.PORTBADDR8
|
||||
address_b[8] => ram_block1a10.PORTBADDR8
|
||||
address_b[8] => ram_block1a11.PORTBADDR8
|
||||
address_b[8] => ram_block1a12.PORTBADDR8
|
||||
address_b[8] => ram_block1a13.PORTBADDR8
|
||||
address_b[8] => ram_block1a14.PORTBADDR8
|
||||
address_b[8] => ram_block1a15.PORTBADDR8
|
||||
address_b[9] => ram_block1a0.PORTBADDR9
|
||||
address_b[9] => ram_block1a1.PORTBADDR9
|
||||
address_b[9] => ram_block1a2.PORTBADDR9
|
||||
address_b[9] => ram_block1a3.PORTBADDR9
|
||||
address_b[9] => ram_block1a4.PORTBADDR9
|
||||
address_b[9] => ram_block1a5.PORTBADDR9
|
||||
address_b[9] => ram_block1a6.PORTBADDR9
|
||||
address_b[9] => ram_block1a7.PORTBADDR9
|
||||
address_b[9] => ram_block1a8.PORTBADDR9
|
||||
address_b[9] => ram_block1a9.PORTBADDR9
|
||||
address_b[9] => ram_block1a10.PORTBADDR9
|
||||
address_b[9] => ram_block1a11.PORTBADDR9
|
||||
address_b[9] => ram_block1a12.PORTBADDR9
|
||||
address_b[9] => ram_block1a13.PORTBADDR9
|
||||
address_b[9] => ram_block1a14.PORTBADDR9
|
||||
address_b[9] => ram_block1a15.PORTBADDR9
|
||||
address_b[10] => ram_block1a0.PORTBADDR10
|
||||
address_b[10] => ram_block1a1.PORTBADDR10
|
||||
address_b[10] => ram_block1a2.PORTBADDR10
|
||||
address_b[10] => ram_block1a3.PORTBADDR10
|
||||
address_b[10] => ram_block1a4.PORTBADDR10
|
||||
address_b[10] => ram_block1a5.PORTBADDR10
|
||||
address_b[10] => ram_block1a6.PORTBADDR10
|
||||
address_b[10] => ram_block1a7.PORTBADDR10
|
||||
address_b[10] => ram_block1a8.PORTBADDR10
|
||||
address_b[10] => ram_block1a9.PORTBADDR10
|
||||
address_b[10] => ram_block1a10.PORTBADDR10
|
||||
address_b[10] => ram_block1a11.PORTBADDR10
|
||||
address_b[10] => ram_block1a12.PORTBADDR10
|
||||
address_b[10] => ram_block1a13.PORTBADDR10
|
||||
address_b[10] => ram_block1a14.PORTBADDR10
|
||||
address_b[10] => ram_block1a15.PORTBADDR10
|
||||
address_b[11] => ram_block1a0.PORTBADDR11
|
||||
address_b[11] => ram_block1a1.PORTBADDR11
|
||||
address_b[11] => ram_block1a2.PORTBADDR11
|
||||
address_b[11] => ram_block1a3.PORTBADDR11
|
||||
address_b[11] => ram_block1a4.PORTBADDR11
|
||||
address_b[11] => ram_block1a5.PORTBADDR11
|
||||
address_b[11] => ram_block1a6.PORTBADDR11
|
||||
address_b[11] => ram_block1a7.PORTBADDR11
|
||||
address_b[11] => ram_block1a8.PORTBADDR11
|
||||
address_b[11] => ram_block1a9.PORTBADDR11
|
||||
address_b[11] => ram_block1a10.PORTBADDR11
|
||||
address_b[11] => ram_block1a11.PORTBADDR11
|
||||
address_b[11] => ram_block1a12.PORTBADDR11
|
||||
address_b[11] => ram_block1a13.PORTBADDR11
|
||||
address_b[11] => ram_block1a14.PORTBADDR11
|
||||
address_b[11] => ram_block1a15.PORTBADDR11
|
||||
address_b[12] => ram_block1a0.PORTBADDR12
|
||||
address_b[12] => ram_block1a1.PORTBADDR12
|
||||
address_b[12] => ram_block1a2.PORTBADDR12
|
||||
address_b[12] => ram_block1a3.PORTBADDR12
|
||||
address_b[12] => ram_block1a4.PORTBADDR12
|
||||
address_b[12] => ram_block1a5.PORTBADDR12
|
||||
address_b[12] => ram_block1a6.PORTBADDR12
|
||||
address_b[12] => ram_block1a7.PORTBADDR12
|
||||
address_b[12] => ram_block1a8.PORTBADDR12
|
||||
address_b[12] => ram_block1a9.PORTBADDR12
|
||||
address_b[12] => ram_block1a10.PORTBADDR12
|
||||
address_b[12] => ram_block1a11.PORTBADDR12
|
||||
address_b[12] => ram_block1a12.PORTBADDR12
|
||||
address_b[12] => ram_block1a13.PORTBADDR12
|
||||
address_b[12] => ram_block1a14.PORTBADDR12
|
||||
address_b[12] => ram_block1a15.PORTBADDR12
|
||||
address_b[13] => address_reg_b[0].DATAIN
|
||||
address_b[13] => decode_jsa:decode3.data[0]
|
||||
address_b[13] => decode_c8a:rden_decode_b.data[0]
|
||||
clock0 => ram_block1a0.CLK0
|
||||
clock0 => ram_block1a0.CLK1
|
||||
clock0 => ram_block1a1.CLK0
|
||||
clock0 => ram_block1a1.CLK1
|
||||
clock0 => ram_block1a2.CLK0
|
||||
clock0 => ram_block1a2.CLK1
|
||||
clock0 => ram_block1a3.CLK0
|
||||
clock0 => ram_block1a3.CLK1
|
||||
clock0 => ram_block1a4.CLK0
|
||||
clock0 => ram_block1a4.CLK1
|
||||
clock0 => ram_block1a5.CLK0
|
||||
clock0 => ram_block1a5.CLK1
|
||||
clock0 => ram_block1a6.CLK0
|
||||
clock0 => ram_block1a6.CLK1
|
||||
clock0 => ram_block1a7.CLK0
|
||||
clock0 => ram_block1a7.CLK1
|
||||
clock0 => ram_block1a8.CLK0
|
||||
clock0 => ram_block1a8.CLK1
|
||||
clock0 => ram_block1a9.CLK0
|
||||
clock0 => ram_block1a9.CLK1
|
||||
clock0 => ram_block1a10.CLK0
|
||||
clock0 => ram_block1a10.CLK1
|
||||
clock0 => ram_block1a11.CLK0
|
||||
clock0 => ram_block1a11.CLK1
|
||||
clock0 => ram_block1a12.CLK0
|
||||
clock0 => ram_block1a12.CLK1
|
||||
clock0 => ram_block1a13.CLK0
|
||||
clock0 => ram_block1a13.CLK1
|
||||
clock0 => ram_block1a14.CLK0
|
||||
clock0 => ram_block1a14.CLK1
|
||||
clock0 => ram_block1a15.CLK0
|
||||
clock0 => ram_block1a15.CLK1
|
||||
clock0 => address_reg_a[0].CLK
|
||||
clock0 => address_reg_b[0].CLK
|
||||
clock0 => out_address_reg_a[0].CLK
|
||||
clock0 => out_address_reg_b[0].CLK
|
||||
data_a[0] => ram_block1a0.PORTADATAIN
|
||||
data_a[0] => ram_block1a8.PORTADATAIN
|
||||
data_a[1] => ram_block1a1.PORTADATAIN
|
||||
data_a[1] => ram_block1a9.PORTADATAIN
|
||||
data_a[2] => ram_block1a2.PORTADATAIN
|
||||
data_a[2] => ram_block1a10.PORTADATAIN
|
||||
data_a[3] => ram_block1a3.PORTADATAIN
|
||||
data_a[3] => ram_block1a11.PORTADATAIN
|
||||
data_a[4] => ram_block1a4.PORTADATAIN
|
||||
data_a[4] => ram_block1a12.PORTADATAIN
|
||||
data_a[5] => ram_block1a5.PORTADATAIN
|
||||
data_a[5] => ram_block1a13.PORTADATAIN
|
||||
data_a[6] => ram_block1a6.PORTADATAIN
|
||||
data_a[6] => ram_block1a14.PORTADATAIN
|
||||
data_a[7] => ram_block1a7.PORTADATAIN
|
||||
data_a[7] => ram_block1a15.PORTADATAIN
|
||||
data_b[0] => ram_block1a0.PORTBDATAIN
|
||||
data_b[0] => ram_block1a8.PORTBDATAIN
|
||||
data_b[1] => ram_block1a1.PORTBDATAIN
|
||||
data_b[1] => ram_block1a9.PORTBDATAIN
|
||||
data_b[2] => ram_block1a2.PORTBDATAIN
|
||||
data_b[2] => ram_block1a10.PORTBDATAIN
|
||||
data_b[3] => ram_block1a3.PORTBDATAIN
|
||||
data_b[3] => ram_block1a11.PORTBDATAIN
|
||||
data_b[4] => ram_block1a4.PORTBDATAIN
|
||||
data_b[4] => ram_block1a12.PORTBDATAIN
|
||||
data_b[5] => ram_block1a5.PORTBDATAIN
|
||||
data_b[5] => ram_block1a13.PORTBDATAIN
|
||||
data_b[6] => ram_block1a6.PORTBDATAIN
|
||||
data_b[6] => ram_block1a14.PORTBDATAIN
|
||||
data_b[7] => ram_block1a7.PORTBDATAIN
|
||||
data_b[7] => ram_block1a15.PORTBDATAIN
|
||||
q_a[0] <= mux_3nb:mux4.result[0]
|
||||
q_a[1] <= mux_3nb:mux4.result[1]
|
||||
q_a[2] <= mux_3nb:mux4.result[2]
|
||||
q_a[3] <= mux_3nb:mux4.result[3]
|
||||
q_a[4] <= mux_3nb:mux4.result[4]
|
||||
q_a[5] <= mux_3nb:mux4.result[5]
|
||||
q_a[6] <= mux_3nb:mux4.result[6]
|
||||
q_a[7] <= mux_3nb:mux4.result[7]
|
||||
q_b[0] <= mux_3nb:mux5.result[0]
|
||||
q_b[1] <= mux_3nb:mux5.result[1]
|
||||
q_b[2] <= mux_3nb:mux5.result[2]
|
||||
q_b[3] <= mux_3nb:mux5.result[3]
|
||||
q_b[4] <= mux_3nb:mux5.result[4]
|
||||
q_b[5] <= mux_3nb:mux5.result[5]
|
||||
q_b[6] <= mux_3nb:mux5.result[6]
|
||||
q_b[7] <= mux_3nb:mux5.result[7]
|
||||
wren_a => decode_jsa:decode2.enable
|
||||
wren_b => decode_jsa:decode3.enable
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode2
|
||||
data[0] => eq_node[1].IN0
|
||||
data[0] => eq_node[0].IN0
|
||||
enable => eq_node[1].IN1
|
||||
enable => eq_node[0].IN1
|
||||
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_jsa:decode3
|
||||
data[0] => eq_node[1].IN0
|
||||
data[0] => eq_node[0].IN0
|
||||
enable => eq_node[1].IN1
|
||||
enable => eq_node[0].IN1
|
||||
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_a
|
||||
data[0] => eq_node[1].IN0
|
||||
data[0] => eq_node[0].IN0
|
||||
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|decode_c8a:rden_decode_b
|
||||
data[0] => eq_node[1].IN0
|
||||
data[0] => eq_node[0].IN0
|
||||
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux4
|
||||
data[0] => result_node[0].IN1
|
||||
data[1] => result_node[1].IN1
|
||||
data[2] => result_node[2].IN1
|
||||
data[3] => result_node[3].IN1
|
||||
data[4] => result_node[4].IN1
|
||||
data[5] => result_node[5].IN1
|
||||
data[6] => result_node[6].IN1
|
||||
data[7] => result_node[7].IN1
|
||||
data[8] => result_node[0].IN1
|
||||
data[9] => result_node[1].IN1
|
||||
data[10] => result_node[2].IN1
|
||||
data[11] => result_node[3].IN1
|
||||
data[12] => result_node[4].IN1
|
||||
data[13] => result_node[5].IN1
|
||||
data[14] => result_node[6].IN1
|
||||
data[15] => result_node[7].IN1
|
||||
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
sel[0] => result_node[7].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[6].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[5].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[4].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[3].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[2].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[1].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[0].IN0
|
||||
sel[0] => _.IN0
|
||||
|
||||
|
||||
|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_bui2:auto_generated|mux_3nb:mux5
|
||||
data[0] => result_node[0].IN1
|
||||
data[1] => result_node[1].IN1
|
||||
data[2] => result_node[2].IN1
|
||||
data[3] => result_node[3].IN1
|
||||
data[4] => result_node[4].IN1
|
||||
data[5] => result_node[5].IN1
|
||||
data[6] => result_node[6].IN1
|
||||
data[7] => result_node[7].IN1
|
||||
data[8] => result_node[0].IN1
|
||||
data[9] => result_node[1].IN1
|
||||
data[10] => result_node[2].IN1
|
||||
data[11] => result_node[3].IN1
|
||||
data[12] => result_node[4].IN1
|
||||
data[13] => result_node[5].IN1
|
||||
data[14] => result_node[6].IN1
|
||||
data[15] => result_node[7].IN1
|
||||
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
sel[0] => result_node[7].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[6].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[5].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[4].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[3].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[2].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[1].IN0
|
||||
sel[0] => _.IN0
|
||||
sel[0] => result_node[0].IN0
|
||||
sel[0] => _.IN0
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user