benny/de0-zx-spectrum
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ROM0 now has the spectrum rom

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This commit is contained in:
Adrian Scripca
2022-03-30 13:18:06 +03:00
parent c59b02b186
commit 9d6eb7a9fa
94 changed files with 27700 additions and 9902 deletions
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output_files/spectrum.map.rpt
+99 -69
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum
Wed Mar 30 12:38:28 2022
Wed Mar 30 13:12:13 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -16,7 +16,7 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
13. altsyncram Parameter Settings by Entity Instance
14. Elapsed Time Per Partition
@@ -46,18 +46,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ;
; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 33 ;
; Total combinational functions ; 33 ;
; Dedicated logic registers ; 24 ;
; Total registers ; 24 ;
; Total logic elements ; 54 ;
; Total combinational functions ; 52 ;
; Dedicated logic registers ; 38 ;
; Total registers ; 38 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 64 ;
; Total memory bits ; 131,072 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
@@ -405,12 +405,6 @@ File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
@@ -471,10 +465,28 @@ File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library :
File Name with User-Entered Path : db/altsyncram_ro91.tdf
File Name with User-Entered Path : db/altsyncram_qh91.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf
Library :
File Name with User-Entered Path : rom/gw03.hex
Used in Netlist : yes
File Type : Auto-Found Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom/gw03.hex
Library :
File Name with User-Entered Path : db/decode_c8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_c8a.tdf
Library :
File Name with User-Entered Path : db/mux_3nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf
Library :
+--------------------------------------------------------------------------------+
@@ -485,29 +497,29 @@ Library :
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 33 ;
; Estimated Total logic elements ; 54 ;
; ; ;
; Total combinational functions ; 33 ;
; Total combinational functions ; 52 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 22 ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 10 ;
; -- <=2 input functions ; 34 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 20 ;
; -- normal mode ; 20 ;
; -- arithmetic mode ; 32 ;
; ; ;
; Total registers ; 24 ;
; -- Dedicated logic registers ; 24 ;
; Total registers ; 38 ;
; -- Dedicated logic registers ; 38 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
; Total memory bits ; 64 ;
; Total memory bits ; 131072 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 183 ;
; Average fan-out ; 2.20 ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 473 ;
; Average fan-out ; 3.81 ;
+---------------------------------------------+----------------+
@@ -515,9 +527,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 33 (33)
LC Registers : 24 (24)
Memory Bits : 64
LC Combinationals : 52 (44)
LC Registers : 38 (36)
Memory Bits : 131072
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -527,9 +539,9 @@ Full Hierarchy Name : |spectrum
Library Name : work
Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
LC Combinationals : 8 (0)
LC Registers : 2 (0)
Memory Bits : 131072
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -539,9 +551,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
LC Combinationals : 8 (0)
LC Registers : 2 (0)
Memory Bits : 131072
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -550,16 +562,28 @@ Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
LC Combinationals : 8 (0)
LC Registers : 2 (2)
Memory Bits : 131072
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2|
LC Combinationals : 8 (8)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2
Library Name : work
+--------------------------------------------------------------------------------+
@@ -569,15 +593,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Port A Depth : 8
Port A Depth : 16384
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 64
MIF : led_patterns.mif
Size : 131072
MIF : ./rom/gw03.hex
+--------------------------------------------------------------------------------+
@@ -601,18 +625,18 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 24 ;
; Total registers ; 38 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Clock Enable ; 13 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------+
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ;
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
@@ -658,11 +682,11 @@ Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 3
Value : 14
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 8
Value : 16384
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
@@ -778,7 +802,7 @@ Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Value : ./rom/gw03.hex
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
@@ -830,7 +854,7 @@ Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_ro91
Value : altsyncram_qh91
Type : Untyped
+--------------------------------------------------------------------------------+
@@ -846,7 +870,7 @@ Note: In order to hide this table in the UI and the text report file, please set
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 8 ;
; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
@@ -872,7 +896,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 12:38:26 2022
Info: Processing started: Wed Mar 30 13:12:11 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
@@ -880,8 +904,8 @@ Info (12021): Found 1 design units, including 1 entities, in source file spectru
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
@@ -889,32 +913,38 @@ Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_componen
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "init_file" = "./rom/gw03.hex"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "8"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "widthad_a" = "3"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf
Info (12023): Found entity 1: altsyncram_ro91
Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf
Info (12023): Found entity 1: altsyncram_qh91
Info (12128): Elaborating entity "altsyncram_qh91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
Info (12023): Found entity 1: decode_c8a
Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 54 logic cells
Info (21064): Implemented 8 RAM segments
Info (21064): Implemented 16 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 384 megabytes
Info: Processing ended: Wed Mar 30 12:38:28 2022
Info: Peak virtual memory: 392 megabytes
Info: Processing ended: Wed Mar 30 13:12:13 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: Total CPU time (on all processors): 00:00:02