Added kempston, autofire and enable autofire, enable turbo push buttons for GPIO1[32] and GPIO1[33]
This commit is contained in:
@@ -0,0 +1,36 @@
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ADDRESS_REG_B=CLOCK1
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CLOCK_ENABLE_INPUT_A=BYPASS
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CLOCK_ENABLE_INPUT_B=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
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CLOCK_ENABLE_OUTPUT_B=BYPASS
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INDATA_REG_B=CLOCK1
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INTENDED_DEVICE_FAMILY="Cyclone IV E"
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LPM_TYPE=altsyncram
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NUMWORDS_A=16384
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NUMWORDS_B=16384
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OPERATION_MODE=BIDIR_DUAL_PORT
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OUTDATA_ACLR_A=NONE
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OUTDATA_ACLR_B=NONE
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OUTDATA_REG_A=CLOCK0
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OUTDATA_REG_B=CLOCK1
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
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READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
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WIDTHAD_A=14
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WIDTHAD_B=14
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WIDTH_A=8
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WIDTH_B=8
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WIDTH_BYTEENA_A=1
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WIDTH_BYTEENA_B=1
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WRCONTROL_WRADDRESS_REG_B=CLOCK1
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DEVICE_FAMILY="Cyclone IV E"
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address_a
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address_b
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clock0
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clock1
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data_a
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data_b
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wren_a
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wren_b
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q_a
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q_b
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@@ -0,0 +1,32 @@
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Quartus II generated Memory Initialization File (.mif)
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WIDTH=8;
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DEPTH=8;
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ADDRESS_RADIX=UNS;
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DATA_RADIX=UNS;
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CONTENT BEGIN
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0 : 129;
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1 : 66;
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2 : 36;
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3 : 24;
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4 : 36;
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5 : 66;
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6 : 129;
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7 : 255;
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END;
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@@ -0,0 +1,436 @@
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/*
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This SDRAM controller is for the Mojo's SDRAM shield which uses
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a 48LC32M8A2-7E SDRAM chip. This module was designed under the
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assumption that the click rate is 100MHz. Timing values would
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need to be re-evaluated under different clock rates.
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This controller features two baisc improvements over the most
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basic of controllers. It does burst reads and writes of 4 bytes,
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and it only closes a row when it has to.
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*/
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module sdram (
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input clk,
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input rst,
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// these signals go directly to the IO pins
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output sdram_clk,
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output sdram_cle,
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output sdram_cs,
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output sdram_cas,
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output sdram_ras,
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output sdram_we,
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output sdram_dqm,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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inout [7:0] sdram_dq,
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// User interface
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input [22:0] addr, // address to read/write
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input rw, // 1 = write, 0 = read
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input [31:0] data_in, // data from a read
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output [31:0] data_out, // data for a write
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output busy, // controller is busy when high
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input in_valid, // pulse high to initiate a read/write
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output out_valid // pulses high when data from read is valid
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);
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// Commands for the SDRAM
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localparam CMD_UNSELECTED = 4'b1000;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE_REG = 4'b0000;
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localparam STATE_SIZE = 4;
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localparam INIT = 0,
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WAIT = 1,
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PRECHARGE_INIT = 2,
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REFRESH_INIT_1 = 3,
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REFRESH_INIT_2 = 4,
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LOAD_MODE_REG = 5,
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IDLE = 6,
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REFRESH = 7,
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ACTIVATE = 8,
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READ = 9,
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READ_RES = 10,
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WRITE = 11,
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PRECHARGE = 12;
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wire sdram_clk_ddr;
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// This is used to drive the SDRAM clock
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) ODDR2_inst (
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.Q(sdram_clk_ddr), // 1-bit DDR output data
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.C0(clk), // 1-bit clock input
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.C1(~clk), // 1-bit clock input
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.CE(1'b1), // 1-bit clock enable input
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.D0(1'b0), // 1-bit data input (associated with C0)
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.D1(1'b1), // 1-bit data input (associated with C1)
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.R(1'b0), // 1-bit reset input
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.S(1'b0) // 1-bit set input
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);
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IODELAY2 #(
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.IDELAY_VALUE(0),
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.IDELAY_MODE("NORMAL"),
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.ODELAY_VALUE(100), // value of 100 seems to work at 100MHz
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.IDELAY_TYPE("FIXED"),
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.DELAY_SRC("ODATAIN"),
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.DATA_RATE("SDR")
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) IODELAY_inst (
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.IDATAIN(1'b0),
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.T(1'b0),
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.ODATAIN(sdram_clk_ddr),
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.CAL(1'b0),
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.IOCLK0(1'b0),
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.IOCLK1(1'b0),
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.CLK(1'b0),
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.INC(1'b0),
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.CE(1'b0),
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.RST(1'b0),
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.BUSY(),
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.DATAOUT(),
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.DATAOUT2(),
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.TOUT(),
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.DOUT(sdram_clk)
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);
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// registers for SDRAM signals
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reg cle_d, dqm_d;
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reg [3:0] cmd_d;
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reg [1:0] ba_d;
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reg [12:0] a_d;
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reg [7:0] dq_d;
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reg [7:0] dqi_d;
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// We want the output/input registers to be embedded in the
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// IO buffers so we set IOB to "TRUE". This is to ensure all
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// the signals are sent and received at the same time.
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(* IOB = "TRUE" *)
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reg cle_q, dqm_q;
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(* IOB = "TRUE" *)
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reg [3:0] cmd_q;
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(* IOB = "TRUE" *)
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reg [1:0] ba_q;
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(* IOB = "TRUE" *)
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reg [12:0] a_q;
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(* IOB = "TRUE" *)
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reg [7:0] dq_q;
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(* IOB = "TRUE" *)
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reg [7:0] dqi_q;
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reg dq_en_d, dq_en_q;
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// Output assignments
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assign sdram_cle = cle_q;
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assign sdram_cs = cmd_q[3];
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assign sdram_ras = cmd_q[2];
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assign sdram_cas = cmd_q[1];
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assign sdram_we = cmd_q[0];
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assign sdram_dqm = dqm_q;
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assign sdram_ba = ba_q;
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assign sdram_a = a_q;
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assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1
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reg [STATE_SIZE-1:0] state_d, state_q = INIT;
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reg [STATE_SIZE-1:0] next_state_d, next_state_q;
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reg [22:0] addr_d, addr_q;
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reg [31:0] data_d, data_q;
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reg out_valid_d, out_valid_q;
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assign data_out = data_q;
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assign busy = !ready_q;
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assign out_valid = out_valid_q;
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reg [15:0] delay_ctr_d, delay_ctr_q;
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reg [1:0] byte_ctr_d, byte_ctr_q;
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reg [9:0] refresh_ctr_d, refresh_ctr_q;
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reg refresh_flag_d, refresh_flag_q;
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reg ready_d, ready_q;
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reg saved_rw_d, saved_rw_q;
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reg [22:0] saved_addr_d, saved_addr_q;
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reg [31:0] saved_data_d, saved_data_q;
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reg rw_op_d, rw_op_q;
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reg [3:0] row_open_d, row_open_q;
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reg [12:0] row_addr_d[3:0], row_addr_q[3:0];
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reg [2:0] precharge_bank_d, precharge_bank_q;
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integer i;
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always @* begin
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// Default values
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dq_d = dq_q;
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dqi_d = sdram_dq;
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dq_en_d = 1'b0; // normally keep the bus in high-Z
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cle_d = cle_q;
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cmd_d = CMD_NOP; // default to NOP
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dqm_d = 1'b0;
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ba_d = 2'd0;
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a_d = 25'd0;
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state_d = state_q;
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next_state_d = next_state_q;
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delay_ctr_d = delay_ctr_q;
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addr_d = addr_q;
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data_d = data_q;
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out_valid_d = 1'b0;
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precharge_bank_d = precharge_bank_q;
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rw_op_d = rw_op_q;
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byte_ctr_d = 2'd0;
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row_open_d = row_open_q;
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// row_addr is a 2d array and must be coppied this way
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for (i = 0; i < 4; i = i + 1)
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row_addr_d[i] = row_addr_q[i];
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// The data in the SDRAM must be refreshed periodically.
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// This conter ensures that the data remains intact.
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refresh_flag_d = refresh_flag_q;
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refresh_ctr_d = refresh_ctr_q + 1'b1;
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if (refresh_ctr_q > 10'd750) begin
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refresh_ctr_d = 10'd0;
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refresh_flag_d = 1'b1;
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end
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saved_rw_d = saved_rw_q;
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saved_data_d = saved_data_q;
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saved_addr_d = saved_addr_q;
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ready_d = ready_q;
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// This is a queue of 1 for read/write operations.
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// When the queue is empty we aren't busy and can
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// accept another request.
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if (ready_q && in_valid) begin
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saved_rw_d = rw;
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saved_data_d = data_in;
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saved_addr_d = addr;
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ready_d = 1'b0;
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end
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case (state_q)
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///// INITALIZATION /////
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INIT: begin
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ready_d = 1'b0;
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row_open_d = 4'b0;
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out_valid_d = 1'b0;
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a_d = 13'b0;
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ba_d = 2'b0;
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cle_d = 1'b1;
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state_d = WAIT;
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delay_ctr_d = 16'd10100; // wait for 101us
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next_state_d = PRECHARGE_INIT;
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dq_en_d = 1'b0;
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end
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WAIT: begin
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delay_ctr_d = delay_ctr_q - 1'b1;
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if (delay_ctr_q == 13'd0) begin
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state_d = next_state_q;
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if (next_state_q == WRITE) begin
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dq_en_d = 1'b1; // enable the bus early
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dq_d = data_q[7:0];
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end
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end
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end
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PRECHARGE_INIT: begin
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cmd_d = CMD_PRECHARGE;
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a_d[10] = 1'b1; // all banks
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ba_d = 2'd0;
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state_d = WAIT;
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next_state_d = REFRESH_INIT_1;
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delay_ctr_d = 13'd0;
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end
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REFRESH_INIT_1: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd7;
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next_state_d = REFRESH_INIT_2;
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end
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REFRESH_INIT_2: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd7;
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next_state_d = LOAD_MODE_REG;
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end
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LOAD_MODE_REG: begin
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cmd_d = CMD_LOAD_MODE_REG;
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ba_d = 2'b0;
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// Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4
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a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010
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state_d = WAIT;
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delay_ctr_d = 13'd1;
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next_state_d = IDLE;
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refresh_flag_d = 1'b0;
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refresh_ctr_d = 10'b1;
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ready_d = 1'b1;
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end
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///// IDLE STATE /////
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IDLE: begin
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if (refresh_flag_q) begin // we need to do a refresh
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state_d = PRECHARGE;
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next_state_d = REFRESH;
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precharge_bank_d = 3'b100; // all banks
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refresh_flag_d = 1'b0; // clear the refresh flag
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end else if (!ready_q) begin // operation waiting
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ready_d = 1'b1; // clear the queue
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rw_op_d = saved_rw_q; // save the values we'll need later
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addr_d = saved_addr_q;
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if (saved_rw_q) // Write
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data_d = saved_data_q;
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// if the row is open we don't have to activate it
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if (row_open_q[saved_addr_q[9:8]]) begin
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if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin
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// Row is already open
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if (saved_rw_q)
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state_d = WRITE;
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else
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state_d = READ;
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end else begin
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// A different row in the bank is open
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state_d = PRECHARGE; // precharge open row
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precharge_bank_d = {1'b0, saved_addr_q[9:8]};
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next_state_d = ACTIVATE; // open current row
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end
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end else begin
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// no rows open
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state_d = ACTIVATE; // open the row
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end
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end
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end
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///// REFRESH /////
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REFRESH: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns)
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next_state_d = IDLE;
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end
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///// ACTIVATE /////
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ACTIVATE: begin
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cmd_d = CMD_ACTIVE;
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a_d = addr_q[22:10];
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ba_d = addr_q[9:8];
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delay_ctr_d = 13'd0;
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state_d = WAIT;
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if (rw_op_q)
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next_state_d = WRITE;
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else
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next_state_d = READ;
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row_open_d[addr_q[9:8]] = 1'b1; // row is now open
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row_addr_d[addr_q[9:8]] = addr_q[22:10];
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||||
end
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||||
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///// READ /////
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READ: begin
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cmd_d = CMD_READ;
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a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
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||||
ba_d = addr_q[9:8];
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state_d = WAIT;
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delay_ctr_d = 13'd2; // wait for the data to show up
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next_state_d = READ_RES;
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||||
end
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READ_RES: begin
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byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes
|
||||
data_d = {dqi_q, data_q[31:8]}; // shift the data in
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if (byte_ctr_q == 2'd3) begin
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||||
out_valid_d = 1'b1;
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state_d = IDLE;
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||||
end
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||||
end
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||||
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///// WRITE /////
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WRITE: begin
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byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes
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||||
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if (byte_ctr_q == 2'd0) // first byte send write command
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||||
cmd_d = CMD_WRITE;
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||||
|
||||
dq_d = data_q[7:0];
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||||
data_d = {8'h00, data_q[31:8]}; // shift the data out
|
||||
dq_en_d = 1'b1; // enable out bus
|
||||
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
|
||||
ba_d = addr_q[9:8];
|
||||
|
||||
if (byte_ctr_q == 2'd3) begin
|
||||
state_d = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
///// PRECHARGE /////
|
||||
PRECHARGE: begin
|
||||
cmd_d = CMD_PRECHARGE;
|
||||
a_d[10] = precharge_bank_q[2]; // all banks
|
||||
ba_d = precharge_bank_q[1:0];
|
||||
state_d = WAIT;
|
||||
delay_ctr_d = 13'd0;
|
||||
|
||||
if (precharge_bank_q[2]) begin
|
||||
row_open_d = 4'b0000; // closed all rows
|
||||
end else begin
|
||||
row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row
|
||||
end
|
||||
end
|
||||
|
||||
default: state_d = INIT;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(rst) begin
|
||||
cle_q <= 1'b0;
|
||||
dq_en_q <= 1'b0;
|
||||
state_q <= INIT;
|
||||
ready_q <= 1'b0;
|
||||
end else begin
|
||||
cle_q <= cle_d;
|
||||
dq_en_q <= dq_en_d;
|
||||
state_q <= state_d;
|
||||
ready_q <= ready_d;
|
||||
end
|
||||
|
||||
saved_rw_q <= saved_rw_d;
|
||||
saved_data_q <= saved_data_d;
|
||||
saved_addr_q <= saved_addr_d;
|
||||
|
||||
cmd_q <= cmd_d;
|
||||
dqm_q <= dqm_d;
|
||||
ba_q <= ba_d;
|
||||
a_q <= a_d;
|
||||
dq_q <= dq_d;
|
||||
dqi_q <= dqi_d;
|
||||
|
||||
next_state_q <= next_state_d;
|
||||
refresh_flag_q <= refresh_flag_d;
|
||||
refresh_ctr_q <= refresh_ctr_d;
|
||||
data_q <= data_d;
|
||||
addr_q <= addr_d;
|
||||
out_valid_q <= out_valid_d;
|
||||
row_open_q <= row_open_d;
|
||||
for (i = 0; i < 4; i = i + 1)
|
||||
row_addr_q[i] <= row_addr_d[i];
|
||||
precharge_bank_q <= precharge_bank_d;
|
||||
rw_op_q <= rw_op_d;
|
||||
byte_ctr_q <= byte_ctr_d;
|
||||
delay_ctr_q <= delay_ctr_d;
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,186 @@
|
||||
Assembler report for spectrum
|
||||
Sat Apr 2 16:35:54 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: spectrum.sof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Sat Apr 2 16:35:54 2022 ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Assembler Settings ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Option : Use smart compilation
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Enable compact report table
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate compressed bitstreams
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Compression mode
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Clock source for configuration device
|
||||
Setting : Internal
|
||||
Default Value : Internal
|
||||
|
||||
Option : Clock frequency of the configuration device
|
||||
Setting : 10 MHZ
|
||||
Default Value : 10 MHz
|
||||
|
||||
Option : Divide clock frequency by
|
||||
Setting : 1
|
||||
Default Value : 1
|
||||
|
||||
Option : Auto user code
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Use configuration device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Configuration device
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Configuration device auto user code
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate Tabular Text File (.ttf) For Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate Raw Binary File (.rbf) For Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Hexadecimal Output File start address
|
||||
Setting : 0
|
||||
Default Value : 0
|
||||
|
||||
Option : Hexadecimal Output File count direction
|
||||
Setting : Up
|
||||
Default Value : Up
|
||||
|
||||
Option : Release clears before tri-states
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Auto-restart configuration after error
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Enable OCT_DONE
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate Serial Vector Format File (.svf) for Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate a JEDEC STAPL Format File (.jam) for Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
|
||||
Setting : On
|
||||
Default Value : On
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+---------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+---------------------------+
|
||||
; File Name ;
|
||||
+---------------------------+
|
||||
; spectrum.sof ;
|
||||
+---------------------------+
|
||||
|
||||
|
||||
+----------------------------------------+
|
||||
; Assembler Device Options: spectrum.sof ;
|
||||
+----------------+-----------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------+
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; JTAG usercode ; 0x00589516 ;
|
||||
; Checksum ; 0x00589516 ;
|
||||
+----------------+-----------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 16:35:52 2022
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 399 megabytes
|
||||
Info: Processing ended: Sat Apr 2 16:35:54 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
P ActionCode(Cfg)
|
||||
Device PartName(EP4CE22F17) Path("/home/benny/work/fpga/spectrum/output_files/") File("spectrum.sof") MfrSpec(OpMask(1));
|
||||
|
||||
ChainEnd;
|
||||
|
||||
AlteraBegin;
|
||||
ChainType(JTAG);
|
||||
AlteraEnd;
|
||||
@@ -0,0 +1 @@
|
||||
Sat Apr 2 18:51:29 2022
|
||||
@@ -0,0 +1,107 @@
|
||||
EDA Netlist Writer report for spectrum
|
||||
Sat Apr 2 16:36:04 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. EDA Netlist Writer Summary
|
||||
3. Simulation Settings
|
||||
4. Simulation Generated Files
|
||||
5. EDA Netlist Writer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Sat Apr 2 16:36:04 2022 ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Simulation Files Creation ; Successful ;
|
||||
+---------------------------+---------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Simulation Settings ;
|
||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
||||
; Option ; Setting ;
|
||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
||||
; Tool Name ; ModelSim-Altera (Verilog) ;
|
||||
; Generate netlist for functional simulation only ; Off ;
|
||||
; Time scale ; 1 ps ;
|
||||
; Truncate long hierarchy paths ; Off ;
|
||||
; Map illegal HDL characters ; Off ;
|
||||
; Flatten buses into individual nodes ; Off ;
|
||||
; Maintain hierarchy ; Off ;
|
||||
; Bring out device-wide set/reset signals as ports ; Off ;
|
||||
; Enable glitch filtering ; Off ;
|
||||
; Do not write top level VHDL entity ; Off ;
|
||||
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
||||
; Architecture name in VHDL output netlist ; structure ;
|
||||
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
||||
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Simulation Generated Files ;
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Generated Files ;
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum.vo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo ;
|
||||
; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_v.sdo ;
|
||||
+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------+
|
||||
; EDA Netlist Writer Messages ;
|
||||
+-----------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit EDA Netlist Writer
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 16:36:01 2022
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
|
||||
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_min_1200mv_0c_fast.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 384 megabytes
|
||||
Info: Processing ended: Sat Apr 2 16:36:04 2022
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
|
||||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||
Extra Info (176238): Start inferring scan chains for DSP blocks
|
||||
Extra Info (176239): Inferring scan chains for DSP blocks is complete
|
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
@@ -0,0 +1,16 @@
|
||||
Fitter Status : Successful - Sat Apr 2 16:35:50 2022
|
||||
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Revision Name : spectrum
|
||||
Top-level Entity Name : spectrum
|
||||
Family : Cyclone IV E
|
||||
Device : EP4CE22F17C6
|
||||
Timing Models : Final
|
||||
Total logic elements : 2,621 / 22,320 ( 12 % )
|
||||
Total combinational functions : 2,487 / 22,320 ( 11 % )
|
||||
Dedicated logic registers : 635 / 22,320 ( 3 % )
|
||||
Total registers : 664
|
||||
Total pins : 114 / 154 ( 74 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 524,288 / 608,256 ( 86 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
|
||||
Total PLLs : 2 / 4 ( 50 % )
|
||||
@@ -0,0 +1,337 @@
|
||||
Flow report for spectrum
|
||||
Sat Apr 2 18:53:05 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Flow Status ; Flow Failed - Sat Apr 2 18:53:05 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; N/A until Partition Merge ;
|
||||
; Total combinational functions ; N/A until Partition Merge ;
|
||||
; Dedicated logic registers ; N/A until Partition Merge ;
|
||||
; Total registers ; N/A until Partition Merge ;
|
||||
; Total pins ; N/A until Partition Merge ;
|
||||
; Total virtual pins ; N/A until Partition Merge ;
|
||||
; Total memory bits ; N/A until Partition Merge ;
|
||||
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
|
||||
; Total PLLs ; N/A until Partition Merge ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 04/02/2022 18:53:05 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; spectrum ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Assignment Name : COMPILER_SIGNATURE_ID
|
||||
Value : 0.164891478433237
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : EDA_OUTPUT_DATA_FORMAT
|
||||
Value : Verilog Hdl
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : eda_simulation
|
||||
|
||||
Assignment Name : EDA_SIMULATION_TOOL
|
||||
Value : ModelSim-Altera (Verilog)
|
||||
Default Value : <None>
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ROM: 1-PORT
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : RAM: 2-PORT
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : RAM: 1-PORT
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ALTPLL
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ROM: 1-PORT
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ALTPLL
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : RAM: 2-PORT
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ALTPLL
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.0
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MAX_CORE_JUNCTION_TEMP
|
||||
Value : 85
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MIN_CORE_JUNCTION_TEMP
|
||||
Value : 0
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : rom0_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : ram16_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : ram32_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll.ppf
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : rom_scr_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll_video_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll_video.ppf
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : ram_video_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : sdram_clk_gen_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : sdram_clk_gen.ppf
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
|
||||
Value : 1.2V
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : PARTITION_COLOR
|
||||
Value : 16764057
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : Top
|
||||
|
||||
Assignment Name : PARTITION_FITTER_PRESERVATION_LEVEL
|
||||
Value : PLACEMENT_AND_ROUTING
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : Top
|
||||
|
||||
Assignment Name : PARTITION_NETLIST_TYPE
|
||||
Value : SOURCE
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : Top
|
||||
|
||||
Assignment Name : PROJECT_OUTPUT_DIRECTORY
|
||||
Value : output_files
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Module Name : Analysis & Synthesis
|
||||
Elapsed Time : 00:00:01
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 397 MB
|
||||
Total CPU Time (on all processors) : 00:00:01
|
||||
|
||||
Module Name : Total
|
||||
Elapsed Time : 00:00:01
|
||||
Average Processors Used : --
|
||||
Peak Virtual Memory : --
|
||||
Total CPU Time (on all processors) : 00:00:01
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Module Name : Analysis & Synthesis
|
||||
Machine Hostname : alpha
|
||||
OS Name : Ubuntu 21.10
|
||||
OS Version : 21
|
||||
Processor type : x86_64
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="e252db009bbe51b65b45"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
@@ -0,0 +1,544 @@
|
||||
Analysis & Synthesis report for spectrum
|
||||
Sat Apr 2 18:53:05 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Messages
|
||||
6. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Failed - Sat Apr 2 18:53:05 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Total logic elements ; N/A until Partition Merge ;
|
||||
; Total combinational functions ; N/A until Partition Merge ;
|
||||
; Dedicated logic registers ; N/A until Partition Merge ;
|
||||
; Total registers ; N/A until Partition Merge ;
|
||||
; Total pins ; N/A until Partition Merge ;
|
||||
; Total virtual pins ; N/A until Partition Merge ;
|
||||
; Total memory bits ; N/A until Partition Merge ;
|
||||
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
|
||||
; Total PLLs ; N/A until Partition Merge ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Option : Device
|
||||
Setting : EP4CE22F17C6
|
||||
Default Value :
|
||||
|
||||
Option : Top-level entity name
|
||||
Setting : spectrum
|
||||
Default Value : spectrum
|
||||
|
||||
Option : Family name
|
||||
Setting : Cyclone IV E
|
||||
Default Value : Cyclone IV GX
|
||||
|
||||
Option : Use smart compilation
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Enable compact report table
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Restructure Multiplexers
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Create Debugging Nodes for IP Cores
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Preserve fewer node names
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Disable OpenCore Plus hardware evaluation
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Verilog Version
|
||||
Setting : Verilog_2001
|
||||
Default Value : Verilog_2001
|
||||
|
||||
Option : VHDL Version
|
||||
Setting : VHDL_1993
|
||||
Default Value : VHDL_1993
|
||||
|
||||
Option : State Machine Processing
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Safe State Machine
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Extract Verilog State Machines
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Extract VHDL State Machines
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Ignore Verilog initial constructs
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Iteration limit for constant Verilog loops
|
||||
Setting : 5000
|
||||
Default Value : 5000
|
||||
|
||||
Option : Iteration limit for non-constant Verilog loops
|
||||
Setting : 250
|
||||
Default Value : 250
|
||||
|
||||
Option : Add Pass-Through Logic to Inferred RAMs
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Infer RAMs from Raw Logic
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Parallel Synthesis
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : DSP Block Balancing
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : NOT Gate Push-Back
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Power-Up Don't Care
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Remove Redundant Logic Cells
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Remove Duplicate Registers
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Ignore CARRY Buffers
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Ignore CASCADE Buffers
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Ignore GLOBAL Buffers
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Ignore ROW GLOBAL Buffers
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Ignore LCELL Buffers
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Ignore SOFT Buffers
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Limit AHDL Integers to 32 Bits
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Optimization Technique
|
||||
Setting : Balanced
|
||||
Default Value : Balanced
|
||||
|
||||
Option : Carry Chain Length
|
||||
Setting : 70
|
||||
Default Value : 70
|
||||
|
||||
Option : Auto Carry Chains
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto Open-Drain Pins
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Perform WYSIWYG Primitive Resynthesis
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Auto ROM Replacement
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto RAM Replacement
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto DSP Block Replacement
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto Shift Register Replacement
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Allow Shift Register Merging across Hierarchies
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Auto Clock Enable Replacement
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Strict RAM Replacement
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Allow Synchronous Control Signals
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Force Use of Synchronous Clear Signals
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Auto RAM Block Balancing
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto RAM to Logic Cell Conversion
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Auto Resource Sharing
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Allow Any RAM Size For Recognition
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Allow Any ROM Size For Recognition
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Allow Any Shift Register Size For Recognition
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Use LogicLock Constraints during Resource Balancing
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Ignore translate_off and synthesis_off directives
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Timing-Driven Synthesis
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Report Parameter Settings
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Report Source Assignments
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Report Connectivity Checks
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Ignore Maximum Fan-Out Assignments
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Synchronization Register Chain Length
|
||||
Setting : 2
|
||||
Default Value : 2
|
||||
|
||||
Option : PowerPlay Power Optimization
|
||||
Setting : Normal compilation
|
||||
Default Value : Normal compilation
|
||||
|
||||
Option : HDL message level
|
||||
Setting : Level2
|
||||
Default Value : Level2
|
||||
|
||||
Option : Suppress Register Optimization Related Messages
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Number of Removed Registers Reported in Synthesis Report
|
||||
Setting : 5000
|
||||
Default Value : 5000
|
||||
|
||||
Option : Number of Swept Nodes Reported in Synthesis Report
|
||||
Setting : 5000
|
||||
Default Value : 5000
|
||||
|
||||
Option : Number of Inverted Registers Reported in Synthesis Report
|
||||
Setting : 100
|
||||
Default Value : 100
|
||||
|
||||
Option : Clock MUX Protection
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Auto Gated Clock Conversion
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Block Design Naming
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : SDC constraint protection
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Synthesis Effort
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Shift Register Replacement - Allow Asynchronous Clear Signal
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Pre-Mapping Resynthesis Optimization
|
||||
Setting : Off
|
||||
Default Value : Off
|
||||
|
||||
Option : Analysis & Synthesis Message Level
|
||||
Setting : Medium
|
||||
Default Value : Medium
|
||||
|
||||
Option : Disable Register Merging Across Hierarchies
|
||||
Setting : Auto
|
||||
Default Value : Auto
|
||||
|
||||
Option : Resource Aware Inference For Block RAM
|
||||
Setting : On
|
||||
Default Value : On
|
||||
|
||||
Option : Synthesis Seed
|
||||
Setting : 1
|
||||
Default Value : 1
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 12 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 18:53:04 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
|
||||
Info (12023): Found entity 1: spectrum
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
|
||||
Info (12023): Found entity 1: rom0
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
|
||||
Info (12023): Found entity 1: ram16
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
|
||||
Info (12023): Found entity 1: ram32
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
|
||||
Info (12023): Found entity 1: pll
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu.v
|
||||
Info (12023): Found entity 1: alu
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v
|
||||
Info (12023): Found entity 1: alu_bit_select
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v
|
||||
Info (12023): Found entity 1: alu_control
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v
|
||||
Info (12023): Found entity 1: alu_core
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v
|
||||
Info (12023): Found entity 1: alu_flags
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v
|
||||
Info (12023): Found entity 1: alu_mux_2
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v
|
||||
Info (12023): Found entity 1: alu_mux_2z
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v
|
||||
Info (12023): Found entity 1: alu_mux_3z
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v
|
||||
Info (12023): Found entity 1: alu_mux_4
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v
|
||||
Info (12023): Found entity 1: alu_mux_8
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v
|
||||
Info (12023): Found entity 1: alu_prep_daa
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v
|
||||
Info (12023): Found entity 1: alu_select
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v
|
||||
Info (12023): Found entity 1: alu_shifter_core
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v
|
||||
Info (12023): Found entity 1: alu_slice
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v
|
||||
Info (12023): Found entity 1: clk_delay
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v
|
||||
Info (12023): Found entity 1: decode_state
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/execute.v
|
||||
Info (12023): Found entity 1: execute
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v
|
||||
Info (12023): Found entity 1: interrupts
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/ir.v
|
||||
Info (12023): Found entity 1: ir
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v
|
||||
Info (12023): Found entity 1: memory_ifc
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v
|
||||
Info (12023): Found entity 1: pin_control
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v
|
||||
Info (12023): Found entity 1: pla_decode
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/resets.v
|
||||
Info (12023): Found entity 1: resets
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v
|
||||
Info (12023): Found entity 1: sequencer
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v
|
||||
Info (12023): Found entity 1: address_latch
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v
|
||||
Info (12023): Found entity 1: address_mux
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v
|
||||
Info (12023): Found entity 1: address_pins
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v
|
||||
Info (12023): Found entity 1: bus_control
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v
|
||||
Info (12023): Found entity 1: bus_switch
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v
|
||||
Info (12023): Found entity 1: control_pins_n
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v
|
||||
Info (12023): Found entity 1: data_pins
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v
|
||||
Info (12023): Found entity 1: data_switch
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v
|
||||
Info (12023): Found entity 1: data_switch_mask
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v
|
||||
Info (12023): Found entity 1: inc_dec
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v
|
||||
Info (12023): Found entity 1: inc_dec_2bit
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v
|
||||
Info (12023): Found entity 1: z80_top_direct_n
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v
|
||||
Info (12023): Found entity 1: reg_control
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v
|
||||
Info (12023): Found entity 1: reg_file
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v
|
||||
Info (12023): Found entity 1: reg_latch
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ula/clocks.sv
|
||||
Info (12023): Found entity 1: clocks
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv
|
||||
Info (12023): Found entity 1: zx_keyboard
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ula/video.sv
|
||||
Info (12023): Found entity 1: video
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ula/ula.sv
|
||||
Info (12023): Found entity 1: ula
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv
|
||||
Info (12023): Found entity 1: ps2_keyboard
|
||||
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd
|
||||
Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
|
||||
Info (12023): Found entity 1: i2c_loader
|
||||
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd
|
||||
Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
|
||||
Info (12023): Found entity 1: i2s_intf
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file rom_scr.v
|
||||
Info (12023): Found entity 1: rom_scr
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v
|
||||
Info (12023): Found entity 1: pll_video
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v
|
||||
Info (12023): Found entity 1: ram_video
|
||||
Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl
|
||||
Info (12022): Found design unit 1: sdram_controller-rtl
|
||||
Info (12023): Found entity 1: sdram_controller
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
|
||||
Info (12023): Found entity 1: sdram_clk_gen
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(118)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(120)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(122)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(124)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(126)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(128)
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file output_files/output_files/sdram.v
|
||||
Info (12023): Found entity 1: sdram
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128)
|
||||
Error (10228): Verilog HDL error at sdram.v(12): module "sdram" cannot be declared more than once File: /home/benny/work/fpga/spectrum/sdram.v Line: 12
|
||||
Info (10499): HDL info at sdram.v(12): see declaration for object "sdram"
|
||||
Info (12021): Found 0 design units, including 0 entities, in source file sdram.v
|
||||
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
|
||||
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 13 warnings
|
||||
Error: Peak virtual memory: 397 megabytes
|
||||
Error: Processing ended: Sat Apr 2 18:53:05 2022
|
||||
Error: Elapsed time: 00:00:01
|
||||
Error: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg.
|
||||
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(19): object "nRESET" differs only in case from object "nreset" in the same scope
|
||||
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(22): object "CLK" differs only in case from object "clk" in the same scope
|
||||
@@ -0,0 +1,14 @@
|
||||
Analysis & Synthesis Status : Failed - Sat Apr 2 18:53:05 2022
|
||||
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Revision Name : spectrum
|
||||
Top-level Entity Name : spectrum
|
||||
Family : Cyclone IV E
|
||||
Total logic elements : N/A until Partition Merge
|
||||
Total combinational functions : N/A until Partition Merge
|
||||
Dedicated logic registers : N/A until Partition Merge
|
||||
Total registers : N/A until Partition Merge
|
||||
Total pins : N/A until Partition Merge
|
||||
Total virtual pins : N/A until Partition Merge
|
||||
Total memory bits : N/A until Partition Merge
|
||||
Embedded Multiplier 9-bit elements : N/A until Partition Merge
|
||||
Total PLLs : N/A until Partition Merge
|
||||
@@ -0,0 +1,326 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus II help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 1: 3.3V
|
||||
-- Bank 2: 3.3V
|
||||
-- Bank 3: 3.3V
|
||||
-- Bank 4: 3.3V
|
||||
-- Bank 5: 3.3V
|
||||
-- Bank 6: 3.3V
|
||||
-- Bank 7: 3.3V
|
||||
-- Bank 8: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
|
||||
-- or leave it unconnected.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
VCCIO8 : A1 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
|
||||
buzzer_out : A6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
AUD_XCK : A7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : A8 : : : : 8 :
|
||||
GND+ : A9 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
|
||||
LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VGA_B[2] : A12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
|
||||
LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCIO7 : A16 : power : : 3.3V : 7 :
|
||||
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
GND : B2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
|
||||
raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y
|
||||
PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : B8 : : : : 8 :
|
||||
SW[2] : B9 : input : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
|
||||
VGA_B[1] : B11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VGA_VS : B12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
|
||||
GND : B15 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 :
|
||||
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
|
||||
DRAM_WE_N : C2 : output : 3.3-V LVTTL : : 1 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
|
||||
VCCIO8 : C4 : power : : 3.3V : 8 :
|
||||
GND : C5 : gnd : : : :
|
||||
AUD_DACLRCK : C6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VCCIO8 : C7 : power : : 3.3V : 8 :
|
||||
AUD_DACDAT : C8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VGA_G[0] : C9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCIO7 : C10 : power : : 3.3V : 7 :
|
||||
VGA_B[0] : C11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : C12 : gnd : : : :
|
||||
VCCIO7 : C13 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 :
|
||||
LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
|
||||
VCCD_PLL3 : D4 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
|
||||
PS2_CLK : D6 : input : 3.3-V LVTTL : : 8 : Y
|
||||
GND : D7 : gnd : : : :
|
||||
AUD_ADCDAT : D8 : input : 3.3-V LVTTL : : 8 : Y
|
||||
VGA_G[1] : D9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : D10 : gnd : : : :
|
||||
VGA_B[3] : D11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VGA_HS : D12 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VCCD_PLL2 : D13 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 :
|
||||
KEY[1] : E1 : input : 3.3-V LVTTL : : 1 : Y
|
||||
GND : E2 : gnd : : : :
|
||||
VCCIO1 : E3 : power : : 3.3V : 1 :
|
||||
GND : E4 : gnd : : : :
|
||||
GNDA3 : E5 : gnd : : : :
|
||||
AUD_BCLK : E6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
AUD_ADCLRCK : E7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VGA_R[0] : E8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VGA_R[3] : E9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VGA_G[3] : E10 : output : 3.3-V LVTTL : : 7 : Y
|
||||
VGA_G[2] : E11 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GNDA2 : E12 : gnd : : : :
|
||||
GND : E13 : gnd : : : :
|
||||
VCCIO6 : E14 : power : : 3.3V : 6 :
|
||||
GND+ : E15 : : : : 6 :
|
||||
GND+ : E16 : : : : 6 :
|
||||
I2C_SDAT : F1 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
I2C_SCLK : F2 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
LED[5] : F3 : output : 3.3-V LVTTL : : 1 : Y
|
||||
nSTATUS : F4 : : : : 1 :
|
||||
VCCA3 : F5 : power : : 2.5V : :
|
||||
GND : F6 : gnd : : : :
|
||||
VCCINT : F7 : power : : 1.2V : :
|
||||
VGA_R[1] : F8 : output : 3.3-V LVTTL : : 8 : Y
|
||||
VGA_R[2] : F9 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND : F10 : gnd : : : :
|
||||
VCCINT : F11 : power : : 1.2V : :
|
||||
VCCA2 : F12 : power : : 2.5V : :
|
||||
GPIO_1[0] : F13 : output : 3.3-V LVTTL : : 6 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 :
|
||||
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 3.3-V LVTTL : : 6 : N
|
||||
DRAM_DQ[1] : G1 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
DRAM_DQ[0] : G2 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
VCCIO1 : G3 : power : : 3.3V : 1 :
|
||||
GND : G4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
|
||||
VCCINT : G6 : power : : 1.2V : :
|
||||
VCCINT : G7 : power : : 1.2V : :
|
||||
VCCINT : G8 : power : : 1.2V : :
|
||||
VCCINT : G9 : power : : 1.2V : :
|
||||
VCCINT : G10 : power : : 1.2V : :
|
||||
GND : G11 : gnd : : : :
|
||||
MSEL2 : G12 : : : : 6 :
|
||||
GND : G13 : gnd : : : :
|
||||
VCCIO6 : G14 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 :
|
||||
~ALTERA_DCLK~ : H1 : output : 3.3-V LVTTL : : 1 : N
|
||||
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 3.3-V LVTTL : : 1 : N
|
||||
TCK : H3 : input : : : 1 :
|
||||
TDI : H4 : input : : : 1 :
|
||||
nCONFIG : H5 : : : : 1 :
|
||||
VCCINT : H6 : power : : 1.2V : :
|
||||
GND : H7 : gnd : : : :
|
||||
GND : H8 : gnd : : : :
|
||||
GND : H9 : gnd : : : :
|
||||
GND : H10 : gnd : : : :
|
||||
VCCINT : H11 : power : : 1.2V : :
|
||||
MSEL1 : H12 : : : : 6 :
|
||||
MSEL0 : H13 : : : : 6 :
|
||||
CONF_DONE : H14 : : : : 6 :
|
||||
GND : H15 : gnd : : : :
|
||||
GND : H16 : gnd : : : :
|
||||
DRAM_DQ[6] : J1 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_DQ[5] : J2 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
nCE : J3 : : : : 1 :
|
||||
TDO : J4 : output : : : 1 :
|
||||
TMS : J5 : input : : : 1 :
|
||||
VCCINT : J6 : power : : 1.2V : :
|
||||
GND : J7 : gnd : : : :
|
||||
GND : J8 : gnd : : : :
|
||||
GND : J9 : gnd : : : :
|
||||
GND : J10 : gnd : : : :
|
||||
GND : J11 : gnd : : : :
|
||||
VCCINT : J12 : power : : 1.2V : :
|
||||
GPIO_1[32] : J13 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_DQ[4] : K2 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
VCCIO2 : K3 : power : : 3.3V : 2 :
|
||||
GND : K4 : gnd : : : :
|
||||
DRAM_DQ[3] : K5 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
GND : K6 : gnd : : : :
|
||||
VCCINT : K7 : power : : 1.2V : :
|
||||
GND : K8 : gnd : : : :
|
||||
VCCINT : K9 : power : : 1.2V : :
|
||||
VCCINT : K10 : power : : 1.2V : :
|
||||
VCCINT : K11 : power : : 1.2V : :
|
||||
GND : K12 : gnd : : : :
|
||||
GND : K13 : gnd : : : :
|
||||
VCCIO5 : K14 : power : : 3.3V : 5 :
|
||||
GPIO_1[31] : K15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[17] : K16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
DRAM_CAS_N : L1 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_RAS_N : L2 : output : 3.3-V LVTTL : : 2 : Y
|
||||
LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_ADDR[12] : L4 : output : 3.3-V LVTTL : : 2 : Y
|
||||
VCCA1 : L5 : power : : 2.5V : :
|
||||
VCCINT : L6 : power : : 1.2V : :
|
||||
DRAM_CKE : L7 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQ[2] : L8 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
GND : L9 : gnd : : : :
|
||||
GND : L10 : gnd : : : :
|
||||
GND : L11 : gnd : : : :
|
||||
VCCA4 : L12 : power : : 2.5V : :
|
||||
GPIO_1[29] : L13 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[26] : L14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[19] : L15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[16] : L16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
SW[0] : M1 : input : 3.3-V LVTTL : : 2 : Y
|
||||
GND+ : M2 : : : : 2 :
|
||||
VCCIO2 : M3 : power : : 3.3V : 2 :
|
||||
GND : M4 : gnd : : : :
|
||||
GNDA1 : M5 : gnd : : : :
|
||||
DRAM_BA[1] : M6 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_BA[0] : M7 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_ADDR[3] : M8 : output : 3.3-V LVTTL : : 3 : Y
|
||||
VCCINT : M9 : power : : 1.2V : :
|
||||
GPIO_1[28] : M10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCINT : M11 : power : : 1.2V : :
|
||||
GNDA4 : M12 : gnd : : : :
|
||||
GND : M13 : gnd : : : :
|
||||
VCCIO5 : M14 : power : : 3.3V : 5 :
|
||||
SW[3] : M15 : input : 3.3-V LVTTL : : 5 : Y
|
||||
GND+ : M16 : : : : 5 :
|
||||
DRAM_ADDR[11] : N1 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_ADDR[10] : N2 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_DQ[14] : N3 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
VCCD_PLL1 : N4 : power : : 1.2V : :
|
||||
DRAM_ADDR[1] : N5 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_ADDR[2] : N6 : output : 3.3-V LVTTL : : 3 : Y
|
||||
GND : N7 : gnd : : : :
|
||||
DRAM_ADDR[6] : N8 : output : 3.3-V LVTTL : : 3 : Y
|
||||
GPIO_1[14] : N9 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : N10 : gnd : : : :
|
||||
GPIO_1[15] : N11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[12] : N12 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCD_PLL4 : N13 : power : : 1.2V : :
|
||||
GPIO_1[27] : N14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[24] : N15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[23] : N16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
DRAM_ADDR[9] : P1 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_ADDR[0] : P2 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DRAM_DQ[13] : P3 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
VCCIO3 : P4 : power : : 3.3V : 3 :
|
||||
GND : P5 : gnd : : : :
|
||||
DRAM_CS_N : P6 : output : 3.3-V LVTTL : : 3 : Y
|
||||
VCCIO3 : P7 : power : : 3.3V : 3 :
|
||||
DRAM_ADDR[4] : P8 : output : 3.3-V LVTTL : : 3 : Y
|
||||
GPIO_1[13] : P9 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : P10 : power : : 3.3V : 4 :
|
||||
GPIO_1[10] : P11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : P12 : gnd : : : :
|
||||
VCCIO4 : P13 : power : : 3.3V : 4 :
|
||||
GPIO_1[25] : P14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[20] : P15 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[21] : P16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
DRAM_ADDR[8] : R1 : output : 3.3-V LVTTL : : 2 : Y
|
||||
GND : R2 : gnd : : : :
|
||||
DRAM_DQ[11] : R3 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_CLK : R4 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQ[12] : R5 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQM[0] : R6 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQ[7] : R7 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
CLOCK_50 : R8 : input : 3.3-V LVTTL : : 3 : Y
|
||||
GND+ : R9 : : : : 4 :
|
||||
GPIO_1[11] : R10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[9] : R11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[6] : R12 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[4] : R13 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[22] : R14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GND : R15 : gnd : : : :
|
||||
GPIO_1[18] : R16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
VCCIO3 : T1 : power : : 3.3V : 3 :
|
||||
DRAM_DQ[9] : T2 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQ[10] : T3 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQ[8] : T4 : bidir : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_DQM[1] : T5 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_ADDR[7] : T6 : output : 3.3-V LVTTL : : 3 : Y
|
||||
DRAM_ADDR[5] : T7 : output : 3.3-V LVTTL : : 3 : Y
|
||||
SW[1] : T8 : input : 3.3-V LVTTL : : 3 : Y
|
||||
GND+ : T9 : : : : 4 :
|
||||
GPIO_1[8] : T10 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[7] : T11 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[5] : T12 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[3] : T13 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[2] : T14 : output : 3.3-V LVTTL : : 4 : Y
|
||||
GPIO_1[1] : T15 : output : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : T16 : power : : 3.3V : 4 :
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,209 @@
|
||||
------------------------------------------------------------
|
||||
TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
|
||||
Slack : -18.257
|
||||
TNS : -809.639
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -7.550
|
||||
TNS : -292.429
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.737
|
||||
TNS : -40.228
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.914
|
||||
TNS : -2.914
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 2.500
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
|
||||
Slack : -0.026
|
||||
TNS : -0.026
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.342
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.342
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.343
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.358
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -6.225
|
||||
TNS : -455.695
|
||||
|
||||
Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 3.696
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 4.752
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : 9.489
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 19.601
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 20.596
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.503
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -17.443
|
||||
TNS : -768.889
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -6.729
|
||||
TNS : -260.267
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.426
|
||||
TNS : -37.694
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.785
|
||||
TNS : -2.785
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 3.262
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.059
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.298
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.298
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.298
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.312
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -5.745
|
||||
TNS : -420.318
|
||||
|
||||
Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 3.369
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 4.746
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : 9.487
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 19.597
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 20.589
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.491
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -14.929
|
||||
TNS : -634.264
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -4.459
|
||||
TNS : -174.631
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -3.773
|
||||
TNS : -34.191
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.784
|
||||
TNS : -2.784
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 5.613
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : -0.217
|
||||
TNS : -0.350
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.177
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.178
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.178
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.186
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.694
|
||||
TNS : -356.359
|
||||
|
||||
Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 2.518
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 4.784
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : 9.208
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 19.609
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 20.600
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.535
|
||||
TNS : 0.000
|
||||
|
||||
------------------------------------------------------------
|
||||
Reference in New Issue
Block a user