Added kempston, autofire and enable autofire, enable turbo push buttons for GPIO1[32] and GPIO1[33]
This commit is contained in:
+215
-170
@@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for spectrum
|
||||
Sat Apr 2 14:50:45 2022
|
||||
Wed Apr 6 13:57:51 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
@@ -24,29 +24,31 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
16. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
|
||||
17. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated
|
||||
18. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
|
||||
19. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
|
||||
20. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
|
||||
21. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
|
||||
22. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
|
||||
23. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component
|
||||
24. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_
|
||||
25. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_
|
||||
26. altsyncram Parameter Settings by Entity Instance
|
||||
27. altpll Parameter Settings by Entity Instance
|
||||
28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_"
|
||||
29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2"
|
||||
30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
|
||||
31. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
|
||||
32. Port Connectivity Checks: "z80_top_direct_n:z80_"
|
||||
33. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_"
|
||||
34. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_"
|
||||
35. Port Connectivity Checks: "ula:ula_"
|
||||
36. Port Connectivity Checks: "sdram_controller:sdram_"
|
||||
37. Port Connectivity Checks: "ram16:ram0"
|
||||
38. Port Connectivity Checks: "rom0:rom"
|
||||
39. Elapsed Time Per Partition
|
||||
40. Analysis & Synthesis Messages
|
||||
41. Analysis & Synthesis Suppressed Messages
|
||||
19. Parameter Settings for User Entity Instance: debouncer:debounce_turbo
|
||||
20. Parameter Settings for User Entity Instance: debouncer:debounce_autofire
|
||||
21. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
|
||||
22. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
|
||||
23. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
|
||||
24. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
|
||||
25. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component
|
||||
26. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_
|
||||
27. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_
|
||||
28. altsyncram Parameter Settings by Entity Instance
|
||||
29. altpll Parameter Settings by Entity Instance
|
||||
30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_"
|
||||
31. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2"
|
||||
32. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
|
||||
33. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
|
||||
34. Port Connectivity Checks: "z80_top_direct_n:z80_"
|
||||
35. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_"
|
||||
36. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_"
|
||||
37. Port Connectivity Checks: "ula:ula_"
|
||||
38. Port Connectivity Checks: "sdram_controller:sdram_"
|
||||
39. Port Connectivity Checks: "ram16:ram0"
|
||||
40. Port Connectivity Checks: "rom0:rom"
|
||||
41. Elapsed Time Per Partition
|
||||
42. Analysis & Synthesis Messages
|
||||
43. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
@@ -72,16 +74,16 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Apr 2 14:50:45 2022 ;
|
||||
; Analysis & Synthesis Status ; Successful - Wed Apr 6 13:57:51 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Total logic elements ; 2,751 ;
|
||||
; Total combinational functions ; 2,480 ;
|
||||
; Dedicated logic registers ; 649 ;
|
||||
; Total registers ; 649 ;
|
||||
; Total pins ; 114 ;
|
||||
; Total logic elements ; 2,885 ;
|
||||
; Total combinational functions ; 2,614 ;
|
||||
; Dedicated logic registers ; 714 ;
|
||||
; Total registers ; 714 ;
|
||||
; Total pins ; 120 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 524,288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
@@ -749,6 +751,12 @@ File Type : User Wizard-Generated File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram_clk_gen.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : debouncer.v
|
||||
Used in Netlist : yes
|
||||
File Type : User Verilog HDL File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/spectrum/debouncer.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : cpu/toplevel/globals.vh
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Found Unspecified File
|
||||
@@ -955,32 +963,32 @@ Library :
|
||||
+---------------------------------------------+---------------------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+---------------------------------+
|
||||
; Estimated Total logic elements ; 2,751 ;
|
||||
; Estimated Total logic elements ; 2,885 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 2480 ;
|
||||
; Total combinational functions ; 2614 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 1776 ;
|
||||
; -- 3 input functions ; 416 ;
|
||||
; -- <=2 input functions ; 288 ;
|
||||
; -- 4 input functions ; 1835 ;
|
||||
; -- 3 input functions ; 421 ;
|
||||
; -- <=2 input functions ; 358 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 2404 ;
|
||||
; -- arithmetic mode ; 76 ;
|
||||
; -- normal mode ; 2482 ;
|
||||
; -- arithmetic mode ; 132 ;
|
||||
; ; ;
|
||||
; Total registers ; 649 ;
|
||||
; -- Dedicated logic registers ; 649 ;
|
||||
; Total registers ; 714 ;
|
||||
; -- Dedicated logic registers ; 714 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 114 ;
|
||||
; I/O pins ; 120 ;
|
||||
; Total memory bits ; 524288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 2 ;
|
||||
; -- PLLs ; 2 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ;
|
||||
; Maximum fan-out ; 436 ;
|
||||
; Total fan-out ; 12502 ;
|
||||
; Average fan-out ; 3.63 ;
|
||||
; Maximum fan-out ; 455 ;
|
||||
; Total fan-out ; 13090 ;
|
||||
; Average fan-out ; 3.58 ;
|
||||
+---------------------------------------------+---------------------------------+
|
||||
|
||||
|
||||
@@ -988,17 +996,41 @@ Library :
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Compilation Hierarchy Node : |spectrum
|
||||
LC Combinationals : 2480 (108)
|
||||
LC Registers : 649 (0)
|
||||
LC Combinationals : 2614 (124)
|
||||
LC Registers : 714 (21)
|
||||
Memory Bits : 524288
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 114
|
||||
Pins : 120
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |debouncer:debounce_autofire|
|
||||
LC Combinationals : 34 (34)
|
||||
LC Registers : 22 (22)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|debouncer:debounce_autofire
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |debouncer:debounce_turbo|
|
||||
LC Combinationals : 34 (34)
|
||||
LC Registers : 22 (22)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|debouncer:debounce_turbo
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram16:ram0|
|
||||
LC Combinationals : 2 (0)
|
||||
LC Registers : 2 (0)
|
||||
@@ -1048,7 +1080,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram32:ram1|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1060,7 +1092,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1072,7 +1104,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (4)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1108,7 +1140,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_6nb:mux2|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Combinationals : 14 (14)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1156,7 +1188,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |sdram_controller:sdram_|
|
||||
LC Combinationals : 217 (217)
|
||||
LC Combinationals : 226 (226)
|
||||
LC Registers : 57 (57)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1204,7 +1236,7 @@ Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdr
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ula:ula_|
|
||||
LC Combinationals : 418 (4)
|
||||
LC Combinationals : 436 (4)
|
||||
LC Registers : 224 (7)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1240,7 +1272,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |i2s_intf:i2s_intf_|
|
||||
LC Combinationals : 68 (68)
|
||||
LC Combinationals : 67 (67)
|
||||
LC Registers : 42 (42)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1312,7 +1344,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_|
|
||||
LC Combinationals : 148 (148)
|
||||
LC Combinationals : 167 (167)
|
||||
LC Registers : 43 (43)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1324,7 +1356,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |z80_top_direct_n:z80_|
|
||||
LC Combinationals : 1723 (2)
|
||||
LC Combinationals : 1736 (2)
|
||||
LC Registers : 362 (1)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1336,7 +1368,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |address_latch:address_latch_|
|
||||
LC Combinationals : 45 (16)
|
||||
LC Combinationals : 48 (16)
|
||||
LC Registers : 16 (16)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1348,7 +1380,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec|
|
||||
LC Combinationals : 29 (12)
|
||||
LC Combinationals : 32 (15)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1444,7 +1476,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu:alu_|
|
||||
LC Combinationals : 128 (75)
|
||||
LC Combinationals : 130 (76)
|
||||
LC Registers : 20 (20)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1468,7 +1500,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_core:b2v_core|
|
||||
LC Combinationals : 20 (0)
|
||||
LC Combinationals : 21 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1492,7 +1524,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1|
|
||||
LC Combinationals : 5 (5)
|
||||
LC Combinationals : 4 (4)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1516,7 +1548,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3|
|
||||
LC Combinationals : 3 (3)
|
||||
LC Combinationals : 5 (5)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1612,7 +1644,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_flags:alu_flags_|
|
||||
LC Combinationals : 61 (61)
|
||||
LC Combinationals : 59 (59)
|
||||
LC Registers : 10 (10)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1647,18 +1679,6 @@ Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |control_pins_n:control_pins_|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_pins:data_pins_|
|
||||
LC Combinationals : 9 (9)
|
||||
LC Registers : 8 (8)
|
||||
@@ -1671,20 +1691,8 @@ Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_switch:sw2_|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_switch_mask:sw1_|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Combinationals : 5 (5)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1696,7 +1704,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |decode_state:decode_state_|
|
||||
LC Combinationals : 11 (11)
|
||||
LC Combinationals : 12 (12)
|
||||
LC Registers : 6 (6)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1708,7 +1716,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |execute:execute_|
|
||||
LC Combinationals : 926 (926)
|
||||
LC Combinationals : 934 (934)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1720,7 +1728,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |interrupts:interrupts_|
|
||||
LC Combinationals : 10 (10)
|
||||
LC Combinationals : 11 (11)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1768,7 +1776,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |pla_decode:pla_decode_|
|
||||
LC Combinationals : 74 (74)
|
||||
LC Combinationals : 71 (71)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1780,7 +1788,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_deco
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_control:reg_control_|
|
||||
LC Combinationals : 30 (30)
|
||||
LC Combinationals : 29 (29)
|
||||
LC Registers : 4 (4)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1792,7 +1800,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_file:reg_file_|
|
||||
LC Combinationals : 281 (270)
|
||||
LC Combinationals : 286 (277)
|
||||
LC Registers : 224 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1828,7 +1836,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi|
|
||||
LC Combinationals : 8 (8)
|
||||
LC Combinationals : 6 (6)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1900,7 +1908,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_hi|
|
||||
LC Combinationals : 0 (0)
|
||||
LC Combinationals : 2 (2)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1984,7 +1992,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Combinationals : 0 (0)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -2128,7 +2136,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo|
|
||||
LC Combinationals : 2 (2)
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -2365,12 +2373,12 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 649 ;
|
||||
; Number of registers using Synchronous Clear ; 13 ;
|
||||
; Number of registers using Synchronous Load ; 34 ;
|
||||
; Total registers ; 714 ;
|
||||
; Number of registers using Synchronous Clear ; 55 ;
|
||||
; Number of registers using Synchronous Load ; 35 ;
|
||||
; Number of registers using Asynchronous Clear ; 221 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 464 ;
|
||||
; Number of registers using Clock Enable ; 481 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@@ -2380,16 +2388,16 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
+----------------------------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------------------------+---------+
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 150 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 3 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 144 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 5 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[4] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] ; 2 ;
|
||||
@@ -2397,22 +2405,22 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ;
|
||||
@@ -2425,24 +2433,23 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 64 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ;
|
||||
; z80_top_direct_n:z80_|fpga_reset ; 2 ;
|
||||
; sdram_controller:sdram_|r.init_counter[3] ; 3 ;
|
||||
; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ;
|
||||
; ula:ula_|i2c_loader:i2c_loader_|scl_out ; 2 ;
|
||||
; ula:ula_|i2c_loader:i2c_loader_|sda_out ; 3 ;
|
||||
; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ;
|
||||
; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ;
|
||||
; Total number of inverted registers = 62 ; ;
|
||||
; Total number of inverted registers = 61 ; ;
|
||||
+----------------------------------------------------------+---------+
|
||||
|
||||
|
||||
@@ -2455,7 +2462,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 10 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[5]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[8]
|
||||
|
||||
Multiplexer Inputs : 3:1
|
||||
Bus Width : 4 bits
|
||||
@@ -2463,7 +2470,7 @@ Baseline Area : 8 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 4 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0]
|
||||
|
||||
Multiplexer Inputs : 4:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2479,7 +2486,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 10 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[3]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[8]
|
||||
|
||||
Multiplexer Inputs : 6:1
|
||||
Bus Width : 5 bits
|
||||
@@ -2487,7 +2494,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 5 LEs
|
||||
Saving if Restructured : 15 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
|
||||
|
||||
Multiplexer Inputs : 5:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2503,7 +2510,7 @@ Baseline Area : 42 LEs
|
||||
Area if Restructured : 14 LEs
|
||||
Saving if Restructured : 28 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
|
||||
|
||||
Multiplexer Inputs : 5:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2511,7 +2518,7 @@ Baseline Area : 9 LEs
|
||||
Area if Restructured : 3 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
|
||||
|
||||
Multiplexer Inputs : 10:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2519,7 +2526,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 2 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[11]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[12]
|
||||
|
||||
Multiplexer Inputs : 10:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2527,7 +2534,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 2 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[8]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[9]
|
||||
|
||||
Multiplexer Inputs : 32:1
|
||||
Bus Width : 5 bits
|
||||
@@ -2535,7 +2542,7 @@ Baseline Area : 105 LEs
|
||||
Area if Restructured : 0 LEs
|
||||
Saving if Restructured : 105 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[1]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[2]
|
||||
|
||||
Multiplexer Inputs : 8:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2543,7 +2550,7 @@ Baseline Area : 10 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
|
||||
|
||||
Multiplexer Inputs : 32:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2559,7 +2566,7 @@ Baseline Area : 80 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 76 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[8]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[9]
|
||||
|
||||
Multiplexer Inputs : 31:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2575,7 +2582,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 8 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2583,7 +2590,7 @@ Baseline Area : 18 LEs
|
||||
Area if Restructured : 3 LEs
|
||||
Saving if Restructured : 15 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[2]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[0]
|
||||
|
||||
Multiplexer Inputs : 27:1
|
||||
Bus Width : 4 bits
|
||||
@@ -2591,7 +2598,7 @@ Baseline Area : 72 LEs
|
||||
Area if Restructured : 52 LEs
|
||||
Saving if Restructured : 20 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
|
||||
|
||||
Multiplexer Inputs : 3:1
|
||||
Bus Width : 16 bits
|
||||
@@ -2623,15 +2630,7 @@ Baseline Area : 9 LEs
|
||||
Area if Restructured : 6 LEs
|
||||
Saving if Restructured : 3 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[2]
|
||||
|
||||
Multiplexer Inputs : 6:1
|
||||
Bus Width : 2 bits
|
||||
Baseline Area : 8 LEs
|
||||
Area if Restructured : 6 LEs
|
||||
Saving if Restructured : 2 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Mux0
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[1]
|
||||
|
||||
Multiplexer Inputs : 4:1
|
||||
Bus Width : 8 bits
|
||||
@@ -2641,13 +2640,21 @@ Saving if Restructured : 8 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|Mux74
|
||||
|
||||
Multiplexer Inputs : 8:1
|
||||
Bus Width : 6 bits
|
||||
Baseline Area : 30 LEs
|
||||
Area if Restructured : 24 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Multiplexer Inputs : 7:1
|
||||
Bus Width : 2 bits
|
||||
Baseline Area : 8 LEs
|
||||
Area if Restructured : 8 LEs
|
||||
Saving if Restructured : 0 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Selector0
|
||||
Example Multiplexer Output : |spectrum|Selector4
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 5 bits
|
||||
Baseline Area : 30 LEs
|
||||
Area if Restructured : 20 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Selector14
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2701,6 +2708,28 @@ To : -
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: debouncer:debounce_turbo ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : c_DEBOUNCE_LIMIT
|
||||
Value : 1100000
|
||||
Type : Signed Integer
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: debouncer:debounce_autofire ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : c_DEBOUNCE_LIMIT
|
||||
Value : 1100000
|
||||
Type : Signed Integer
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
@@ -6580,7 +6609,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:11 ;
|
||||
; Top ; 00:00:12 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
@@ -6590,7 +6619,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 14:50:31 2022
|
||||
Info: Processing started: Wed Apr 6 13:57:36 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
|
||||
@@ -6708,10 +6737,31 @@ Info (12021): Found 2 design units, including 1 entities, in source file sdram.v
|
||||
Info (12023): Found entity 1: sdram_controller
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
|
||||
Info (12023): Found entity 1: sdram_clk_gen
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128)
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram.v
|
||||
Info (12023): Found entity 1: sdram
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_ctrl.v
|
||||
Info (12023): Found entity 1: SDRAM_ctrl
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_controller.v
|
||||
Info (12023): Found entity 1: sdram_controller_new
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file pll_sdram.v
|
||||
Info (12023): Found entity 1: pll_sdram
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file debouncer.v
|
||||
Info (12023): Found entity 1: debouncer
|
||||
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
|
||||
Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver
|
||||
Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver
|
||||
Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(114): object "is_io_read_requested" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(115): object "is_io_write_requested" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(118): object "is_rom_address" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(133): object "kempston_last_fire_state" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(231): object "sdram_write_request" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.sv(141): truncated value with size 32 to match size of target (18)
|
||||
Info (12128): Elaborating entity "debouncer" for hierarchy "debouncer:debounce_turbo"
|
||||
Warning (10230): Verilog HDL assignment warning at debouncer.v(13): truncated value with size 32 to match size of target (21)
|
||||
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
|
||||
@@ -7006,10 +7056,10 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]" to the node "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "RamWE" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "sdram_read_request" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nWR" to the node "RamWE" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal1" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal1" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal5" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal5" into an OR gate
|
||||
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[0]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[0]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[7]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[7]" into an OR gate
|
||||
@@ -7086,35 +7136,30 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Info (13000): Registers with preset signals will power-up high
|
||||
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "LED[1]" is stuck at GND
|
||||
Warning (13410): Pin "LED[4]" is stuck at GND
|
||||
Warning (13410): Pin "LED[5]" is stuck at GND
|
||||
Warning (13410): Pin "LED[6]" is stuck at GND
|
||||
Warning (13410): Pin "LED[7]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_1[24]" is stuck at VCC
|
||||
Warning (13410): Pin "GPIO_1[32]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_1[33]" is stuck at GND
|
||||
Warning (13410): Pin "DRAM_CKE" is stuck at VCC
|
||||
Warning (13410): Pin "DRAM_CS_N" is stuck at GND
|
||||
Warning (13410): Pin "kempston_gnd" is stuck at GND
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
|
||||
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||||
Warning (21074): Design contains 3 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "SW[0]"
|
||||
Warning (15610): No output dependent on input pin "SW[2]"
|
||||
Warning (15610): No output dependent on input pin "SW[3]"
|
||||
Info (21057): Implemented 3006 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 11 input pins
|
||||
Info (21059): Implemented 85 output pins
|
||||
Info (21057): Implemented 3146 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 18 input pins
|
||||
Info (21059): Implemented 84 output pins
|
||||
Info (21060): Implemented 18 bidirectional pins
|
||||
Info (21061): Implemented 2826 logic cells
|
||||
Info (21061): Implemented 2960 logic cells
|
||||
Info (21064): Implemented 64 RAM segments
|
||||
Info (21065): Implemented 2 PLLs
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 117 warnings
|
||||
Info: Peak virtual memory: 446 megabytes
|
||||
Info: Processing ended: Sat Apr 2 14:50:45 2022
|
||||
Info: Elapsed time: 00:00:14
|
||||
Info: Processing ended: Wed Apr 6 13:57:51 2022
|
||||
Info: Elapsed time: 00:00:15
|
||||
Info: Total CPU time (on all processors): 00:00:15
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user