Added kempston, autofire and enable autofire, enable turbo push buttons for GPIO1[32] and GPIO1[33]
This commit is contained in:
@@ -1,36 +0,0 @@
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ADDRESS_REG_B=CLOCK1
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CLOCK_ENABLE_INPUT_A=BYPASS
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CLOCK_ENABLE_INPUT_B=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
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CLOCK_ENABLE_OUTPUT_B=BYPASS
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INDATA_REG_B=CLOCK1
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INTENDED_DEVICE_FAMILY="Cyclone IV E"
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LPM_TYPE=altsyncram
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NUMWORDS_A=16384
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NUMWORDS_B=16384
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OPERATION_MODE=BIDIR_DUAL_PORT
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OUTDATA_ACLR_A=NONE
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OUTDATA_ACLR_B=NONE
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OUTDATA_REG_A=CLOCK0
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OUTDATA_REG_B=CLOCK1
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
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READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
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WIDTHAD_A=14
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WIDTHAD_B=14
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WIDTH_A=8
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WIDTH_B=8
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WIDTH_BYTEENA_A=1
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WIDTH_BYTEENA_B=1
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WRCONTROL_WRADDRESS_REG_B=CLOCK1
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DEVICE_FAMILY="Cyclone IV E"
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address_a
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address_b
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clock0
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clock1
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data_a
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data_b
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wren_a
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wren_b
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q_a
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q_b
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@@ -1,32 +0,0 @@
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Quartus II generated Memory Initialization File (.mif)
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WIDTH=8;
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DEPTH=8;
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ADDRESS_RADIX=UNS;
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DATA_RADIX=UNS;
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CONTENT BEGIN
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0 : 129;
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1 : 66;
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2 : 36;
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3 : 24;
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4 : 36;
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5 : 66;
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6 : 129;
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7 : 255;
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END;
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@@ -0,0 +1,738 @@
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------------------------------------------------------
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-- FSM for a SDRAM controller
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--
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-- Version 0.1 - Ready to simulate
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--
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-- Author: Mike Field (hamster@snap.net.nz)
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--
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-- Feel free to use it however you would like, but
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-- just drop me an email to say thanks.
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-------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- library unisim;
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-- use unisim.vcomponents.all;
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entity sdram_controller2 is
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generic (
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HIGH_BIT: integer := 24;
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MHZ: integer := 96;
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REFRESH_CYCLES: integer := 4096;
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ADDRESS_BITS: integer := 12
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);
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PORT (
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clock_100: in std_logic;
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clock_100_delayed_3ns: in std_logic;
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rst: in std_logic;
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-- Signals to/from the SDRAM chip
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DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
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DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
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DRAM_CAS_N : OUT STD_LOGIC;
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DRAM_CKE : OUT STD_LOGIC;
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DRAM_CLK : OUT STD_LOGIC;
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DRAM_CS_N : OUT STD_LOGIC;
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DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
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DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
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DRAM_RAS_N : OUT STD_LOGIC;
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DRAM_WE_N : OUT STD_LOGIC;
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pending: out std_logic;
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--- Inputs from rest of the system
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address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
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req_read : IN STD_LOGIC;
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req_write : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
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data_out_valid : OUT STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR (31 downto 0);
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data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
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);
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end entity;
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architecture rtl of sdram_controller2 is
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type reg is record
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address : std_logic_vector(ADDRESS_BITS-1 downto 0);
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bank : std_logic_vector( 1 downto 0);
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init_counter : std_logic_vector(14 downto 0);
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rf_counter : integer;
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rf_pending : std_logic;
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rd_pending : std_logic;
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wr_pending : std_logic;
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act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
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act_ba : std_logic_vector(1 downto 0);
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data_out_low : std_logic_vector(15 downto 0);
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req_addr_q : std_logic_vector(HIGH_BIT downto 2);
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req_data_write: std_logic_vector(31 downto 0);
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req_mask : std_logic_vector(3 downto 0);
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data_out_valid: std_logic;
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dq_masks : std_logic_vector(1 downto 0);
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tristate : std_logic;
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end record;
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signal r : reg;
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signal n : reg;
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signal rstate : std_logic_vector(8 downto 0);
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signal nstate : std_logic_vector(8 downto 0);
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signal rdata_write : std_logic_vector(15 downto 0);
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signal ndata_write : std_logic_vector(15 downto 0);
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-- Vectors for each SDRAM 'command'
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--- CS_N, RAS_N, CAS_N, WE_N
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constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
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constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
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constant cmd_write : std_logic_vector(3 downto 0) := "0100";
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constant cmd_act : std_logic_vector(3 downto 0) := "0011";
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constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
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constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
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constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
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-- State assignments
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constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
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constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
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constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
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constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
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constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
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constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
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constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
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constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
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constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
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constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
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constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
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constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
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constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
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constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
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constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
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constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
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constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
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constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
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constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
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constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
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constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
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constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
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constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
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constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
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constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
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constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
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constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
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constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
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constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
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constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
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constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
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constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
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constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
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constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
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constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
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constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
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constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
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constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
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constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
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constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
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constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
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constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
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constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
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constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
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constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
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constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
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constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
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constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
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constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
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constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
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constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
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constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
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constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
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constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
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constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
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constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
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constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
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constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
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constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
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constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
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constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
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constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
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constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
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signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
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signal addr_bank: std_logic_vector(1 downto 0);
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constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
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signal addr_col : std_logic_vector(7 downto 0);
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signal captured : std_logic_vector(15 downto 0);
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signal busy: std_logic;
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constant tOPD: time := 2.1 ns;
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constant tHZ: time := 8 ns;
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signal dram_dq_dly : std_logic_vector(15 downto 0);
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-- Debug only
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signal debug_cmd: std_logic_vector(3 downto 0);
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signal not_clock_100_delayed_3ns: std_logic;
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constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
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attribute IOB: string;
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signal i_DRAM_CS_N: std_logic;
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attribute IOB of i_DRAM_CS_N: signal is "true";
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signal i_DRAM_RAS_N: std_logic;
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attribute IOB of i_DRAM_RAS_N: signal is "true";
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signal i_DRAM_CAS_N: std_logic;
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attribute IOB of i_DRAM_CAS_N: signal is "true";
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signal i_DRAM_WE_N: std_logic;
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attribute IOB of i_DRAM_WE_N: signal is "true";
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signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
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attribute IOB of i_DRAM_ADDR: signal is "true";
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signal i_DRAM_BA: std_logic_vector(1 downto 0);
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attribute IOB of i_DRAM_BA: signal is "true";
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signal i_DRAM_DQM: std_logic_vector(1 downto 0);
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attribute IOB of i_DRAM_DQM: signal is "true";
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attribute IOB of rdata_write: signal is "true";
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attribute IOB of captured: signal is "true";
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signal i_DRAM_CLK: std_logic;
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attribute fsm_encoding: string;
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attribute fsm_encoding of nstate: signal is "user";
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attribute fsm_encoding of rstate: signal is "user";
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begin
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debug_cmd <= rstate(3 downto 0);
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-- Addressing is in 32 bit words - twice that of the DRAM width,
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-- so each burst of four access two system words.
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--addr_row <= address(23 downto 11);
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--addr_bank <= address(10 downto 9);
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process(r.req_addr_q)
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begin
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addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
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-- (24-2) downto (24-2 - 2 - 13 - 1)
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-- 22 downto 6
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addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
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||||
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
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addr_col <= (others => '0');
|
||||
|
||||
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
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||||
r.req_addr_q(8 downto 2) & "0";
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||||
end process;
|
||||
|
||||
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
|
||||
|
||||
clock: ODDR2
|
||||
generic map (
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||||
DDR_ALIGNMENT => "NONE",
|
||||
INIT => '0',
|
||||
SRTYPE => "ASYNC")
|
||||
port map (
|
||||
D0 => '1',
|
||||
D1 => '0',
|
||||
Q => i_DRAM_CLK,
|
||||
C0 => clock_100_delayed_3ns,
|
||||
C1 => not_clock_100_delayed_3ns,
|
||||
CE => '1',
|
||||
R => '0',
|
||||
S => '0'
|
||||
);
|
||||
|
||||
DRAM_CKE <= '1';
|
||||
|
||||
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
|
||||
|
||||
i_DRAM_CS_N <= transport rstate(3) after tOPD;
|
||||
DRAM_CS_N <= i_DRAM_CS_N;
|
||||
|
||||
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
|
||||
DRAM_RAS_N <= i_DRAM_RAS_N;
|
||||
|
||||
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
|
||||
DRAM_CAS_N <= i_DRAM_CAS_N;
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||||
|
||||
i_DRAM_WE_N <= transport rstate(0) after tOPD;
|
||||
DRAM_WE_N <= i_DRAM_WE_N;
|
||||
|
||||
i_DRAM_ADDR <= transport r.address after tOPD;
|
||||
DRAM_ADDR <= i_DRAM_ADDR;
|
||||
|
||||
i_DRAM_BA <= transport r.bank after tOPD;
|
||||
DRAM_BA <= i_DRAM_BA;
|
||||
|
||||
i_DRAM_DQM <= transport r.dq_masks after tOPD;
|
||||
DRAM_DQM <= i_DRAM_DQM;
|
||||
|
||||
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
|
||||
data_out_valid <= r.data_out_valid;
|
||||
|
||||
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
|
||||
|
||||
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
|
||||
|
||||
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
|
||||
begin
|
||||
-- copy the existing values
|
||||
n <= r;
|
||||
nstate <= rstate;
|
||||
ndata_write <= rdata_write;
|
||||
|
||||
if req_read = '1' then
|
||||
n.rd_pending <= '1';
|
||||
if r.rd_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if req_write = '1' then
|
||||
n.wr_pending <= '1';
|
||||
if r.wr_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
-- Queue data here
|
||||
n.req_data_write <= data_in;
|
||||
n.req_mask <= data_mask;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
n.dq_masks <= "11";
|
||||
|
||||
-- first off, do we need to perform a refresh cycle ASAP?
|
||||
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
|
||||
n.rf_counter <= 0;
|
||||
n.rf_pending <= '1';
|
||||
else
|
||||
-- only start looking for refreshes outside of the initialisation state.
|
||||
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
|
||||
n.rf_counter <= r.rf_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Set the data bus into HIZ, high and low bytes masked
|
||||
--DRAM_DQ <= (others => 'Z');
|
||||
n.tristate <= '0';
|
||||
|
||||
n.init_counter <= r.init_counter-1;
|
||||
|
||||
--ndata_write <= (others => DontCareValue);
|
||||
|
||||
n.data_out_valid <= '0'; -- alvie- here, no ?
|
||||
|
||||
-- Process the FSM
|
||||
case rstate(8 downto 4) is
|
||||
when s_init_nop_id => --s_init_nop(8 downto 4) =>
|
||||
nstate <= s_init_nop;
|
||||
n.address <= (others => '0');
|
||||
n.bank <= (others => '0');
|
||||
n.act_ba <= (others => '0');
|
||||
n.rf_counter <= 0;
|
||||
-- n.data_out_valid <= '1'; -- alvie- not here
|
||||
|
||||
-- T-130, precharge all banks.
|
||||
if r.init_counter = "000000010000010" then
|
||||
nstate <= s_init_pre;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
|
||||
|
||||
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
|
||||
nstate <= s_init_ref;
|
||||
end if;
|
||||
|
||||
-- T-3, the load mode register
|
||||
if r.init_counter = 3 then
|
||||
nstate <= s_init_mrs;
|
||||
-- Mode register is as follows:
|
||||
-- resvd wr_b OpMd CAS=3 Seq bust=1
|
||||
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
|
||||
-- resvd
|
||||
n.bank <= "00";
|
||||
end if;
|
||||
|
||||
-- T-1 The switch to the FSM (first command will be a NOP
|
||||
if r.init_counter = 1 then
|
||||
nstate <= s_idle;
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Idle section
|
||||
------------------------------
|
||||
when s_idle_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
-- do we have to activate a row?
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
-- refreshes take priority over everything
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
n.rf_pending <= '0';
|
||||
end if;
|
||||
------------------------------
|
||||
-- Row activation
|
||||
-- s_ra2 is also the "idle with active row" state and provides
|
||||
-- a resting point between operations on the same row
|
||||
------------------------------
|
||||
when s_ra0_id =>
|
||||
nstate <= s_ra1;
|
||||
when s_ra1_id =>
|
||||
nstate <= s_ra2;
|
||||
|
||||
|
||||
when s_ra2_id=>
|
||||
-- we can stay in this state until we have something to do
|
||||
nstate <= s_ra2;
|
||||
n.tristate<='0';
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
else
|
||||
|
||||
-- If there is a read pending, deactivate the row
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- unless we have a read to perform on the same row? do that instead
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_rd0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks <= "00";
|
||||
n.rd_pending <= '0';
|
||||
--n.tristate<='1';
|
||||
end if;
|
||||
|
||||
-- unless we have a write on the same row? writes take priroty over reads
|
||||
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_wr0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
ndata_write <= r.req_data_write(31 downto 16);
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= not r.req_mask(3 downto 2);
|
||||
n.wr_pending <= '0';
|
||||
--n.tristate <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
end if;
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending;
|
||||
-- n.wr_pending <= r.wr_pending;
|
||||
--n.tristate <= '0';
|
||||
--end if;
|
||||
|
||||
------------------------------------------------------
|
||||
-- Deactivate the current row and return to idle state
|
||||
------------------------------------------------------
|
||||
when s_dr0_id =>
|
||||
nstate <= s_dr1;
|
||||
when s_dr1_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
------------------------------
|
||||
-- The Refresh section
|
||||
------------------------------
|
||||
when s_rf0_id =>
|
||||
nstate <= s_rf1;
|
||||
when s_rf1_id =>
|
||||
nstate <= s_rf2;
|
||||
when s_rf2_id =>
|
||||
nstate <= s_rf3;
|
||||
when s_rf3_id =>
|
||||
nstate <= s_rf4;
|
||||
when s_rf4_id =>
|
||||
nstate <= s_rf5;
|
||||
when s_rf5_id =>
|
||||
nstate <= s_idle;
|
||||
------------------------------
|
||||
-- The Write section
|
||||
------------------------------
|
||||
when s_wr0_id =>
|
||||
nstate <= s_wr3;
|
||||
n.bank <= addr_bank;
|
||||
n.address(0) <= '1';
|
||||
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.dq_masks<= not r.req_mask(1 downto 0);
|
||||
n.tristate <= '0';
|
||||
|
||||
when s_wr1_id => null;
|
||||
when s_wr2_id =>
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
|
||||
|
||||
when s_wr3_id =>
|
||||
-- Default to the idle+row active state
|
||||
nstate <= s_ra2;
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.data_out_valid<='1'; -- alvie- ack write
|
||||
n.tristate <= '0';
|
||||
n.dq_masks<= "11";
|
||||
|
||||
-- If there is a read or write then deactivate the row
|
||||
--if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
-- But if there is a read pending in the same row, do that
|
||||
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_rd0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
-- --n.act_ba <= addr_bank;
|
||||
-- n.dq_masks <= "00";
|
||||
-- n.rd_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- unless there is a write pending in the same row, do that
|
||||
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_wr0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
--n.act_ba <= addr_bank;
|
||||
-- n.dq_masks<= "00";
|
||||
-- n.wr_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- But always try and refresh if one is pending!
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_wr2; --dr0;
|
||||
--n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Read section
|
||||
------------------------------
|
||||
when s_rd0_id => -- 10001
|
||||
nstate <= s_rd1;
|
||||
n.tristate<='1';
|
||||
n.dq_masks <= "00";
|
||||
n.address(0)<='1';
|
||||
|
||||
when s_rd1_id => -- 10010
|
||||
nstate <= s_rd2;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
|
||||
nstate <= s_rd3; -- Another request came, and we can pipeline -
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
end if;
|
||||
|
||||
when s_rd2_id => -- 10011
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
when s_rd3_id => -- 10100
|
||||
|
||||
nstate <= s_rd4;
|
||||
n.dq_masks <= "00";
|
||||
n.address(0) <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
-- Data is still not ready...
|
||||
|
||||
when s_rd4_id => -- 10101
|
||||
nstate <= s_rd5;
|
||||
n.dq_masks <= "00";
|
||||
--n.address(0)<='1';
|
||||
n.tristate<='1';
|
||||
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
nstate <= s_rd5; -- Another request came, and we can pipeline -
|
||||
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
else
|
||||
nstate <= s_rd6; -- NOTE: not correct
|
||||
end if;
|
||||
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending; -- Keep request
|
||||
--end if;
|
||||
|
||||
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
|
||||
|
||||
when s_rd5_id =>
|
||||
-- If a refresh is pending then always deactivate the row
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
n.address(0) <= '1';
|
||||
nstate <= s_rd4; -- Another request came, and we can pipeline -
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd6_id =>
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks<= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd7_id =>
|
||||
nstate <= s_ra2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd8_id => null;
|
||||
|
||||
when s_rd9_id => null;
|
||||
|
||||
-- The Deactivate row during read section
|
||||
------------------------------
|
||||
when s_drdr0_id =>
|
||||
nstate <= s_drdr1;
|
||||
when s_drdr1_id =>
|
||||
nstate <= s_drdr2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
when s_drdr2_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
end if;
|
||||
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
nstate <= s_init_nop;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
--- The clock driven logic
|
||||
process (clock_100, n)
|
||||
begin
|
||||
if clock_100'event and clock_100 = '1' then
|
||||
if rst='1' then
|
||||
rstate <= (others => '0');
|
||||
r.address <= (others => '0');
|
||||
r.bank <= (others => '0');
|
||||
r.init_counter <= "100000000000000";
|
||||
-- synopsys translate_off
|
||||
r.init_counter <= "000000100000000";
|
||||
-- synopsys translate_on
|
||||
r.rf_counter <= 0;
|
||||
r.rf_pending <= '0';
|
||||
r.rd_pending <= '0';
|
||||
r.wr_pending <= '0';
|
||||
r.act_row <= (others => '0');
|
||||
r.data_out_low <= (others => '0');
|
||||
r.data_out_valid <= '0';
|
||||
r.dq_masks <= "11";
|
||||
r.tristate<='1';
|
||||
else
|
||||
r <= n;
|
||||
rstate <= nstate;
|
||||
rdata_write <= ndata_write;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dram_dq_dly <= transport dram_dq after 1.9 ns;
|
||||
|
||||
-- process (clock_100_delayed_3ns, dram_dq_dly)
|
||||
-- begin
|
||||
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
|
||||
-- captured <= dram_dq_dly;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process (clock_100)
|
||||
begin
|
||||
if falling_edge(clock_100) then
|
||||
captured <= dram_dq_dly;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,738 @@
|
||||
------------------------------------------------------
|
||||
-- FSM for a SDRAM controller
|
||||
--
|
||||
-- Version 0.1 - Ready to simulate
|
||||
--
|
||||
-- Author: Mike Field (hamster@snap.net.nz)
|
||||
--
|
||||
-- Feel free to use it however you would like, but
|
||||
-- just drop me an email to say thanks.
|
||||
-------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity sdram_controller is
|
||||
generic (
|
||||
HIGH_BIT: integer := 24;
|
||||
MHZ: integer := 96;
|
||||
REFRESH_CYCLES: integer := 4096;
|
||||
ADDRESS_BITS: integer := 12
|
||||
);
|
||||
PORT (
|
||||
clock_100: in std_logic;
|
||||
clock_100_delayed_3ns: in std_logic;
|
||||
rst: in std_logic;
|
||||
|
||||
-- Signals to/from the SDRAM chip
|
||||
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
|
||||
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
|
||||
DRAM_CAS_N : OUT STD_LOGIC;
|
||||
DRAM_CKE : OUT STD_LOGIC;
|
||||
DRAM_CLK : OUT STD_LOGIC;
|
||||
DRAM_CS_N : OUT STD_LOGIC;
|
||||
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
|
||||
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
|
||||
DRAM_RAS_N : OUT STD_LOGIC;
|
||||
DRAM_WE_N : OUT STD_LOGIC;
|
||||
|
||||
pending: out std_logic;
|
||||
|
||||
--- Inputs from rest of the system
|
||||
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
|
||||
req_read : IN STD_LOGIC;
|
||||
req_write : IN STD_LOGIC;
|
||||
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
|
||||
data_out_valid : OUT STD_LOGIC;
|
||||
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
|
||||
data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
||||
architecture rtl of sdram_controller is
|
||||
|
||||
type reg is record
|
||||
address : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
bank : std_logic_vector( 1 downto 0);
|
||||
init_counter : std_logic_vector(14 downto 0);
|
||||
rf_counter : integer;
|
||||
rf_pending : std_logic;
|
||||
rd_pending : std_logic;
|
||||
wr_pending : std_logic;
|
||||
act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
act_ba : std_logic_vector(1 downto 0);
|
||||
data_out_low : std_logic_vector(15 downto 0);
|
||||
req_addr_q : std_logic_vector(HIGH_BIT downto 2);
|
||||
req_data_write: std_logic_vector(31 downto 0);
|
||||
req_mask : std_logic_vector(3 downto 0);
|
||||
data_out_valid: std_logic;
|
||||
dq_masks : std_logic_vector(1 downto 0);
|
||||
tristate : std_logic;
|
||||
end record;
|
||||
|
||||
signal r : reg;
|
||||
signal n : reg;
|
||||
|
||||
signal rstate : std_logic_vector(8 downto 0);
|
||||
signal nstate : std_logic_vector(8 downto 0);
|
||||
signal rdata_write : std_logic_vector(15 downto 0);
|
||||
signal ndata_write : std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
-- Vectors for each SDRAM 'command'
|
||||
--- CS_N, RAS_N, CAS_N, WE_N
|
||||
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
|
||||
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
|
||||
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
|
||||
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
|
||||
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
|
||||
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
|
||||
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
|
||||
|
||||
-- State assignments
|
||||
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
|
||||
|
||||
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
|
||||
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
|
||||
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
|
||||
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
|
||||
|
||||
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
|
||||
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
|
||||
|
||||
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
|
||||
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
|
||||
|
||||
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
|
||||
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
|
||||
|
||||
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
|
||||
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
|
||||
|
||||
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
|
||||
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
|
||||
|
||||
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
|
||||
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
|
||||
|
||||
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
|
||||
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
|
||||
|
||||
|
||||
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
|
||||
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
|
||||
|
||||
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
|
||||
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
|
||||
|
||||
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
|
||||
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
|
||||
|
||||
|
||||
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
|
||||
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
|
||||
|
||||
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
|
||||
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
|
||||
|
||||
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
|
||||
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
|
||||
|
||||
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
|
||||
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
|
||||
|
||||
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
|
||||
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
|
||||
|
||||
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
|
||||
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
|
||||
|
||||
|
||||
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
|
||||
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
|
||||
|
||||
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
|
||||
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
|
||||
|
||||
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
|
||||
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
|
||||
|
||||
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
|
||||
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
|
||||
|
||||
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
|
||||
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
|
||||
|
||||
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
|
||||
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
|
||||
|
||||
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
|
||||
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
|
||||
|
||||
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
|
||||
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
|
||||
|
||||
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
|
||||
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
|
||||
|
||||
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
|
||||
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
|
||||
|
||||
|
||||
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
|
||||
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
|
||||
|
||||
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
|
||||
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
|
||||
|
||||
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
|
||||
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
|
||||
|
||||
signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
signal addr_bank: std_logic_vector(1 downto 0);
|
||||
|
||||
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
|
||||
|
||||
|
||||
signal addr_col : std_logic_vector(7 downto 0);
|
||||
signal captured : std_logic_vector(15 downto 0);
|
||||
signal busy: std_logic;
|
||||
|
||||
constant tOPD: time := 2.1 ns;
|
||||
constant tHZ: time := 8 ns;
|
||||
|
||||
signal dram_dq_dly : std_logic_vector(15 downto 0);
|
||||
|
||||
-- Debug only
|
||||
signal debug_cmd: std_logic_vector(3 downto 0);
|
||||
|
||||
signal not_clock_100_delayed_3ns: std_logic;
|
||||
|
||||
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
|
||||
|
||||
attribute IOB: string;
|
||||
|
||||
signal i_DRAM_CS_N: std_logic;
|
||||
attribute IOB of i_DRAM_CS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_RAS_N: std_logic;
|
||||
attribute IOB of i_DRAM_RAS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_CAS_N: std_logic;
|
||||
attribute IOB of i_DRAM_CAS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_WE_N: std_logic;
|
||||
attribute IOB of i_DRAM_WE_N: signal is "true";
|
||||
|
||||
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
attribute IOB of i_DRAM_ADDR: signal is "true";
|
||||
|
||||
signal i_DRAM_BA: std_logic_vector(1 downto 0);
|
||||
attribute IOB of i_DRAM_BA: signal is "true";
|
||||
|
||||
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
|
||||
attribute IOB of i_DRAM_DQM: signal is "true";
|
||||
|
||||
attribute IOB of rdata_write: signal is "true";
|
||||
attribute IOB of captured: signal is "true";
|
||||
|
||||
signal i_DRAM_CLK: std_logic;
|
||||
|
||||
attribute fsm_encoding: string;
|
||||
attribute fsm_encoding of nstate: signal is "user";
|
||||
attribute fsm_encoding of rstate: signal is "user";
|
||||
|
||||
begin
|
||||
|
||||
debug_cmd <= rstate(3 downto 0);
|
||||
|
||||
-- Addressing is in 32 bit words - twice that of the DRAM width,
|
||||
-- so each burst of four access two system words.
|
||||
--addr_row <= address(23 downto 11);
|
||||
--addr_bank <= address(10 downto 9);
|
||||
process(r.req_addr_q)
|
||||
begin
|
||||
addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
|
||||
-- (24-2) downto (24-2 - 2 - 13 - 1)
|
||||
-- 22 downto 6
|
||||
addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
|
||||
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
|
||||
addr_col <= (others => '0');
|
||||
|
||||
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
|
||||
r.req_addr_q(8 downto 2) & "0";
|
||||
end process;
|
||||
|
||||
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
|
||||
|
||||
clock: ODDR2
|
||||
generic map (
|
||||
DDR_ALIGNMENT => "NONE",
|
||||
INIT => '0',
|
||||
SRTYPE => "ASYNC")
|
||||
port map (
|
||||
D0 => '1',
|
||||
D1 => '0',
|
||||
Q => i_DRAM_CLK,
|
||||
C0 => clock_100_delayed_3ns,
|
||||
C1 => not_clock_100_delayed_3ns,
|
||||
CE => '1',
|
||||
R => '0',
|
||||
S => '0'
|
||||
);
|
||||
|
||||
DRAM_CKE <= '1';
|
||||
|
||||
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
|
||||
|
||||
i_DRAM_CS_N <= transport rstate(3) after tOPD;
|
||||
DRAM_CS_N <= i_DRAM_CS_N;
|
||||
|
||||
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
|
||||
DRAM_RAS_N <= i_DRAM_RAS_N;
|
||||
|
||||
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
|
||||
DRAM_CAS_N <= i_DRAM_CAS_N;
|
||||
|
||||
i_DRAM_WE_N <= transport rstate(0) after tOPD;
|
||||
DRAM_WE_N <= i_DRAM_WE_N;
|
||||
|
||||
i_DRAM_ADDR <= transport r.address after tOPD;
|
||||
DRAM_ADDR <= i_DRAM_ADDR;
|
||||
|
||||
i_DRAM_BA <= transport r.bank after tOPD;
|
||||
DRAM_BA <= i_DRAM_BA;
|
||||
|
||||
i_DRAM_DQM <= transport r.dq_masks after tOPD;
|
||||
DRAM_DQM <= i_DRAM_DQM;
|
||||
|
||||
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
|
||||
data_out_valid <= r.data_out_valid;
|
||||
|
||||
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
|
||||
|
||||
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
|
||||
|
||||
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
|
||||
begin
|
||||
-- copy the existing values
|
||||
n <= r;
|
||||
nstate <= rstate;
|
||||
ndata_write <= rdata_write;
|
||||
|
||||
if req_read = '1' then
|
||||
n.rd_pending <= '1';
|
||||
if r.rd_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if req_write = '1' then
|
||||
n.wr_pending <= '1';
|
||||
if r.wr_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
-- Queue data here
|
||||
n.req_data_write <= data_in;
|
||||
n.req_mask <= data_mask;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
n.dq_masks <= "11";
|
||||
|
||||
-- first off, do we need to perform a refresh cycle ASAP?
|
||||
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
|
||||
n.rf_counter <= 0;
|
||||
n.rf_pending <= '1';
|
||||
else
|
||||
-- only start looking for refreshes outside of the initialisation state.
|
||||
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
|
||||
n.rf_counter <= r.rf_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Set the data bus into HIZ, high and low bytes masked
|
||||
--DRAM_DQ <= (others => 'Z');
|
||||
n.tristate <= '0';
|
||||
|
||||
n.init_counter <= r.init_counter-1;
|
||||
|
||||
--ndata_write <= (others => DontCareValue);
|
||||
|
||||
n.data_out_valid <= '0'; -- alvie- here, no ?
|
||||
|
||||
-- Process the FSM
|
||||
case rstate(8 downto 4) is
|
||||
when s_init_nop_id => --s_init_nop(8 downto 4) =>
|
||||
nstate <= s_init_nop;
|
||||
n.address <= (others => '0');
|
||||
n.bank <= (others => '0');
|
||||
n.act_ba <= (others => '0');
|
||||
n.rf_counter <= 0;
|
||||
-- n.data_out_valid <= '1'; -- alvie- not here
|
||||
|
||||
-- T-130, precharge all banks.
|
||||
if r.init_counter = "000000010000010" then
|
||||
nstate <= s_init_pre;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
|
||||
|
||||
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
|
||||
nstate <= s_init_ref;
|
||||
end if;
|
||||
|
||||
-- T-3, the load mode register
|
||||
if r.init_counter = 3 then
|
||||
nstate <= s_init_mrs;
|
||||
-- Mode register is as follows:
|
||||
-- resvd wr_b OpMd CAS=3 Seq bust=1
|
||||
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
|
||||
-- resvd
|
||||
n.bank <= "00";
|
||||
end if;
|
||||
|
||||
-- T-1 The switch to the FSM (first command will be a NOP
|
||||
if r.init_counter = 1 then
|
||||
nstate <= s_idle;
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Idle section
|
||||
------------------------------
|
||||
when s_idle_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
-- do we have to activate a row?
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
-- refreshes take priority over everything
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
n.rf_pending <= '0';
|
||||
end if;
|
||||
------------------------------
|
||||
-- Row activation
|
||||
-- s_ra2 is also the "idle with active row" state and provides
|
||||
-- a resting point between operations on the same row
|
||||
------------------------------
|
||||
when s_ra0_id =>
|
||||
nstate <= s_ra1;
|
||||
when s_ra1_id =>
|
||||
nstate <= s_ra2;
|
||||
|
||||
|
||||
when s_ra2_id=>
|
||||
-- we can stay in this state until we have something to do
|
||||
nstate <= s_ra2;
|
||||
n.tristate<='0';
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
else
|
||||
|
||||
-- If there is a read pending, deactivate the row
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- unless we have a read to perform on the same row? do that instead
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_rd0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks <= "00";
|
||||
n.rd_pending <= '0';
|
||||
--n.tristate<='1';
|
||||
end if;
|
||||
|
||||
-- unless we have a write on the same row? writes take priroty over reads
|
||||
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_wr0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
ndata_write <= r.req_data_write(31 downto 16);
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= not r.req_mask(3 downto 2);
|
||||
n.wr_pending <= '0';
|
||||
--n.tristate <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
end if;
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending;
|
||||
-- n.wr_pending <= r.wr_pending;
|
||||
--n.tristate <= '0';
|
||||
--end if;
|
||||
|
||||
------------------------------------------------------
|
||||
-- Deactivate the current row and return to idle state
|
||||
------------------------------------------------------
|
||||
when s_dr0_id =>
|
||||
nstate <= s_dr1;
|
||||
when s_dr1_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
------------------------------
|
||||
-- The Refresh section
|
||||
------------------------------
|
||||
when s_rf0_id =>
|
||||
nstate <= s_rf1;
|
||||
when s_rf1_id =>
|
||||
nstate <= s_rf2;
|
||||
when s_rf2_id =>
|
||||
nstate <= s_rf3;
|
||||
when s_rf3_id =>
|
||||
nstate <= s_rf4;
|
||||
when s_rf4_id =>
|
||||
nstate <= s_rf5;
|
||||
when s_rf5_id =>
|
||||
nstate <= s_idle;
|
||||
------------------------------
|
||||
-- The Write section
|
||||
------------------------------
|
||||
when s_wr0_id =>
|
||||
nstate <= s_wr3;
|
||||
n.bank <= addr_bank;
|
||||
n.address(0) <= '1';
|
||||
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.dq_masks<= not r.req_mask(1 downto 0);
|
||||
n.tristate <= '0';
|
||||
|
||||
when s_wr1_id => null;
|
||||
when s_wr2_id =>
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
|
||||
|
||||
when s_wr3_id =>
|
||||
-- Default to the idle+row active state
|
||||
nstate <= s_ra2;
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.data_out_valid<='1'; -- alvie- ack write
|
||||
n.tristate <= '0';
|
||||
n.dq_masks<= "11";
|
||||
|
||||
-- If there is a read or write then deactivate the row
|
||||
--if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
-- But if there is a read pending in the same row, do that
|
||||
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_rd0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
-- --n.act_ba <= addr_bank;
|
||||
-- n.dq_masks <= "00";
|
||||
-- n.rd_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- unless there is a write pending in the same row, do that
|
||||
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_wr0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
--n.act_ba <= addr_bank;
|
||||
-- n.dq_masks<= "00";
|
||||
-- n.wr_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- But always try and refresh if one is pending!
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_wr2; --dr0;
|
||||
--n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Read section
|
||||
------------------------------
|
||||
when s_rd0_id => -- 10001
|
||||
nstate <= s_rd1;
|
||||
n.tristate<='1';
|
||||
n.dq_masks <= "00";
|
||||
n.address(0)<='1';
|
||||
|
||||
when s_rd1_id => -- 10010
|
||||
nstate <= s_rd2;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
|
||||
nstate <= s_rd3; -- Another request came, and we can pipeline -
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
end if;
|
||||
|
||||
when s_rd2_id => -- 10011
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
when s_rd3_id => -- 10100
|
||||
|
||||
nstate <= s_rd4;
|
||||
n.dq_masks <= "00";
|
||||
n.address(0) <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
-- Data is still not ready...
|
||||
|
||||
when s_rd4_id => -- 10101
|
||||
nstate <= s_rd5;
|
||||
n.dq_masks <= "00";
|
||||
--n.address(0)<='1';
|
||||
n.tristate<='1';
|
||||
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
nstate <= s_rd5; -- Another request came, and we can pipeline -
|
||||
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
else
|
||||
nstate <= s_rd6; -- NOTE: not correct
|
||||
end if;
|
||||
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending; -- Keep request
|
||||
--end if;
|
||||
|
||||
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
|
||||
|
||||
when s_rd5_id =>
|
||||
-- If a refresh is pending then always deactivate the row
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
n.address(0) <= '1';
|
||||
nstate <= s_rd4; -- Another request came, and we can pipeline -
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd6_id =>
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks<= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd7_id =>
|
||||
nstate <= s_ra2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd8_id => null;
|
||||
|
||||
when s_rd9_id => null;
|
||||
|
||||
-- The Deactivate row during read section
|
||||
------------------------------
|
||||
when s_drdr0_id =>
|
||||
nstate <= s_drdr1;
|
||||
when s_drdr1_id =>
|
||||
nstate <= s_drdr2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
when s_drdr2_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
end if;
|
||||
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
nstate <= s_init_nop;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
--- The clock driven logic
|
||||
process (clock_100, n)
|
||||
begin
|
||||
if clock_100'event and clock_100 = '1' then
|
||||
if rst='1' then
|
||||
rstate <= (others => '0');
|
||||
r.address <= (others => '0');
|
||||
r.bank <= (others => '0');
|
||||
r.init_counter <= "100000000000000";
|
||||
-- synopsys translate_off
|
||||
r.init_counter <= "000000100000000";
|
||||
-- synopsys translate_on
|
||||
r.rf_counter <= 0;
|
||||
r.rf_pending <= '0';
|
||||
r.rd_pending <= '0';
|
||||
r.wr_pending <= '0';
|
||||
r.act_row <= (others => '0');
|
||||
r.data_out_low <= (others => '0');
|
||||
r.data_out_valid <= '0';
|
||||
r.dq_masks <= "11";
|
||||
r.tristate<='1';
|
||||
else
|
||||
r <= n;
|
||||
rstate <= nstate;
|
||||
rdata_write <= ndata_write;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dram_dq_dly <= transport dram_dq after 1.9 ns;
|
||||
|
||||
-- process (clock_100_delayed_3ns, dram_dq_dly)
|
||||
-- begin
|
||||
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
|
||||
-- captured <= dram_dq_dly;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process (clock_100)
|
||||
begin
|
||||
if falling_edge(clock_100) then
|
||||
captured <= dram_dq_dly;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
@@ -1,5 +1,5 @@
|
||||
Assembler report for spectrum
|
||||
Sat Apr 2 14:51:11 2022
|
||||
Wed Apr 6 13:58:19 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
@@ -37,7 +37,7 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Sat Apr 2 14:51:11 2022 ;
|
||||
; Assembler Status ; Successful - Wed Apr 6 13:58:19 2022 ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
@@ -162,8 +162,8 @@ Default Value : On
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------+
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; JTAG usercode ; 0x0058B9EB ;
|
||||
; Checksum ; 0x0058B9EB ;
|
||||
; JTAG usercode ; 0x0059A13C ;
|
||||
; Checksum ; 0x0059A13C ;
|
||||
+----------------+-----------------------+
|
||||
|
||||
|
||||
@@ -173,13 +173,13 @@ Default Value : On
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 14:51:09 2022
|
||||
Info: Processing started: Wed Apr 6 13:58:17 2022
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 383 megabytes
|
||||
Info: Processing ended: Sat Apr 2 14:51:11 2022
|
||||
Info: Peak virtual memory: 387 megabytes
|
||||
Info: Processing ended: Wed Apr 6 13:58:19 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
Sat Apr 2 14:51:22 2022
|
||||
Wed Apr 6 13:58:30 2022
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
EDA Netlist Writer report for spectrum
|
||||
Sat Apr 2 14:51:22 2022
|
||||
Wed Apr 6 13:58:30 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
@@ -36,7 +36,7 @@ applicable agreement for further details.
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Sat Apr 2 14:51:22 2022 ;
|
||||
; EDA Netlist Writer Status ; Successful - Wed Apr 6 13:58:30 2022 ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
@@ -88,7 +88,7 @@ applicable agreement for further details.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit EDA Netlist Writer
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 14:51:19 2022
|
||||
Info: Processing started: Wed Apr 6 13:58:26 2022
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
|
||||
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
@@ -99,9 +99,9 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
|
||||
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
|
||||
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 379 megabytes
|
||||
Info: Processing ended: Sat Apr 2 14:51:22 2022
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Peak virtual memory: 380 megabytes
|
||||
Info: Processing ended: Wed Apr 6 13:58:30 2022
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
|
||||
|
||||
|
||||
+5134
-4701
File diff suppressed because it is too large
Load Diff
@@ -1,15 +1,15 @@
|
||||
Fitter Status : Successful - Sat Apr 2 14:51:07 2022
|
||||
Fitter Status : Successful - Wed Apr 6 13:58:15 2022
|
||||
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Revision Name : spectrum
|
||||
Top-level Entity Name : spectrum
|
||||
Family : Cyclone IV E
|
||||
Device : EP4CE22F17C6
|
||||
Timing Models : Final
|
||||
Total logic elements : 2,609 / 22,320 ( 12 % )
|
||||
Total combinational functions : 2,490 / 22,320 ( 11 % )
|
||||
Dedicated logic registers : 635 / 22,320 ( 3 % )
|
||||
Total registers : 664
|
||||
Total pins : 114 / 154 ( 74 % )
|
||||
Total logic elements : 2,743 / 22,320 ( 12 % )
|
||||
Total combinational functions : 2,624 / 22,320 ( 12 % )
|
||||
Dedicated logic registers : 700 / 22,320 ( 3 % )
|
||||
Total registers : 729
|
||||
Total pins : 120 / 154 ( 78 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 524,288 / 608,256 ( 86 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Flow report for spectrum
|
||||
Sat Apr 2 14:51:22 2022
|
||||
Wed Apr 6 13:58:30 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
@@ -40,18 +40,18 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Apr 2 14:51:22 2022 ;
|
||||
; Flow Status ; Successful - Wed Apr 6 13:58:30 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE22F17C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 2,609 / 22,320 ( 12 % ) ;
|
||||
; Total combinational functions ; 2,490 / 22,320 ( 11 % ) ;
|
||||
; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ;
|
||||
; Total registers ; 664 ;
|
||||
; Total pins ; 114 / 154 ( 74 % ) ;
|
||||
; Total logic elements ; 2,743 / 22,320 ( 12 % ) ;
|
||||
; Total combinational functions ; 2,624 / 22,320 ( 12 % ) ;
|
||||
; Dedicated logic registers ; 700 / 22,320 ( 3 % ) ;
|
||||
; Total registers ; 729 ;
|
||||
; Total pins ; 120 / 154 ( 78 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 524,288 / 608,256 ( 86 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
|
||||
@@ -64,7 +64,7 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 04/02/2022 14:50:31 ;
|
||||
; Start date & time ; 04/06/2022 13:57:37 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; spectrum ;
|
||||
+-------------------+---------------------+
|
||||
@@ -74,7 +74,7 @@ applicable agreement for further details.
|
||||
; Flow Non-Default Global Settings ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Assignment Name : COMPILER_SIGNATURE_ID
|
||||
Value : 0.164890023113286
|
||||
Value : 0.164924265739740
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
@@ -91,6 +91,18 @@ Default Value : <None>
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : ENABLE_LOGIC_ANALYZER_INTERFACE
|
||||
Value : Off
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : ENABLE_SIGNALTAP
|
||||
Value : Off
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ROM: 1-PORT
|
||||
Default Value : --
|
||||
@@ -139,6 +151,12 @@ Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_NAME
|
||||
Value : ALTPLL
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
@@ -187,6 +205,12 @@ Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : IP_TOOL_VERSION
|
||||
Value : 13.1
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MAX_CORE_JUNCTION_TEMP
|
||||
Value : 85
|
||||
Default Value : --
|
||||
@@ -265,6 +289,18 @@ Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll_sdram_bb.v
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : MISC_FILE
|
||||
Value : pll_sdram.ppf
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
|
||||
Value : 1.2V
|
||||
Default Value : --
|
||||
@@ -289,11 +325,29 @@ Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : Top
|
||||
|
||||
Assignment Name : POWER_BOARD_THERMAL_MODEL
|
||||
Value : None (CONSERVATIVE)
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : POWER_PRESET_COOLING_SOLUTION
|
||||
Value : 23 MM HEAT SINK WITH 200 LFPM AIRFLOW
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : PROJECT_OUTPUT_DIRECTORY
|
||||
Value : output_files
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
|
||||
Assignment Name : USE_SIGNALTAP_FILE
|
||||
Value : output_files/stp1.stp
|
||||
Default Value : --
|
||||
Entity Name : --
|
||||
Section Id : --
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
@@ -302,40 +356,40 @@ Section Id : --
|
||||
; Flow Elapsed Time ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Module Name : Analysis & Synthesis
|
||||
Elapsed Time : 00:00:14
|
||||
Elapsed Time : 00:00:15
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 446 MB
|
||||
Total CPU Time (on all processors) : 00:00:14
|
||||
|
||||
Module Name : Fitter
|
||||
Elapsed Time : 00:00:21
|
||||
Elapsed Time : 00:00:23
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 641 MB
|
||||
Total CPU Time (on all processors) : 00:00:21
|
||||
Peak Virtual Memory : 645 MB
|
||||
Total CPU Time (on all processors) : 00:00:23
|
||||
|
||||
Module Name : Assembler
|
||||
Elapsed Time : 00:00:02
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 383 MB
|
||||
Peak Virtual Memory : 387 MB
|
||||
Total CPU Time (on all processors) : 00:00:02
|
||||
|
||||
Module Name : TimeQuest Timing Analyzer
|
||||
Elapsed Time : 00:00:03
|
||||
Elapsed Time : 00:00:04
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 445 MB
|
||||
Peak Virtual Memory : 441 MB
|
||||
Total CPU Time (on all processors) : 00:00:04
|
||||
|
||||
Module Name : EDA Netlist Writer
|
||||
Elapsed Time : 00:00:03
|
||||
Elapsed Time : 00:00:04
|
||||
Average Processors Used : 1.0
|
||||
Peak Virtual Memory : 371 MB
|
||||
Peak Virtual Memory : 368 MB
|
||||
Total CPU Time (on all processors) : 00:00:03
|
||||
|
||||
Module Name : Total
|
||||
Elapsed Time : 00:00:43
|
||||
Elapsed Time : 00:00:48
|
||||
Average Processors Used : --
|
||||
Peak Virtual Memory : --
|
||||
Total CPU Time (on all processors) : 00:00:44
|
||||
Total CPU Time (on all processors) : 00:00:46
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="e17a9ad4e9f9aba40443"/>
|
||||
<hash md5_digest_80b="52d41130cb1428434bde"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
+215
-170
@@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for spectrum
|
||||
Sat Apr 2 14:50:45 2022
|
||||
Wed Apr 6 13:57:51 2022
|
||||
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
|
||||
|
||||
@@ -24,29 +24,31 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
16. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
|
||||
17. Source assignments for ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated
|
||||
18. Source assignments for ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
|
||||
19. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
|
||||
20. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
|
||||
21. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
|
||||
22. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
|
||||
23. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component
|
||||
24. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_
|
||||
25. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_
|
||||
26. altsyncram Parameter Settings by Entity Instance
|
||||
27. altpll Parameter Settings by Entity Instance
|
||||
28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_"
|
||||
29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2"
|
||||
30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
|
||||
31. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
|
||||
32. Port Connectivity Checks: "z80_top_direct_n:z80_"
|
||||
33. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_"
|
||||
34. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_"
|
||||
35. Port Connectivity Checks: "ula:ula_"
|
||||
36. Port Connectivity Checks: "sdram_controller:sdram_"
|
||||
37. Port Connectivity Checks: "ram16:ram0"
|
||||
38. Port Connectivity Checks: "rom0:rom"
|
||||
39. Elapsed Time Per Partition
|
||||
40. Analysis & Synthesis Messages
|
||||
41. Analysis & Synthesis Suppressed Messages
|
||||
19. Parameter Settings for User Entity Instance: debouncer:debounce_turbo
|
||||
20. Parameter Settings for User Entity Instance: debouncer:debounce_autofire
|
||||
21. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
|
||||
22. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component
|
||||
23. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component
|
||||
24. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
|
||||
25. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component
|
||||
26. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_
|
||||
27. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_
|
||||
28. altsyncram Parameter Settings by Entity Instance
|
||||
29. altpll Parameter Settings by Entity Instance
|
||||
30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_"
|
||||
31. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2"
|
||||
32. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux"
|
||||
33. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_"
|
||||
34. Port Connectivity Checks: "z80_top_direct_n:z80_"
|
||||
35. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_"
|
||||
36. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_"
|
||||
37. Port Connectivity Checks: "ula:ula_"
|
||||
38. Port Connectivity Checks: "sdram_controller:sdram_"
|
||||
39. Port Connectivity Checks: "ram16:ram0"
|
||||
40. Port Connectivity Checks: "rom0:rom"
|
||||
41. Elapsed Time Per Partition
|
||||
42. Analysis & Synthesis Messages
|
||||
43. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
||||
|
||||
@@ -72,16 +74,16 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+--------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Apr 2 14:50:45 2022 ;
|
||||
; Analysis & Synthesis Status ; Successful - Wed Apr 6 13:57:51 2022 ;
|
||||
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
|
||||
; Revision Name ; spectrum ;
|
||||
; Top-level Entity Name ; spectrum ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Total logic elements ; 2,751 ;
|
||||
; Total combinational functions ; 2,480 ;
|
||||
; Dedicated logic registers ; 649 ;
|
||||
; Total registers ; 649 ;
|
||||
; Total pins ; 114 ;
|
||||
; Total logic elements ; 2,885 ;
|
||||
; Total combinational functions ; 2,614 ;
|
||||
; Dedicated logic registers ; 714 ;
|
||||
; Total registers ; 714 ;
|
||||
; Total pins ; 120 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 524,288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
@@ -749,6 +751,12 @@ File Type : User Wizard-Generated File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram_clk_gen.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : debouncer.v
|
||||
Used in Netlist : yes
|
||||
File Type : User Verilog HDL File
|
||||
File Name with Absolute Path : /home/benny/work/fpga/spectrum/debouncer.v
|
||||
Library :
|
||||
|
||||
File Name with User-Entered Path : cpu/toplevel/globals.vh
|
||||
Used in Netlist : yes
|
||||
File Type : Auto-Found Unspecified File
|
||||
@@ -955,32 +963,32 @@ Library :
|
||||
+---------------------------------------------+---------------------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+---------------------------------+
|
||||
; Estimated Total logic elements ; 2,751 ;
|
||||
; Estimated Total logic elements ; 2,885 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 2480 ;
|
||||
; Total combinational functions ; 2614 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 1776 ;
|
||||
; -- 3 input functions ; 416 ;
|
||||
; -- <=2 input functions ; 288 ;
|
||||
; -- 4 input functions ; 1835 ;
|
||||
; -- 3 input functions ; 421 ;
|
||||
; -- <=2 input functions ; 358 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 2404 ;
|
||||
; -- arithmetic mode ; 76 ;
|
||||
; -- normal mode ; 2482 ;
|
||||
; -- arithmetic mode ; 132 ;
|
||||
; ; ;
|
||||
; Total registers ; 649 ;
|
||||
; -- Dedicated logic registers ; 649 ;
|
||||
; Total registers ; 714 ;
|
||||
; -- Dedicated logic registers ; 714 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 114 ;
|
||||
; I/O pins ; 120 ;
|
||||
; Total memory bits ; 524288 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 2 ;
|
||||
; -- PLLs ; 2 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ;
|
||||
; Maximum fan-out ; 436 ;
|
||||
; Total fan-out ; 12502 ;
|
||||
; Average fan-out ; 3.63 ;
|
||||
; Maximum fan-out ; 455 ;
|
||||
; Total fan-out ; 13090 ;
|
||||
; Average fan-out ; 3.58 ;
|
||||
+---------------------------------------------+---------------------------------+
|
||||
|
||||
|
||||
@@ -988,17 +996,41 @@ Library :
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Compilation Hierarchy Node : |spectrum
|
||||
LC Combinationals : 2480 (108)
|
||||
LC Registers : 649 (0)
|
||||
LC Combinationals : 2614 (124)
|
||||
LC Registers : 714 (21)
|
||||
Memory Bits : 524288
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 114
|
||||
Pins : 120
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |debouncer:debounce_autofire|
|
||||
LC Combinationals : 34 (34)
|
||||
LC Registers : 22 (22)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|debouncer:debounce_autofire
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |debouncer:debounce_turbo|
|
||||
LC Combinationals : 34 (34)
|
||||
LC Registers : 22 (22)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|debouncer:debounce_turbo
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram16:ram0|
|
||||
LC Combinationals : 2 (0)
|
||||
LC Registers : 2 (0)
|
||||
@@ -1048,7 +1080,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ram32:ram1|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1060,7 +1092,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (0)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1072,7 +1104,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated|
|
||||
LC Combinationals : 12 (0)
|
||||
LC Combinationals : 22 (0)
|
||||
LC Registers : 4 (4)
|
||||
Memory Bits : 262144
|
||||
DSP Elements : 0
|
||||
@@ -1108,7 +1140,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |mux_6nb:mux2|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Combinationals : 14 (14)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1156,7 +1188,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |sdram_controller:sdram_|
|
||||
LC Combinationals : 217 (217)
|
||||
LC Combinationals : 226 (226)
|
||||
LC Registers : 57 (57)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1204,7 +1236,7 @@ Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdr
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |ula:ula_|
|
||||
LC Combinationals : 418 (4)
|
||||
LC Combinationals : 436 (4)
|
||||
LC Registers : 224 (7)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1240,7 +1272,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |i2s_intf:i2s_intf_|
|
||||
LC Combinationals : 68 (68)
|
||||
LC Combinationals : 67 (67)
|
||||
LC Registers : 42 (42)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1312,7 +1344,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_|
|
||||
LC Combinationals : 148 (148)
|
||||
LC Combinationals : 167 (167)
|
||||
LC Registers : 43 (43)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1324,7 +1356,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |z80_top_direct_n:z80_|
|
||||
LC Combinationals : 1723 (2)
|
||||
LC Combinationals : 1736 (2)
|
||||
LC Registers : 362 (1)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1336,7 +1368,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |address_latch:address_latch_|
|
||||
LC Combinationals : 45 (16)
|
||||
LC Combinationals : 48 (16)
|
||||
LC Registers : 16 (16)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1348,7 +1380,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec|
|
||||
LC Combinationals : 29 (12)
|
||||
LC Combinationals : 32 (15)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1444,7 +1476,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu:alu_|
|
||||
LC Combinationals : 128 (75)
|
||||
LC Combinationals : 130 (76)
|
||||
LC Registers : 20 (20)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1468,7 +1500,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_core:b2v_core|
|
||||
LC Combinationals : 20 (0)
|
||||
LC Combinationals : 21 (0)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1492,7 +1524,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1|
|
||||
LC Combinationals : 5 (5)
|
||||
LC Combinationals : 4 (4)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1516,7 +1548,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3|
|
||||
LC Combinationals : 3 (3)
|
||||
LC Combinationals : 5 (5)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1612,7 +1644,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |alu_flags:alu_flags_|
|
||||
LC Combinationals : 61 (61)
|
||||
LC Combinationals : 59 (59)
|
||||
LC Registers : 10 (10)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1647,18 +1679,6 @@ Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |control_pins_n:control_pins_|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_pins:data_pins_|
|
||||
LC Combinationals : 9 (9)
|
||||
LC Registers : 8 (8)
|
||||
@@ -1671,20 +1691,8 @@ Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_switch:sw2_|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
DSP 9x9 : 0
|
||||
DSP 18x18 : 0
|
||||
Pins : 0
|
||||
Virtual Pins : 0
|
||||
Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |data_switch_mask:sw1_|
|
||||
LC Combinationals : 4 (4)
|
||||
LC Combinationals : 5 (5)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1696,7 +1704,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |decode_state:decode_state_|
|
||||
LC Combinationals : 11 (11)
|
||||
LC Combinationals : 12 (12)
|
||||
LC Registers : 6 (6)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1708,7 +1716,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |execute:execute_|
|
||||
LC Combinationals : 926 (926)
|
||||
LC Combinationals : 934 (934)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1720,7 +1728,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |interrupts:interrupts_|
|
||||
LC Combinationals : 10 (10)
|
||||
LC Combinationals : 11 (11)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1768,7 +1776,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |pla_decode:pla_decode_|
|
||||
LC Combinationals : 74 (74)
|
||||
LC Combinationals : 71 (71)
|
||||
LC Registers : 0 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1780,7 +1788,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_deco
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_control:reg_control_|
|
||||
LC Combinationals : 30 (30)
|
||||
LC Combinationals : 29 (29)
|
||||
LC Registers : 4 (4)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1792,7 +1800,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_file:reg_file_|
|
||||
LC Combinationals : 281 (270)
|
||||
LC Combinationals : 286 (277)
|
||||
LC Registers : 224 (0)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1828,7 +1836,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi|
|
||||
LC Combinationals : 8 (8)
|
||||
LC Combinationals : 6 (6)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1900,7 +1908,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_de2_hi|
|
||||
LC Combinationals : 0 (0)
|
||||
LC Combinationals : 2 (2)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -1984,7 +1992,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo|
|
||||
LC Combinationals : 1 (1)
|
||||
LC Combinationals : 0 (0)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -2128,7 +2136,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|
|
||||
Library Name : work
|
||||
|
||||
Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo|
|
||||
LC Combinationals : 2 (2)
|
||||
LC Combinationals : 1 (1)
|
||||
LC Registers : 8 (8)
|
||||
Memory Bits : 0
|
||||
DSP Elements : 0
|
||||
@@ -2365,12 +2373,12 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 649 ;
|
||||
; Number of registers using Synchronous Clear ; 13 ;
|
||||
; Number of registers using Synchronous Load ; 34 ;
|
||||
; Total registers ; 714 ;
|
||||
; Number of registers using Synchronous Clear ; 55 ;
|
||||
; Number of registers using Synchronous Load ; 35 ;
|
||||
; Number of registers using Asynchronous Clear ; 221 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 464 ;
|
||||
; Number of registers using Clock Enable ; 481 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@@ -2380,16 +2388,16 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
+----------------------------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------------------------+---------+
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 150 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 3 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 144 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 5 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[4] ; 2 ;
|
||||
; ula:ula_|i2s_intf:i2s_intf_|bdivider[2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] ; 2 ;
|
||||
@@ -2397,22 +2405,22 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ;
|
||||
@@ -2425,24 +2433,23 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ;
|
||||
; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ;
|
||||
; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 64 ;
|
||||
; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ;
|
||||
; z80_top_direct_n:z80_|fpga_reset ; 2 ;
|
||||
; sdram_controller:sdram_|r.init_counter[3] ; 3 ;
|
||||
; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ;
|
||||
; ula:ula_|i2c_loader:i2c_loader_|scl_out ; 2 ;
|
||||
; ula:ula_|i2c_loader:i2c_loader_|sda_out ; 3 ;
|
||||
; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ;
|
||||
; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ;
|
||||
; Total number of inverted registers = 62 ; ;
|
||||
; Total number of inverted registers = 61 ; ;
|
||||
+----------------------------------------------------------+---------+
|
||||
|
||||
|
||||
@@ -2455,7 +2462,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 10 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[5]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[8]
|
||||
|
||||
Multiplexer Inputs : 3:1
|
||||
Bus Width : 4 bits
|
||||
@@ -2463,7 +2470,7 @@ Baseline Area : 8 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 4 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0]
|
||||
|
||||
Multiplexer Inputs : 4:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2479,7 +2486,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 10 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[3]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[8]
|
||||
|
||||
Multiplexer Inputs : 6:1
|
||||
Bus Width : 5 bits
|
||||
@@ -2487,7 +2494,7 @@ Baseline Area : 20 LEs
|
||||
Area if Restructured : 5 LEs
|
||||
Saving if Restructured : 15 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
|
||||
|
||||
Multiplexer Inputs : 5:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2503,7 +2510,7 @@ Baseline Area : 42 LEs
|
||||
Area if Restructured : 14 LEs
|
||||
Saving if Restructured : 28 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
|
||||
|
||||
Multiplexer Inputs : 5:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2511,7 +2518,7 @@ Baseline Area : 9 LEs
|
||||
Area if Restructured : 3 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
|
||||
|
||||
Multiplexer Inputs : 10:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2519,7 +2526,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 2 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[11]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[12]
|
||||
|
||||
Multiplexer Inputs : 10:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2527,7 +2534,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 2 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[8]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[9]
|
||||
|
||||
Multiplexer Inputs : 32:1
|
||||
Bus Width : 5 bits
|
||||
@@ -2535,7 +2542,7 @@ Baseline Area : 105 LEs
|
||||
Area if Restructured : 0 LEs
|
||||
Saving if Restructured : 105 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[1]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[2]
|
||||
|
||||
Multiplexer Inputs : 8:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2543,7 +2550,7 @@ Baseline Area : 10 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
|
||||
|
||||
Multiplexer Inputs : 32:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2559,7 +2566,7 @@ Baseline Area : 80 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 76 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[8]
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[9]
|
||||
|
||||
Multiplexer Inputs : 31:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2575,7 +2582,7 @@ Baseline Area : 12 LEs
|
||||
Area if Restructured : 4 LEs
|
||||
Saving if Restructured : 8 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 3 bits
|
||||
@@ -2583,7 +2590,7 @@ Baseline Area : 18 LEs
|
||||
Area if Restructured : 3 LEs
|
||||
Saving if Restructured : 15 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[2]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|nbit[0]
|
||||
|
||||
Multiplexer Inputs : 27:1
|
||||
Bus Width : 4 bits
|
||||
@@ -2591,7 +2598,7 @@ Baseline Area : 72 LEs
|
||||
Area if Restructured : 52 LEs
|
||||
Saving if Restructured : 20 LEs
|
||||
Registered : Yes
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
|
||||
|
||||
Multiplexer Inputs : 3:1
|
||||
Bus Width : 16 bits
|
||||
@@ -2623,15 +2630,7 @@ Baseline Area : 9 LEs
|
||||
Area if Restructured : 6 LEs
|
||||
Saving if Restructured : 3 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[2]
|
||||
|
||||
Multiplexer Inputs : 6:1
|
||||
Bus Width : 2 bits
|
||||
Baseline Area : 8 LEs
|
||||
Area if Restructured : 6 LEs
|
||||
Saving if Restructured : 2 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Mux0
|
||||
Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[1]
|
||||
|
||||
Multiplexer Inputs : 4:1
|
||||
Bus Width : 8 bits
|
||||
@@ -2641,13 +2640,21 @@ Saving if Restructured : 8 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|sdram_controller:sdram_|Mux74
|
||||
|
||||
Multiplexer Inputs : 8:1
|
||||
Bus Width : 6 bits
|
||||
Baseline Area : 30 LEs
|
||||
Area if Restructured : 24 LEs
|
||||
Saving if Restructured : 6 LEs
|
||||
Multiplexer Inputs : 7:1
|
||||
Bus Width : 2 bits
|
||||
Baseline Area : 8 LEs
|
||||
Area if Restructured : 8 LEs
|
||||
Saving if Restructured : 0 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Selector0
|
||||
Example Multiplexer Output : |spectrum|Selector4
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 5 bits
|
||||
Baseline Area : 30 LEs
|
||||
Area if Restructured : 20 LEs
|
||||
Saving if Restructured : 10 LEs
|
||||
Registered : No
|
||||
Example Multiplexer Output : |spectrum|Selector14
|
||||
|
||||
Multiplexer Inputs : 9:1
|
||||
Bus Width : 2 bits
|
||||
@@ -2701,6 +2708,28 @@ To : -
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: debouncer:debounce_turbo ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : c_DEBOUNCE_LIMIT
|
||||
Value : 1100000
|
||||
Type : Signed Integer
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: debouncer:debounce_autofire ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
Parameter Name : c_DEBOUNCE_LIMIT
|
||||
Value : 1100000
|
||||
Type : Signed Integer
|
||||
+--------------------------------------------------------------------------------+
|
||||
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
|
||||
+--------------------------------------------------------------------------------+
|
||||
@@ -6580,7 +6609,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:11 ;
|
||||
; Top ; 00:00:12 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
@@ -6590,7 +6619,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Info: Processing started: Sat Apr 2 14:50:31 2022
|
||||
Info: Processing started: Wed Apr 6 13:57:36 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
|
||||
@@ -6708,10 +6737,31 @@ Info (12021): Found 2 design units, including 1 entities, in source file sdram.v
|
||||
Info (12023): Found entity 1: sdram_controller
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
|
||||
Info (12023): Found entity 1: sdram_clk_gen
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126)
|
||||
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128)
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram.v
|
||||
Info (12023): Found entity 1: sdram
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_ctrl.v
|
||||
Info (12023): Found entity 1: SDRAM_ctrl
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file sdram_controller.v
|
||||
Info (12023): Found entity 1: sdram_controller_new
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file pll_sdram.v
|
||||
Info (12023): Found entity 1: pll_sdram
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file debouncer.v
|
||||
Info (12023): Found entity 1: debouncer
|
||||
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
|
||||
Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver
|
||||
Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver
|
||||
Warning (10034): Output port "GPIO_1[33..32]" at spectrum.sv(20) has no driver
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(114): object "is_io_read_requested" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(115): object "is_io_write_requested" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(118): object "is_rom_address" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(133): object "kempston_last_fire_state" assigned a value but never read
|
||||
Warning (10036): Verilog HDL or VHDL warning at spectrum.sv(231): object "sdram_write_request" assigned a value but never read
|
||||
Warning (10230): Verilog HDL assignment warning at spectrum.sv(141): truncated value with size 32 to match size of target (18)
|
||||
Info (12128): Elaborating entity "debouncer" for hierarchy "debouncer:debounce_turbo"
|
||||
Warning (10230): Verilog HDL assignment warning at debouncer.v(13): truncated value with size 32 to match size of target (21)
|
||||
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
|
||||
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
|
||||
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
|
||||
@@ -7006,10 +7056,10 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]" to the node "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "RamWE" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "sdram_read_request" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nWR" to the node "RamWE" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal1" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal1" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal5" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal5" into an OR gate
|
||||
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[0]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[0]" into an OR gate
|
||||
Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[7]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[7]" into an OR gate
|
||||
@@ -7086,35 +7136,30 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
|
||||
Info (13000): Registers with preset signals will power-up high
|
||||
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "LED[1]" is stuck at GND
|
||||
Warning (13410): Pin "LED[4]" is stuck at GND
|
||||
Warning (13410): Pin "LED[5]" is stuck at GND
|
||||
Warning (13410): Pin "LED[6]" is stuck at GND
|
||||
Warning (13410): Pin "LED[7]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_1[24]" is stuck at VCC
|
||||
Warning (13410): Pin "GPIO_1[32]" is stuck at GND
|
||||
Warning (13410): Pin "GPIO_1[33]" is stuck at GND
|
||||
Warning (13410): Pin "DRAM_CKE" is stuck at VCC
|
||||
Warning (13410): Pin "DRAM_CS_N" is stuck at GND
|
||||
Warning (13410): Pin "kempston_gnd" is stuck at GND
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
|
||||
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||||
Warning (21074): Design contains 3 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "SW[0]"
|
||||
Warning (15610): No output dependent on input pin "SW[2]"
|
||||
Warning (15610): No output dependent on input pin "SW[3]"
|
||||
Info (21057): Implemented 3006 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 11 input pins
|
||||
Info (21059): Implemented 85 output pins
|
||||
Info (21057): Implemented 3146 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 18 input pins
|
||||
Info (21059): Implemented 84 output pins
|
||||
Info (21060): Implemented 18 bidirectional pins
|
||||
Info (21061): Implemented 2826 logic cells
|
||||
Info (21061): Implemented 2960 logic cells
|
||||
Info (21064): Implemented 64 RAM segments
|
||||
Info (21065): Implemented 2 PLLs
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 117 warnings
|
||||
Info: Peak virtual memory: 446 megabytes
|
||||
Info: Processing ended: Sat Apr 2 14:50:45 2022
|
||||
Info: Elapsed time: 00:00:14
|
||||
Info: Processing ended: Wed Apr 6 13:57:51 2022
|
||||
Info: Elapsed time: 00:00:15
|
||||
Info: Total CPU time (on all processors): 00:00:15
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,3 @@
|
||||
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(19): object "nRESET" differs only in case from object "nreset" in the same scope
|
||||
Info (10281): Verilog HDL Declaration information at z80_top_direct_n.v(22): object "CLK" differs only in case from object "clk" in the same scope
|
||||
Warning (10273): Verilog HDL warning at sdram_controller.v(166): extended using "x" or "z"
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Analysis & Synthesis Status : Successful - Sat Apr 2 14:50:45 2022
|
||||
Analysis & Synthesis Status : Successful - Wed Apr 6 13:57:51 2022
|
||||
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
Revision Name : spectrum
|
||||
Top-level Entity Name : spectrum
|
||||
Family : Cyclone IV E
|
||||
Total logic elements : 2,751
|
||||
Total combinational functions : 2,480
|
||||
Dedicated logic registers : 649
|
||||
Total registers : 649
|
||||
Total pins : 114
|
||||
Total logic elements : 2,885
|
||||
Total combinational functions : 2,614
|
||||
Dedicated logic registers : 714
|
||||
Total registers : 714
|
||||
Total pins : 120
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 524,288
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
|
||||
@@ -71,8 +71,8 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
|
||||
VCCIO8 : A1 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
|
||||
kempston[1] : A4 : input : 3.3-V LVTTL : : 8 : Y
|
||||
kempston[3] : A5 : input : 3.3-V LVTTL : : 8 : Y
|
||||
buzzer_out : A6 : output : 3.3-V LVTTL : : 8 : Y
|
||||
AUD_XCK : A7 : output : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : A8 : : : : 8 :
|
||||
@@ -86,9 +86,9 @@ LED[0] : A15 : output : 3.3-V LVTTL :
|
||||
VCCIO7 : A16 : power : : 3.3V : 7 :
|
||||
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
|
||||
GND : B2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
|
||||
kempston_gnd : B3 : output : 3.3-V LVTTL : : 8 : Y
|
||||
kempston[0] : B4 : input : 3.3-V LVTTL : : 8 : Y
|
||||
kempston[2] : B5 : input : 3.3-V LVTTL : : 8 : Y
|
||||
raw_loader_in : B6 : input : 3.3-V LVTTL : : 8 : Y
|
||||
PS2_DAT : B7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
GND+ : B8 : : : : 8 :
|
||||
@@ -120,7 +120,7 @@ LED[4] : D1 : output : 3.3-V LVTTL :
|
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
|
||||
VCCD_PLL3 : D4 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
|
||||
kempston[4] : D5 : input : 3.3-V LVTTL : : 8 : Y
|
||||
PS2_CLK : D6 : input : 3.3-V LVTTL : : 8 : Y
|
||||
GND : D7 : gnd : : : :
|
||||
AUD_ADCDAT : D8 : input : 3.3-V LVTTL : : 8 : Y
|
||||
@@ -208,8 +208,8 @@ GND : J9 : gnd : :
|
||||
GND : J10 : gnd : : : :
|
||||
GND : J11 : gnd : : : :
|
||||
VCCINT : J12 : power : : 1.2V : :
|
||||
GPIO_1[32] : J13 : output : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y
|
||||
turbo_button : J13 : input : 3.3-V LVTTL : : 5 : Y
|
||||
kempston_autofire_button : J14 : input : 3.3-V LVTTL : : 5 : Y
|
||||
KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y
|
||||
GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y
|
||||
DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
|
||||
Binary file not shown.
+26614
-25278
File diff suppressed because it is too large
Load Diff
@@ -3,51 +3,51 @@ TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
|
||||
Slack : -18.571
|
||||
TNS : -821.372
|
||||
Slack : -18.476
|
||||
TNS : -808.800
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -7.747
|
||||
TNS : -287.138
|
||||
Slack : -7.513
|
||||
TNS : -282.972
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.731
|
||||
TNS : -41.432
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.915
|
||||
TNS : -2.915
|
||||
Slack : -4.734
|
||||
TNS : -42.279
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 3.503
|
||||
Slack : 3.261
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.342
|
||||
Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 70.299
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.342
|
||||
Slack : 0.344
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.357
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.357
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 0.359
|
||||
Slack : 0.358
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
|
||||
Slack : 0.373
|
||||
Slack : 0.382
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -6.212
|
||||
TNS : -460.730
|
||||
Slack : -6.210
|
||||
TNS : -460.961
|
||||
|
||||
Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 3.666
|
||||
Slack : 3.689
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
@@ -63,39 +63,35 @@ Slack : 19.602
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 20.597
|
||||
Slack : 20.593
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.503
|
||||
Slack : 35.490
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -17.727
|
||||
TNS : -781.205
|
||||
Slack : -17.646
|
||||
TNS : -768.789
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -6.896
|
||||
TNS : -255.894
|
||||
Slack : -6.953
|
||||
TNS : -254.832
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.422
|
||||
TNS : -38.759
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.786
|
||||
TNS : -2.786
|
||||
Slack : -4.416
|
||||
TNS : -39.535
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 4.148
|
||||
Slack : 3.951
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.298
|
||||
Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 70.438
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.298
|
||||
Slack : 0.300
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
@@ -106,16 +102,20 @@ Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_ge
|
||||
Slack : 0.312
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.312
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.339
|
||||
Slack : 0.333
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -5.735
|
||||
TNS : -424.927
|
||||
Slack : -5.734
|
||||
TNS : -425.150
|
||||
|
||||
Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 3.339
|
||||
Slack : 3.370
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
@@ -123,51 +123,43 @@ Slack : 4.748
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
Slack : 9.489
|
||||
Slack : 9.488
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 19.596
|
||||
Slack : 19.598
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 20.591
|
||||
Slack : 20.589
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.491
|
||||
Slack : 35.487
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
|
||||
Slack : -15.243
|
||||
TNS : -641.328
|
||||
Slack : -15.170
|
||||
TNS : -635.207
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : -4.921
|
||||
TNS : -171.346
|
||||
Slack : -5.647
|
||||
TNS : -193.116
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -3.770
|
||||
TNS : -34.841
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : -2.784
|
||||
TNS : -2.784
|
||||
Slack : -3.810
|
||||
TNS : -35.303
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 6.261
|
||||
Slack : 6.131
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.098
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.177
|
||||
Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 70.800
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 0.177
|
||||
Slack : 0.179
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
@@ -178,16 +170,24 @@ Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll
|
||||
Slack : 0.186
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 0.186
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
|
||||
Slack : 0.201
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : -4.684
|
||||
TNS : -358.844
|
||||
TNS : -359.024
|
||||
|
||||
Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
|
||||
Slack : 2.507
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]'
|
||||
Slack : 4.783
|
||||
Slack : 4.784
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
|
||||
@@ -203,7 +203,7 @@ Slack : 20.600
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
|
||||
Slack : 35.535
|
||||
Slack : 35.525
|
||||
TNS : 0.000
|
||||
|
||||
------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
<session jtag_chain="USB-Blaster [5-4.2]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
|
||||
<display_tree gui_logging_enabled="0">
|
||||
<display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
|
||||
</display_tree>
|
||||
<instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
|
||||
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
|
||||
<signal_set global_temp="1" is_expanded="true" name="signal_set: 2022/04/05 10:32:38 #0">
|
||||
<clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
|
||||
<config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
|
||||
<top_entity/>
|
||||
<signal_vec>
|
||||
<trigger_input_vec>
|
||||
<wire name="current_state.state_init" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_init" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="CLOCK_50" tap_mode="probeonly"/>
|
||||
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
|
||||
</trigger_input_vec>
|
||||
<data_input_vec>
|
||||
<wire name="current_state.state_init" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_init" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="CLOCK_50" tap_mode="probeonly"/>
|
||||
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
|
||||
</data_input_vec>
|
||||
<storage_qualifier_input_vec>
|
||||
<wire name="current_state.state_init" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read" tap_mode="classic"/>
|
||||
<wire name="current_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write" tap_mode="classic"/>
|
||||
<wire name="current_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_init" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read" tap_mode="classic"/>
|
||||
<wire name="next_state.state_read_idle" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write" tap_mode="classic"/>
|
||||
<wire name="next_state.state_write_idle" tap_mode="classic"/>
|
||||
<wire name="CLOCK_50" tap_mode="probeonly"/>
|
||||
<wire name="sdram_write_request~1" tap_mode="probeonly"/>
|
||||
</storage_qualifier_input_vec>
|
||||
</signal_vec>
|
||||
<presentation>
|
||||
<unified_setup_data_view>
|
||||
<node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
|
||||
<node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
|
||||
<node mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<node data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
|
||||
<node data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
|
||||
<node data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
|
||||
<node data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
|
||||
<node data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
|
||||
</node>
|
||||
<node mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<node data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
|
||||
<node data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
|
||||
<node data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
|
||||
<node data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
|
||||
<node data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
|
||||
</node>
|
||||
</unified_setup_data_view>
|
||||
<data_view>
|
||||
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
|
||||
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
|
||||
<bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
|
||||
<net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
|
||||
<net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
|
||||
<net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
|
||||
<net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
|
||||
</bus>
|
||||
<bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
|
||||
<net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
|
||||
<net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
|
||||
<net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
|
||||
<net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
|
||||
</bus>
|
||||
</data_view>
|
||||
<setup_view>
|
||||
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
|
||||
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
|
||||
<bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
|
||||
<net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
|
||||
<net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
|
||||
<net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
|
||||
<net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
|
||||
</bus>
|
||||
<bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
|
||||
<net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
|
||||
<net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
|
||||
<net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
|
||||
<net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
|
||||
<net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
|
||||
</bus>
|
||||
</setup_view>
|
||||
<trigger_in_editor/>
|
||||
<trigger_out_editor/>
|
||||
</presentation>
|
||||
<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2022/04/05 10:37:05 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
|
||||
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
|
||||
<events use_custom_flow_control="no">
|
||||
<level editor="basic_or" enabled="yes" name="condition1" type="advanced">
|
||||
<power_up enabled="yes">
|
||||
<power_up_expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
|
||||
</power_up_expression>
|
||||
</power_up>
|
||||
<expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
|
||||
</expression>
|
||||
<op_node/>
|
||||
</level>
|
||||
</events>
|
||||
<storage_qualifier_events>
|
||||
<transitional>111111111111
|
||||
<pwr_up_transitional>111111111111</pwr_up_transitional>
|
||||
</transitional>
|
||||
<storage_qualifier_level type="basic">
|
||||
<power_up>
|
||||
</power_up>
|
||||
<op_node/>
|
||||
</storage_qualifier_level>
|
||||
<storage_qualifier_level type="basic">
|
||||
<power_up>
|
||||
</power_up>
|
||||
<op_node/>
|
||||
</storage_qualifier_level>
|
||||
<storage_qualifier_level type="basic">
|
||||
<power_up>
|
||||
</power_up>
|
||||
<op_node/>
|
||||
</storage_qualifier_level>
|
||||
</storage_qualifier_events>
|
||||
</trigger>
|
||||
</signal_set>
|
||||
<position_info>
|
||||
<single attribute="active tab" value="0"/>
|
||||
</position_info>
|
||||
</instance>
|
||||
<mnemonics>
|
||||
<table name="current_state_table" width="5">
|
||||
<symbol name="state_init" value="00001"/>
|
||||
<symbol name="state_read" value="00010"/>
|
||||
<symbol name="state_read_idle" value="00100"/>
|
||||
<symbol name="state_write" value="01000"/>
|
||||
<symbol name="state_write_idle" value="10000"/>
|
||||
</table>
|
||||
<table name="next_state_table" width="5">
|
||||
<symbol name="state_init" value="00001"/>
|
||||
<symbol name="state_read" value="00010"/>
|
||||
<symbol name="state_read_idle" value="00100"/>
|
||||
<symbol name="state_write" value="01000"/>
|
||||
<symbol name="state_write_idle" value="10000"/>
|
||||
</table>
|
||||
</mnemonics>
|
||||
<global_info>
|
||||
<single attribute="active instance" value="0"/>
|
||||
<single attribute="config widget visible" value="1"/>
|
||||
<single attribute="data log widget visible" value="1"/>
|
||||
<single attribute="hierarchy widget visible" value="1"/>
|
||||
<single attribute="instance widget visible" value="1"/>
|
||||
<single attribute="jtag widget visible" value="1"/>
|
||||
<multi attribute="column width" size="23" value="34,34,200,74,68,70,88,88,98,98,88,88,643,101,101,101,101,101,101,101,101,107,78"/>
|
||||
<multi attribute="frame size" size="2" value="3840,2032"/>
|
||||
<multi attribute="jtag widget size" size="2" value="715,200"/>
|
||||
</global_info>
|
||||
<static_plugin_mnemonics/>
|
||||
</session>
|
||||
Reference in New Issue
Block a user